JPS5893270A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a smiecondutor device of high density by selectively forming connecting members on the desired element regions of a substrate, burying the peripheries with isolated insulating films, forming semiconductor films which are contacted with the members, and forming the desired elements thereat. CONSTITUTION:Connecting members 141, 142 which are formed of polycrystalline Si having a size smaller than desired diffused regions 121, 122 of elements are formed on the regions 121, 122 of a semiconductor substrate 11 formed with the diffused regions 121, 122. Then, the portion between the members is buried with an SiO2 film 151, the overall surface is formed to be flat, polycrystalline Si films 181, 182 which are respectively contacted with the members 141, 142 while extending at the periphery of the film 151, and the portion between the films 181 and 182 is buried with an SiO2 film 152. Subsequently, a semidoncudtor film is covered on the overall surface while contacting with films 181, 182, and desired element regiona are formed thereat.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which semiconductor elements are stacked in multiple layers.

[Technical background of the invention]

Recently, attempts have been made to achieve high density, high integration, and high functionality of semiconductor devices by stacking semiconductor elements on the same substrate. In this case, it is desirable that the isolation insulating film be thicker in order to provide sufficient isolation between the stacked semiconductor elements, and therefore processing technology that connects the stacked elements through minute openings is important. This becomes a problem.

[Problems with background technology]

In order to form sufficiently small openings with good dimensional accuracy for the purpose of achieving high integration, it is not only difficult to form holes and turns, but it is also necessary to use a dry etching method with good processing accuracy. , the cross section has a cut shape. As a result, the connecting conductor material layered by the sputtering method or CV l) method does not adhere uniformly to the side surface of the opening, resulting in overhang or a sharp, nearly vertical shape. , is called a role-breaker (Jl,
Elephants may appear. Therefore, in this method, miniaturization of the opening and formation of ridge wiring are critical. In addition, the unevenness on the surface of the semiconductor substrate on which the element is formed makes it extremely difficult to process the semiconductor 8q to be end-layered on this L.

The surface irregularities impair the uniformity and flatness of the fIf layer, and deteriorate the resolution of the resist pattern, for example. Furthermore, these irregularities become larger as the semiconductor chip is removed, making it impossible to achieve the original goal of high integration and high density due to processing difficulties. This surface unevenness is caused by the formation of the openings and is not dependent on the processing technique. In other words, in the conventional method, this difference in height always occurs.

[Purpose of the invention]

The present invention has been made in view of point L, and its purpose is to solve all the problems of the conventional method by improving the connection between the semi-dedicated elements 1flI. Another object of the present invention is to provide a method for manufacturing a semiconductor device that achieves a sieving function with high density and high efficiency and has a high yield.

[Overview of illusion]

In the present invention, prior to providing a separating and insulating film on a half-arm substrate on which an element region is formed, a connecting member is selectively left on a desired element ring to be connected. An isolation insulating film is provided in the area that is not covered by the film, and a semiconductor film on which a semiconductor element is to be formed is formed on this isolation insulating film in contact with the connecting member. Furthermore, the object of the present invention can be more completely achieved by subjecting the semiconductor film to mrm and master turning, and then processing the substrate surface into a flat surface with little difference in height. After patterning the semiconductor film, an insulating film is applied to the entire surface.
This can be achieved by applying an organic film thereon using a spin code method so that the surface is approximately flat, and uniformly etching the organic film and the insulating film under etching conditions where the etching rates of both are equal.

〔Effect of the invention〕

According to the present invention, the bonding member is left in place prior to forming the isolation insulating film, and then the isolation insulating film is provided, so that the technical difficulty of forming fine openings is solved. Compared to R-turn, it is easier to form resist holes and turns to form fine remaining holes and turns. The difficulty is solved by forming a fi1 layer of the semiconductor film by directly contacting the connecting member selectively left, without using the method of forming a fine opening and connecting the lower part with a conductor wiring.
Furthermore, by applying a treatment to flatten the surface,
The unevenness caused by stacking elements can be reduced, thus making it possible to reduce the unevenness caused by stacking elements.
As a result of being able to maintain the resolution of i4 turn, it is fine, 41
A? A semiconductor device with high density and one-piece integration can be obtained by turning.

[Embodiments of the invention]

FIGS. 1(a1 to 1k) are diagrams showing the manufacturing process of an embodiment of the present invention. First, on a single-crystal silicon substrate 1 on which desired elements have been formed, resist holes are opened in desired areas. lal.12 (1it, , x
;t, ) indicate the diffusion layer in the element region. For example, 0FPR-800 positive resist manufactured by Tokyo Ohka Co., Ltd. is used as the resist, and the surface is treated with chlorobenzene to make this resist pattern 13 into a glossy turn shaped into an inverse Teno amount shape suitable for the next lift-off process. . Next, a polysilicon film 14 that will serve as a connecting member is coated on the entire surface with a thickness of about 1 μm.
fb) where the snow f ivy attaches to the thickness of m. Then, the thin polysilicon film 14 on the side wall of the resist nog turn 13 is removed using a dilute organic alkaline aqueous solution, and then the Renost pattern 13 is removed by a lift-off method using an organic solvent, and at the same time the polysilicon film on the resist is removed. Then, selectively the polysilicon film 14. ,14. (c
l.

Next, a silicon oxide film 151 is laminated to a thickness of about 1 μm as an isolation insulating film on the entire surface using the Suno-sentsuta method (di).Next, a polyamide film is deposited as an organic film so that the thickness of the silicon oxide film 151 is about 1 μm on the flat part. Apply butyl methacrylate and then 21
Let the polymethacrylic anhydride film 16 be modified by heat treatment at 0°C.

Further laminated with positive photoresist) OFPR-800 (
(manufactured by Tokyo Ohka Chemical Co., Ltd.), the areas not requiring etching are covered with a resist pattern 17, and a reactive ion etching process is performed using a mixed gas of CF4 gas and H2 gas.At this time, the polymethacrylic anhydride film 161 and The silicon thickening film 151 is etched at approximately the same speed.

The polysilicon film 14 remains exposed (f).

Then, the resist is removed to obtain a flat surface with no crystal height difference and the periphery of the polysilicon film 14 is filled with an oxide film 15 (g
). Next, apply polysilicon to the entire surface using the CVD method to a thickness of approximately 700 mm.
A polysilicon film 1B (181,1&,
) is left (hl. As a result, the necessary region of the polysilicon film 18 comes into contact with the underlying diffusion layer 12 via the polysilicon film 14 serving as a connecting member.Next, a silicon oxide film is formed on the entire surface as an isolation insulating film. (A film 152 is deposited, and an ethyl cellosolve acetate solution of a mixture of novolac resin and polymethyl methacrylate is applied by a spin-coating method to form an organic film 19 having a dry etching rate equivalent to 1 h of silicon acid. do the
This is CF4. gas and 0. After hardening the surface by exposing it to a plasma state using a gas mixture, a resist/mother turn 20 is formed using a positive photoresist to cover a sufficiently wide area where the organic film is thin. (jl. Then, the entire surface is processed by reactive ion etching using CF4 and H3 at the same etching rate for the organic film 19 and the silicon oxide film 15 until the polysilicon film 18 is exposed. A flat surface is obtained by filling the periphery of the polycrystalline silicon 1 and 18 with an arsenic film 15. After this, the surface 1- is further thinly removed, and the polysilicon film 18 is subjected to laser annealing treatment to form a crystalline silicon film 18. A region where an element can be formed is obtained by performing 1 step, and a desired element is formed there.

According to this embodiment, when semiconductor elements are stacked, the difficulty of forming fine openings to connect the stacked elements is eliminated, and the stacking of semiconductor elements is facilitated. become.

By the way, MOS F using polysilicon on the substrate
A structure for integrating ET (in order to compare two structures, one based on the conventional process and one based on the process of this example are shown in the second structure).
As shown in Fig. and Fig. 3. In these V, 21.31 is the single crystal silicon substrate, 22.32 is the diffusion layer in the element region,
x s (,? sl,, 2g, ), ss (s
s.

33,) is a silicon instantaneous film as an isolation insulating film, 24,
J4 indicates a MOSFET made of a polysilicon film. In the conventional process shown in Figure 2, MO8F
'The connection between the BT 24 and the diffusion layer 22 on the cutting board is made using the oxide film 2.
The conductive film wiring 25 is connected through the contact hole formed in 3.
This is done by In contrast, in the process of this embodiment shown in FIG. 3, the terminal region of the M08FFfT 34 is in contact with the diffusion layer 32 on the substrate through the polysilicon film 35 embedded in the oxide film 33. Comparing the two, in Fig. 2, the surface irregularities in each layer are large, the resolution of the resist (i+) turn shadow is poor, and when microfabrication is performed using the dry etching process, problems such as discontinuance of the pattern flA25 occur. Easy to occur.

On the other hand, in FIG. 3, the surface has excellent flatness, and a resist pattern can be easily formed, which is also advantageous when further elements are laminated thereon.

In addition, since there is no need for the process of forming a narrow contact hole, it can be seen that the connection between the connected elements can be made reliably.

The present invention is not limited to the above embodiments. For example, the organic film used for flatly embedding the isolation insulating film may be
There is no problem in carrying out the present invention as long as the material shares the properties of being able to form a smooth surface by the spin cord method and of having approximately the same etching rate as the insulating film to be processed. In this case, a mixture of an organic substance having an etching rate higher than that of the insulating film to be processed and an organic substance having an etching rate lower than that of the insulating film to be processed may be adjusted and used. For example, a combination of a material selected from polystyrene, polyacrylonitrile, I-rivinylcarpazole, etc., and a material selected from polymethyl methacrylate, polymethyl methacrylate, polysulfone, polyisobutyne, etc. can be considered. Furthermore, as the organic film, a photoresist whose etching rate (W) was adjusted to be equal to the etching rate rvL of the isolation insulating film material was used, and the film thickness in the desired area was adjusted by exposing the desired area to light, and then a spin code method was used. The shape of the substrate after etching may be designed to be more desired than the shape of the film provided. Further, the semiconductor films to be laminated may be formed by an epitaxial growth method, and in this case, the crystallinity of the polysilicon film, which is a connecting member of the contact portion, may be improved in advance by, for example, irradiating with a pulse laser. or.

Figure 1 shows the exposed polysilicon film in the contact area (gl
After that, the crystallinity of this is improved using a base laser, etc., and a polysilicon film is further laminated and left in a 4-turn shape, and then this is treated with a base laser, etc. to improve the crystallinity. may be done. Further, the material selectively left as the connecting member is not limited to silicon, but may be a high melting point metal, a silicon alloy, or a silicide. When a high melting point metal is left in the contact portion and polysilicon is provided in contact with it to form a cluster, the interface between the two may be silicided.

[Brief explanation of the drawing]

Figure 1 (al~(kl) is a diagram showing the manufacturing process of one embodiment of the present invention, Figure 2 is a diagram showing the manufacturing process of polysilicon MO8F by the conventional process.
FIG. 3 is a diagram showing a structure in which ETs are integrated on a substrate, and FIG. 3 is a diagram showing a structure corresponding to FIG. 2 realized by the steps of this embodiment. 11... Single crystal silicon substrate, 121.12°...
Diffusion layer, 13... Resist mother turn, 14... Polysilicon film (connection member), ISl, 15. . . . Silicon oxide film (isolation insulating film), 16 . . . Polymethacrylic anhydride film, 17 . . . Resist mother turn. 1B,,1B,...Silicon film 1, 19...Organic substance 1iL x o-...Resist no or turn. Applicant's agent Patent attorney Takehiko Suzue No. 1 Figure 3 14+ 142

Claims (3)

[Claims] (1) In a method for manufacturing a semiconductor device in which semiconductor elements are laminated via an insulating film on a semiconductor substrate on which an element side region is formed, a connecting member is selectively left on a desired element sub-region of the semiconductor substrate. After that, the periphery of this connecting member is filled with an isolation insulating film, a semiconductor film is formed on this isolation insulating film to be in contact with the above-mentioned connecting member, and a desired element is formed on this semiconductor film. A method for manufacturing a semiconductor device. (2) The step of selectively leaving the connecting member is performed by forming a resist pattern before applying the connecting member, and then applying a connecting member film to the entire surface and removing the resist pattern. The method of manufacturing a semiconductor device according to claim 1, wherein unnecessary portions of the connecting member film are lifted off. (3) The process of filling the periphery of the connection member with an isolation insulating film is a process in which an isolation insulating film is coated on the entire surface, and the connection is selectively left on the first part using a spin code method under etching conditions so that the surface becomes flat. The method of manufacturing a semiconductor device according to claim 11, wherein uniform etching is performed until the member is exposed.