JPS6231176A - Laminated semiconductor device - Google Patents
Laminated semiconductor deviceInfo
- Publication number
- JPS6231176A JPS6231176A JP17145985A JP17145985A JPS6231176A JP S6231176 A JPS6231176 A JP S6231176A JP 17145985 A JP17145985 A JP 17145985A JP 17145985 A JP17145985 A JP 17145985A JP S6231176 A JPS6231176 A JP S6231176A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- polycrystalline silicon
- hole
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 11
- 239000000758 substrate Substances 0.000 abstract description 6
- 238000001953 recrystallisation Methods 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 3
- 238000012546 transfer Methods 0.000 abstract description 3
- 230000002457 bidirectional effect Effects 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 55
- 229920005591 polysilicon Polymers 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000010354 integration Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- XOFYZVNMUHMLCC-ZPOLXVRWSA-N prednisone Chemical compound O=C1C=C[C@]2(C)[C@H]3C(=O)C[C@](C)([C@@](CC4)(O)C(=O)CO)[C@@H]4[C@@H]3CCC2=C1 XOFYZVNMUHMLCC-ZPOLXVRWSA-N 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7812—Vertical DMOS transistors, i.e. VDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78642—Vertical transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、再結晶法によって形成された再結晶層を含む
２層以上の能動層を有する積層型半導体装置に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a stacked semiconductor device having two or more active layers including a recrystallized layer formed by a recrystallization method.
〈従来の技術〉
従来よシ、２次元ＬＳＩの近い将来に予想される困難に
対処すべく、更には２次元では不可能な３物元構造を生
かした新たな多機能デバイスを目指して、立体的に能動
回路を集積した積層型半導体装置の研究開発が活発に行
なわれている。<Conventional technology> In order to cope with the difficulties expected in the near future of 2D LSI, we have been developing 3D Research and development of stacked semiconductor devices that integrate active circuits is currently being actively conducted.
この積層型半導体装置を構成する場合、一般的にはまず
２次元デバイスを形成した活性層の上に絶縁層を堆積し
、更にその上に単結晶シリコン層を再結晶法等により形
成する。次にこの層内にデバイスを作り込むこともに上
下の素子間を接続する。これを繰シ返して多層からなる
積層型半導体装置を形成していた。そして積層型半導体
装置の上記の再結晶層に形成されるＭＯＳ構造素子は第
３図に示すように従来の２次元ＬＳＩの形成に用いられ
る横方向に電流の流れる横型構造の素子である。When constructing this stacked semiconductor device, generally an insulating layer is first deposited on an active layer in which a two-dimensional device is formed, and then a single crystal silicon layer is further formed thereon by a recrystallization method or the like. Next, devices are fabricated within this layer and connections are made between the upper and lower elements. This process is repeated to form a stacked semiconductor device consisting of multiple layers. The MOS structure element formed in the above-mentioned recrystallized layer of the stacked semiconductor device is a lateral structure element in which a current flows in the lateral direction, which is used in the formation of a conventional two-dimensional LSI, as shown in FIG.
第３図において、１１は一層目能動層、１２は絶縁層、
１３はドレインまたはソーヌ層、１４は２層目基板、１
５はドレインまたはソース電極、１６はゲートであシ、
ドレイン電極・ソース電極とも同一平面内で引き出され
、素子を流れる電流は図中矢印で示すように横方向に流
れている。In FIG. 3, 11 is a first active layer, 12 is an insulating layer,
13 is a drain or Sone layer, 14 is a second layer substrate, 1
5 is a drain or source electrode, 16 is a gate,
Both the drain electrode and the source electrode are drawn out in the same plane, and the current flowing through the element flows in the horizontal direction as shown by the arrow in the figure.
〈発明が解決しようとする問題点〉
このように従来の積層型半導体装置にあっては各能動層
を積層することによシ、その集積度を上げることは可能
であるものの、各能動層内に作υ込まれる素子は横方向
に電流の流れる構造であるため、装置の縮小化に限度が
あシ、特に積層型半導体装置の利点を充分に生かせる素
子構造とは言い′難く、その改善が望まれていた。<Problems to be solved by the invention> As described above, in conventional stacked semiconductor devices, although it is possible to increase the degree of integration by stacking each active layer, Since the elements fabricated in the semiconductor device have a structure in which current flows in the lateral direction, there is a limit to the miniaturization of the device.In particular, it is difficult to say that the device structure can take full advantage of the advantages of a stacked semiconductor device, and it is difficult to improve it. It was wanted.
本発明は上記の点にかんがみて創案されたものであり、
より高集積化を可能とする構造を備えた積層型半導体装
置を提供することを目的としている。The present invention was created in view of the above points,
It is an object of the present invention to provide a stacked semiconductor device having a structure that enables higher integration.
く問題点を解決するための手段〉
上記の目的を達成するため、本発明は再結晶層を有する
積層型半導体装置において、再結晶層に垂直構成のＭＯ
３型能動素子を備えるように構成している。Means for Solving the Problems> In order to achieve the above object, the present invention provides a stacked semiconductor device having a recrystallized layer, in which an MO is arranged perpendicularly to the recrystallized layer.
It is configured to include type 3 active elements.
〈作 用〉
上記のよう、な構成によシ、２層目以上の再結晶層に作
シ込まれるＭＯ３型能動素子の電流は上下方向に流れる
ことになり、その結果、より高集積化の実現が可能とな
り、積層型半導体装置の特徴が効果的に引き出されるこ
とになる。<Function> As described above, with the configuration, the current of the MO3 type active element implanted in the second and higher recrystallized layers flows in the vertical direction, and as a result, higher integration is possible. It becomes possible to realize this, and the features of the stacked semiconductor device can be effectively brought out.
〈実施例〉
以下、図面を参照して本発明の実施例を詳細に説明する
。第１図は本発明の一実施例装置における２層目以後の
能動層に作シ込まれるＭＯＳＩ−ランジスタの構造を示
す断面図である。<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing the structure of a MOSI transistor that is implanted in the second and subsequent active layers in a device according to an embodiment of the present invention.
第１図において、１は１層目能動層、２は１層目能動層
１上に積層形成された絶縁層、４は絶縁６はゲート、７
はソース電極、８は１層目能動層ｌと２層目能動層との
接続配線（スルーホー）Ｖ ）、９は絶縁膜である。In FIG. 1, 1 is a first active layer, 2 is an insulating layer laminated on the first active layer 1, 4 is an insulator 6 is a gate, and 7 is an insulating layer laminated on the first active layer 1.
8 is a source electrode, 8 is a connection wiring (through hole) between the first active layer l and the second active layer (V), and 9 is an insulating film.
次に、上記のような構造の素子の作製方法をｎチャネル
型素子を例にして説明するが、ＰとＮを置き換えること
によｆｉＰチャネル型ＭＯＳ素子の作製についても同様
である。Next, a method for manufacturing an element having the above structure will be described using an n-channel type element as an example, but the same applies to manufacturing a fiP channel type MOS element by replacing P and N.
まず、従来法を用いて、１層目能動層１に１層目のＬＳ
Ｉを形成し、その後、層間結合を行なうためのスルーホ
ー／Ｉ／８を形成する。このスルーホール８の形成はポ
リシリコンを堆積し、平坦化後ヌルーホール部分８をｎ
＋ポリシリコンにするようＰ＋またはＡ５ のイオン
注入及び拡散を行なって形成する。次に２層目能動層と
なるポリシリコンを比較的厚く（１μｍ以上）堆積し、
レーザー・アニール等により再結晶化する。次にＮタイ
プとなるようＰ＋またはＡ８を打ち込み、拡散する。First, using the conventional method, the first layer LS is applied to the first layer active layer 1.
After that, a through hole/I/8 for performing interlayer bonding is formed. To form this through hole 8, polysilicon is deposited, and after planarization, the null hole portion 8 is
P+ or A5 ions are implanted and diffused to form + polysilicon. Next, a relatively thick layer of polysilicon (more than 1 μm) is deposited to form the second active layer.
Recrystallize by laser annealing, etc. Next, drive P+ or A8 so that it becomes N type and spread it.
このとき再結晶層４とヌル−ホー／ｌ／ ８中のポリシ
リコンとのコンタクトは、ポリシリコン中のＰ＋または
Ａ８が基板中に拡散するため、オーミック・コンタクト
が保証される。次に、基板エッチ等による素子分離を行
ったのち、ゲート酸化膜９を形成する。ゲート電極６の
形成のためのゲート・ポリシリコンを付着、パターニン
グしたのち、Ｂ＋及びＰ （またはＡｓ）を二重イオン
注入し、２層３１及びＮＮ３２を第１図の如く形成する
。ソース・コンタクトは２層３１と８層３２の両方にわ
たってソース電位がとれるようコンタクトの穴あけを行
う。最後にＡｌ蒸着、パターニングを待なってソース電
極７を形成し、更に保護膜をつけて、本発明に係るデバ
イスの作製を完成する。At this time, ohmic contact between the recrystallized layer 4 and the polysilicon in the null-hole/l/8 is ensured because P+ or A8 in the polysilicon diffuses into the substrate. Next, after element isolation is performed by etching the substrate or the like, a gate oxide film 9 is formed. After depositing and patterning gate polysilicon for forming gate electrode 6, double ion implantation of B+ and P (or As) is performed to form two layers 31 and NN 32 as shown in FIG. A source contact hole is formed so that a source potential can be maintained across both the second layer 31 and the eighth layer 32. Finally, after Al vapor deposition and patterning, a source electrode 7 is formed, and a protective film is further applied to complete the fabrication of the device according to the present invention.
このように作製された素子構造においては、電流は第１
図中の矢印の如く上下方向に流れる。また、再結晶層４
の厚さを大きくすると、高耐圧化が図れるという利点が
ある反面、双方向性に問題があシ、トランスファーゲー
トで使用する場合には考慮が必要となる。In the device structure fabricated in this way, the current flows in the first
It flows in the vertical direction as shown by the arrow in the figure. In addition, the recrystallization layer 4
Increasing the thickness has the advantage of increasing the breakdown voltage, but on the other hand, there is a problem with bidirectionality, which must be taken into consideration when used in a transfer gate.
第２図は電流が上下方向に流れるトランジヌタ構造の別
の例を示す素子構造断面図であシ、第１図と同一部分は
同一符号で示している。FIG. 2 is a cross-sectional view of an element structure showing another example of a transistor structure in which current flows in the vertical direction, and the same parts as in FIG. 1 are indicated by the same reference numerals.
第２図において、１は１層目能動層、２は絶縁膜、４１
はＢ＋層、４２はＰ層、４３はＢ＋層、５はドレインま
たはソース電極、６はゲート、−８は１層目と２層目の
接続配線用ヌル−ホールである。In FIG. 2, 1 is the first active layer, 2 is an insulating film, and 41
is a B+ layer, 42 is a P layer, 43 is a B+ layer, 5 is a drain or source electrode, 6 is a gate, and -8 is a null hole for connection wiring between the first and second layers.
次に、この第２図に示した構造の素子の作製方法を説明
すると、上層能動層を再結晶化して形成するところまで
、第１図に示した素子の作製と同一方法で作製する。次
に再結晶層基板をＢ＋とじたのち、マヌクなしでＢ＋と
Ｐ＋（またはＡ＋、）の二重イオン注入を行ない、上部
から下部へ向けてｎ＋層３１，２層３２及びｎ＋層３３
のＢ＋Ｐ ｎ＋三層構造とする。次に再結晶層をテーパ
ーエスチングし、その側面にゲート酸化膜２１をつけ、
このテーパーエツチング部分にポリシリコンでゲート６
を構成する。更に酸化膜２２をつけたのち、コンタクト
・ホールの形成、Ａｌ蒸着・パターニングを行なってド
レインまたはソース電極５を形成し、最後に保護膜をつ
けてデバイスの作成を完了する。Next, a method for manufacturing the device having the structure shown in FIG. 2 will be described. The device is manufactured by the same method as the device shown in FIG. 1, up to the point where the upper active layer is recrystallized and formed. Next, after closing the recrystallized layer substrate with B+, double ion implantation of B+ and P+ (or A+) is performed without manucing, and from the top to the bottom, the n+ layer 31, the second layer 32, and the n+ layer 33.
It has a B+P n+ three-layer structure. Next, the recrystallized layer is tapered etched, and a gate oxide film 21 is attached to the side surface of the recrystallized layer.
Gate 6 is made of polysilicon on this tapered etched part.
Configure. Further, after forming an oxide film 22, contact holes are formed, Al evaporation and patterning are performed to form a drain or source electrode 5, and finally a protective film is applied to complete the device fabrication.
この構造においては、電流は第２図中の矢印のように上
下方向に流れる。なお、この構造においては、双方向特
性が保証され、トラン簡スフアゲートとして使用しても
何ら問題は生じない。In this structure, current flows in the vertical direction as indicated by the arrows in FIG. Note that this structure guarantees bidirectional characteristics, and no problem will occur even if it is used as a transfer gate.
〈発明の効果〉
以上のように本発明によれば、電流を上下方向に流す縦
型トランジスタを再結晶層内に形成した積層型半導体装
置が提供され、デバイスの縮小化が可能となシ、積層型
半導体装置の有する利点をより一層引き出すことが出来
、装置のよυ高集積化を実現することが出来る。<Effects of the Invention> As described above, according to the present invention, there is provided a stacked semiconductor device in which a vertical transistor that allows current to flow in the vertical direction is formed in a recrystallized layer, and the device can be downsized. The advantages of the stacked semiconductor device can be further brought out, and the device can be highly integrated.
第１図は本発明の一実施例装置における２層目以後の能
動層に作り込まれるＭＯＳトランジスタの構造を示す断
面図、第２図は他の実施例における素子構造断面を示す
図、第３図は従来の装置における横型構造素子を示す断
面図である。
１・・ＩＭ目能動層、 ２・・絶縁膜、 ３１ ・
Ｐ層、 ３２・・一層、 ４・・・再結晶層（ｎ層また
はｎ層）、 ６・・・ゲート、 ７・・・ソース電極、
８・・・１層目能動層と２層自能動層との接続配線（７
，７レーホ −ル ）、 ９・・ 絶縁膜。FIG. 1 is a cross-sectional view showing the structure of a MOS transistor built into the second and subsequent active layers in a device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a device structure in another embodiment, and FIG. The figure is a sectional view showing a horizontal structural element in a conventional device. 1. IM active layer, 2. Insulating film, 31.
P layer, 32... single layer, 4... recrystallized layer (n layer or n layer), 6... gate, 7... source electrode,
8... Connection wiring between the first active layer and the second automatic active layer (7
, 7 Rehole), 9... Insulating film.
Claims (1)
再結晶層に垂直構成のＭＯＳ型能動素子を備えてなるこ
とを特徴とする積層型半導体装置。1. A stacked semiconductor device having a recrystallized layer, characterized in that the recrystallized layer is provided with a vertically configured MOS active element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17145985A JPS6231176A (en) | 1985-08-02 | 1985-08-02 | Laminated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17145985A JPS6231176A (en) | 1985-08-02 | 1985-08-02 | Laminated semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6231176A true JPS6231176A (en) | 1987-02-10 |
Family
ID=15923497
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17145985A Pending JPS6231176A (en) | 1985-08-02 | 1985-08-02 | Laminated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6231176A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63296281A (en) * | 1987-05-28 | 1988-12-02 | Fujitsu Ltd | Semiconductor device |
| WO2002041403A3 (en) * | 2000-11-14 | 2002-12-05 | Infineon Technologies Ag | Mos low-voltage vertical transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52106688A (en) * | 1976-03-05 | 1977-09-07 | Nec Corp | Field-effect transistor |
| JPS5617071A (en) * | 1979-07-20 | 1981-02-18 | Fujitsu Ltd | Semiconductor device |
| JPS5893270A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6012769A (en) * | 1983-07-01 | 1985-01-23 | Seiko Instr & Electronics Ltd | Thin film transistor |
| JPS60124974A (en) * | 1983-12-12 | 1985-07-04 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated gate type semiconductor device |
-
1985
- 1985-08-02 JP JP17145985A patent/JPS6231176A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS52106688A (en) * | 1976-03-05 | 1977-09-07 | Nec Corp | Field-effect transistor |
| JPS5617071A (en) * | 1979-07-20 | 1981-02-18 | Fujitsu Ltd | Semiconductor device |
| JPS5893270A (en) * | 1981-11-30 | 1983-06-02 | Toshiba Corp | Manufacture of semiconductor device |
| JPS6012769A (en) * | 1983-07-01 | 1985-01-23 | Seiko Instr & Electronics Ltd | Thin film transistor |
| JPS60124974A (en) * | 1983-12-12 | 1985-07-04 | Semiconductor Energy Lab Co Ltd | Manufacture of insulated gate type semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63296281A (en) * | 1987-05-28 | 1988-12-02 | Fujitsu Ltd | Semiconductor device |
| WO2002041403A3 (en) * | 2000-11-14 | 2002-12-05 | Infineon Technologies Ag | Mos low-voltage vertical transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2791260B2 (en) | Method for manufacturing semiconductor device | |
| JPH04348077A (en) | Thin-film transistor | |
| JP2510599B2 (en) | Field effect transistor | |
| JPS6231176A (en) | Laminated semiconductor device | |
| JPS6251216A (en) | Manufacture of semiconductor device | |
| JPH04116846A (en) | Semiconductor device and its manufacture | |
| JPH0393276A (en) | Semiconductor storage device and manufacture thereof | |
| JPS6050063B2 (en) | Complementary MOS semiconductor device and manufacturing method thereof | |
| JPS62112361A (en) | Complementary semiconductor device | |
| JPH04206732A (en) | Thin film transistor | |
| JP2838932B2 (en) | Field effect type semiconductor device | |
| JPH021942A (en) | Semiconductor device and its manufacture | |
| JPS5821861A (en) | Semiconductor memory device | |
| JPS62244163A (en) | Semiconductor device | |
| JPH03196672A (en) | Cmos integrated circuit | |
| JPH03101167A (en) | Semiconductor device and manufacture thereof | |
| JPS60234353A (en) | Semiconductor device | |
| JPH04127440A (en) | Manufacture of semiconductor device | |
| JPH01162358A (en) | Formation of laminar-structure mis semiconductor device | |
| JPH04221856A (en) | Semiconductor device | |
| JPH0621462A (en) | Thin-film transistor | |
| JPH0487339A (en) | Semiconductor device and its manufacture | |
| JPH03120728A (en) | Manufacture of semiconductor device | |
| JPS63246863A (en) | Manufacture of complementary insulated-gate semiconductor device | |
| JPH04251974A (en) | Semiconductor device |