DE10302623B4 - Semiconductor structure with a reduced terminal capacitance and a method for producing the semiconductor structure - Google Patents

Abstract

Semiconductor structure with:
a substrate (101);
a pad (105);
wherein the substrate (101) below the pad (105) has a trench (800) which is formed to reduce a coupling capacitance between the substrate (101) and the pad (105), wherein the walls of the trench (800) covered by an oxide layer,
wherein a deposited insulating layer (207) is disposed between the pad (105) and the trench (800), and wherein the insulating layer (207) includes an insulating ridge (801) interposed between the oxide layers covering the walls of the trench (800) Ditch protrudes.

Description

Semiconductor structure with a reduced connection capacity as well a method for producing the semiconductor structure

The The present invention relates to a semiconductor structure as well to a method for producing the semiconductor structure, wherein the Semiconductor structure has a reduced capacitance between a pad and a substrate.

With an increasing integration density of modern semiconductor devices and with the use of ever higher frequencies for information transmission grows the importance of building elements within a possible huge Frequency bandwidth loss, a desired frequency characteristics have as well as cheap and ideally with the help of existing technologies can be produced. The desired Frequency characteristics within a large bandwidth paired with low production costs can be achieved only if already in a production of Semiconductor parasitic components Effects that are brought about, for example, by coupling capacitances or coupling inductances, be reduced.

Point For example, semiconductor structures metallizations as pads, thus forms between a substrate, which is the semiconductor structure has, and the pad always an undesirable Coupling capacitance, which have a negative influence has the frequency characteristics of the semiconductor structure. For example the semiconductor structure on a Si substrate, the coupling capacity is between the metallization of the connection pads and the Si substrate especially in high-frequency applications of the semiconductor element problematic and therefore undesirable. In particular, in power components are sometimes very many Connecting wires needed, so that one high number of connection pads can be present, whereby the coupling capacities very large values reachable.

In the writing by Rikjos, "Future Developments and Technology Options in Cellular Phone Power Amplifiers: From Power Amplifier to Integrated RF Fronts and Modules ", IEEE BCTM 7.1., a method for reducing the coupling capacity is proposed, in which by gluing the discs on a glass slide the Silicon is replaced by glass, which reduces the coupling capacity should be. A disadvantage of the published in the cited document However, the procedure is a big one Process costs, the high manufacturing costs entails because the discs with Help another method must be attached to the glass slide.

The US 5,539,243 A discloses a semiconductor structure having a first electrode disposed under an interlayer insulator film and a second electrode formed on or over the interlayer insulator film. The first electrode is connected to an active region formed in a semiconductor substrate, the second electrode acts as a bonding pad, and is connected to the first electrode through the interlayer insulator film. Between the second electrode and the substrate, there is a capacity reduction structure having an insulator layer in which a plurality of cavities are arranged at intervals.

JP 10-261671 A discloses a semiconductor structure and a method for producing the same. In one on a substrate 10 arranged epitaxial layer are arranged a plurality of columnar insulating members which extend through the epitaxial layer into the substrate. As a result, a capacitance generated by an electrode pad arranged on the epitaxial layer can be reduced.

From JP 09-097790 A, a semiconductor structure is known in which an oxide film and a nitride film are formed on a semiconductor substrate. An opening is provided on the oxide film and the nitride film, forming a stripe-like deep groove by etching the substrate through the opening. The side surface of the groove is oxidized, whereby a strip-like part of the substrate is oxidized to form an oxide film 18 to form as thick as the depth of the groove. Thus, the semiconductor structure is below a bonding pad with a thick oxide film 18 Mistake.

The JP 57-035339 A discloses a semiconductor structure and a method for producing the same, in which below a bonding pad a porous Silicon oxide film is provided, the one compared to one incidentally on a surface of a Substrate formed silicon oxide film has increased thickness. Thereby can be a parasitic Capacity, to the formation of the bonding electrode contributes reduced become.

The The object of the present invention is to provide a semiconductor structure with an efficiently reduced coupling capacity and a method of manufacturing to create the semiconductor structure.

This object is achieved by a semiconductor structure according to claim 1 or by a method for producing the semiconductor structure according to An claim 7 solved.

In the usual Technologies for producing a semiconductor structure is between the connection surfaces and the Si substrate an insulation layer existing. The thickness of this insulation layer is however for some high frequency applications insufficient. To existing standard technologies for this To be able to use applications is therefore a reduction of the capacitance between pad and Substrate required.

For this In addition, in the present invention, it is locally under the pad Trench etched into the substrate and filled with a dielectric. This is done without the remaining structure significantly over standard technology to change. This allows existing standard technologies are used. This causes a Significant reduction in development costs and production costs. The present invention is based on the finding that the coupling capacity an additional arranged under the pad Oxide range can be reduced.

One Another advantage of the present invention is that the oxide region can be formed using standard technologies, preferably with the help of LOCOS technology (LOCOS = local oxidation of silicon), resulting in a cost reduction leads, since existing low-cost Manufacturing can be used.

One Another advantage of the present invention is that to a Reduction of coupling capacity no further substrates needed be what an increase the production costs prevented.

One Another advantage of the present invention is to be seen in that the Oxide region is formed within the already existing substrate, So that the coupling capacitance not reduced at the expense of dimensions of the semiconductor structure so that one integration the semiconductor structure is not affected.

preferred embodiments The present invention will be described below with reference to FIG the enclosed drawings closer explained. Show it:

1 to 7 Semiconductor structures;

8th an embodiment of a semiconductor structure according to the present invention;

9 another embodiment of a semiconductor structure according to the present invention;

10 a semiconductor structure; and

11 a semiconductor structure.

The 1 to 7 . 10 and 11 show comparative examples of semiconductor structures. The semiconductor structure according to 1 has a substrate 101 on, which consists for example of silicon. On the substrate is an insulation layer 107 , The substrate 101 includes an oxide region 103 , On the insulation layer 107 , above the oxide region 103 is a connection pad 105 which is, for example, a metallization layer. The spatial extent of the pad 105 is lower than that of the oxide region, so that the below the pad 105 formed oxide region 103 the pad 105 from the substrate 101 more decoupled, than only with the insulation layer 107 the case is.

The following are the properties of the in 1 illustrated example explained.

To reduce the effective coupling capacity with the pad 105 (Pad), the insulation layer 107 and the substrate 101 is formed, in addition, the oxide region 103 , formed below the pad. In a first approximation, a model of a plate capacitor can be used to describe the coupling capacitance, wherein the coupling capacitance has a growing thickness of the oxide region and / or with a decreasing dielectric constant of the oxide region 103 sinks. In order to reduce the coupling capacity, the oxide range 103 preferably be formed such that a quotient of the thickness of the oxide region 103 and its dielectric constant is as large as possible, which is particularly advantageous if the pad can not be made arbitrarily small due to the process or due to the necessary electrical properties of the semiconductor structure.

To make the in 1 shown semiconductor structure is first the substrate 101 provided. In a next step, the oxide region is formed in the substrate 103 trained and it is in further steps, the insulation layer 107 and the pad 105 educated. The oxide region can be realized by means of the already mentioned LOCOS technology, in which SiO ₂ layers are produced. However, it is only the insulation layer that can be used 107 be applied and then the oxide region 103 be formed.

2 shows another comparative example of a semiconductor structure.

One in the substrate 101 formed oxide region 200 has a ditch 201 on which is filled with oxide (oxide trench). In addition, the oxide region indicates 200 a first oxide layer 203 on, from one to the trench filled with oxide 201 adjacent, as well as a second oxide layer 205 on the other side of the oxide trench 201 borders. Both have the first oxide layer 203 as well as the second oxide layer 205 a thickness that is less than a thickness of the oxide trench 201 , On the oxide trench 201 is the pad 105 arranged. Here is a spatial extension of the pad 105 lower than that of the oxide trench 201 , On the substrate 101 as well as on the first oxide layer 203 and on the second oxide layer 205 is an insulation layer 207 arranged, with parts of the insulation layer 207 each from one side and from the other side to the oxide trench 201 adjoin. The insulation layer 207 as well as the oxide trench 201 are further arranged so that they form a common upper surface. It should be noted, however, that the insulation layer 207 also partially the oxide trench 201 can cover, but without the pad 105 cover.

To make the in 2 The semiconductor structure shown is first the substrate 101 provided, which may be, for example, a Si substrate. In a further step, for example, with the aid of the LOCOS method already mentioned, a substrate region is oxidized, wherein the first oxide layer 203 and the second oxide layer 205 be formed. After this step, the first oxide layer 203 and the second oxide layer 205 be interconnected, since they can be generated in an oxidation process. At the first oxide layer 203 At the transition to unoxidized silicon, the so-called LOCOS beak, which always occurs when LOCOS technology is used for the oxidation, occurs. In a further step, the insulation layer 207 formed on a surface thus formed. In a further step, the ditch 201 through a region of the insulation layer 207 in the substrate 101 etched in and filled, for example, with a plasma oxide. In order to achieve a planar trench surface, the oxide trench is in a further process step 201 etched back and / or ground. After that, on the oxide trench 201 the pad 105 (Pad metal) deposited and structured so that they above the oxide-filled trench 201 is trained.

3 shows another comparative example of a semiconductor structure according to the present invention.

Unlike the in 2 Comparative example shown is on the insulating layer 207 as well as on the oxide trench 201 a passivation 301 arranged and structured such that the pad 105 either not at all or only partially covered.

The passivation 301 serves to protect the semiconductor structure from contamination. In the passivation 301 it may be, for example, a nitride layer after the deposition of the pad 105 deposited and patterned such that a portion of the pad 105 (Pad metal) is accessible.

In 4 another comparative example of a semiconductor structure according to the present invention is shown.

Unlike the in 3 The comparative example shown has the in 4 illustrated semiconductor structure an oxide layer 401 on that in a ditch 403 is arranged around except for the upper surface thereof. In this case, the oxide layer comprises 401 both the first oxide layer 203 as well as the second oxide layer 205 each laterally in an upper region of the oxide layer 401 extend. The remainder of the trench 403 is filled with plasma oxide, for example, so that the trench is completely filled with insulating material. The first and second oxide layers ( 203 . 205 ) as well as the oxide in the trench 403 an oxide region 405 ,

To make the in 4 The semiconductor structure shown is first the substrate 101 provided, which is for example a silicon substrate. In a further process step is in the substrate 101 the ditch 403 etched. With the help of LOCOS technology can then the oxide layer 401 be formed. In doing so, as already mentioned in connection with the 3 has been discussed, the LOCOS beak 203 and the oxide layer 205 , Since the ditch 403 is etched before field oxidation, the oxide layer is formed on the walls 401 (Field oxide). In a further method step, the trench 403 filled with oxide, for example, plasma oxide is used, etched back and / or ground. After this planarization, the plasma oxide also covers the previously free silicon next to the LOCOS beak. This cover can be removed. Here, the oxide trench and the adjacent oxide layers 203 and 205 covered with photoresist and the plasma oxide layer removed on the exposed area. This ensures that there are no significant changes in the active silicon area compared to the standard technology. In a further method step, an exposed surface of the substrate is applied 101 , the oxide layer 401 as well as the exposed trench surface the insulation layer 207 appropriate. After an optional further method step, further comprising a surface of the insulation layer 207 is etched back and / or ground, the connection surface above the oxide trench 403 arranged. It is between the pad 105 and the oxide trench 403 the insulation layer 207 arranged if it has not previously been etched back to the oxide trench area.

Since according to the in 4 In the illustrated comparative example, the step of oxidizing the substrate portion is performed after the step of etching the trench, the oxide layer may be formed 401 on the walls of the ditch 403 be formed using the LOCOS technology such that their spatial extent greater than that of the pad 105 is.

In 5 another comparative example of a semiconductor structure according to the present invention is shown.

Unlike the in 4 The comparative example shown has the in 5 illustrated semiconductor structure a further oxide region 501 on that between an insulation layer 503 that the other oxide area 501 , the oxide trench 403 , the oxide layer 401 and the first and second oxide layers ( 203 . 205 ) and the substrate 101 is arranged such that the insulating layer 503 with the substrate 101 not in touch. In addition, the in 5 illustrated semiconductor structure, the passivation layer 301 on how they already related to the in 3 Comparative example has been discussed.

To make the in 5 The semiconductor structure shown is first the substrate 101 provided and it is in a further process step of the trench 403 etched, then the layer 401 generated, then filled the remaining trench. All of these insulation layers together form the oxide region 405 , The area 403 is therefore the entire trench in the silicon. After forming the oxide layer 401 (Field oxide) therefore becomes both the remaining area of the trench 403 as well as the further oxide range 501 filled with oxide, for example the plasma oxide already mentioned. In a further process step, the further oxide region 501 , as well as the plasma oxide in the trench 403 etched back and / or ground, so that forms a planar surface. In a further method step, the insulation layer is applied to the upper surface thus formed 503 for example, arranged by depositing a dielectric. All further process steps are carried out like a normal process, as already described in connection with FIG 3 has already been described.

In that both the trench 403 as well as the further oxide range 501 can be filled with oxide, the process step in which the oxide is formed, can be simplified because not only the trench 403 is filled with oxide, but also all other exposed surfaces, resulting in a further simplification of the manufacturing process. Furthermore, in order to achieve a planar surface, for example, the CMP method can be applied to the entire surface thus formed for grinding, so that punctiform surface processing is avoided, resulting in further process cost reduction.

6 shows another comparative example of a semiconductor structure according to the present invention.

Unlike the in 4 The comparative example shown has the in 6 illustrated semiconductor structure an oxide trench 600 which is, for example, filled with field oxide and which extends laterally into the first and second oxide regions ( 203 . 205 ) passes over. The oxide trench 600 also has a first limit 603 as well as a second limit 605 each spaced from a top surface of the oxide trench 600 and extend into it. The first and second boundaries are areas where the field oxide filling the oxide trench has grown together from left and right, respectively. The oxide trench 600 also has a substrate web 601 on, which is part of the substrate 101 is. In this case, the substrate web protrudes 601 from below into the ditch 600 into it, without him with the overlying insulation layer 207 is in contact. The ditch 600 is in the in 6 as already mentioned, filled with field oxide, wherein the first oxide layer 203 and the second oxide layer 205 Parts of the field oxide are. The oxide trench and the first and second oxide layers ( 203 . 205 ) form an oxide region 607 ,

To make the in 6 shown semiconductor structure is in the provided substrate 101 the ditch 600 etched so that the substrate web 601 is trained. In a further method step, for example, using the LOCOS technology of the trench 600 filled by a field oxidation, with a suitable choice of a width of the web 601 also a complete oxidation of the web 601 can be achieved. Here are the in 6 shown limits 603 and 605 the respective areas where the field oxide has grown together from left and right, respectively. In a further method step, the insulation layer 207 applied. After polishing the insulation layer 207 , which can be performed for example by means of the already mentioned CMP method, is the pad 105 formed by, for example, a metallization layer on the insulating layer 207 is applied. This is the pad 105 above the oxide region 607 educated.

In 7 another comparative example of a semiconductor structure according to the present invention is shown.

Unlike the in 6 The comparative example shown has the in 7 shown semiconductor structure passivation 301 as they are already related to in 3 and in 5 Comparative examples shown has been discussed.

In 8th an embodiment of a semiconductor structure according to the present invention is shown.

Unlike the in 6 The comparative example shown has the in 8th illustrated semiconductor structure an oxide trench 800 which is filled with field oxide, for example, and to which the first and the second oxide regions ( 203 . 205 ). The oxide trench 600 points next to the already discussed substrate web 601 a first isolation bar 801 and a second isolation bar 803 on. Both the first isolation bar 801 as well as the second isolation bar 803 are with an insulating material of the insulation layer 207 filled and protrude from above into the oxide-filled trench 600 into it. In the in 8th illustrated embodiment, the first insulating web 801 to the left of the substrate web 601 arranged. The second isolation bridge 803 is, on the other hand, right next to the substrate web 601 arranged. The ditch 800 and the first and second oxide layers ( 203 . 205 ) form an oxide region 805 ,

To make the in 8th The semiconductor structure shown is first the substrate 101 provided, which may be silicon substrate. In a further method step, the trench 800 etched and, for example, filled with field oxide using the LOCOS technology. The field oxidation fills the trench 800 not completely. The remaining filling of recesses for the isolation bridges 801 and 803 is then done by depositing the dielectric material (dielectric). All further process steps are carried out as the process, as already described in connection with the in 6 Comparative example has been discussed.

The formation of the isolation webs 801 and 803 is particularly advantageous because there are no special process steps to fill the trench 800 with oxide are required. The advantage over the production after 6 lies in the use of the already deposited insulating layers 207 to fill up the trench. In addition, it is conceivable to durchrossoxidieren the respective webs completely, so that the oxide trench 800 completely filled with oxide. This is particularly advantageous since, for example, the silicon webs, as for example in the form of the substrate web 601 in the 8th illustrated embodiment, the coupling capacitance between the pad 105 and the substrate 101 can enlarge.

In 9 FIG. 3 shows another embodiment of a semiconductor structure according to the present invention.

Unlike the in 8th illustrated embodiment, the in 9 shown semiconductor structure passivation 301 on, as already related to, for example, in 3 illustrated embodiment has been discussed.

10 shows another comparative example of a semiconductor structure.

Unlike the in 2 The illustrated comparative example has an oxide filled trench 1011 the substrate web 601 on, as he already related to the in 6 Comparative example has been discussed. The trench filled with oxide 1011 as well as the first and the second oxide layer form an oxide region 1013 , The trench filled with oxide 1011 also has another first limit 1015 as well as another second border 1017 on, each marking areas where the oxide has grown together, as it is already related to the in 6 Comparative example has been discussed.

In 11 another comparative example of the semiconductor structure according to the present invention is shown.

Unlike the in 10 The comparative example shown has the in 11 shown semiconductor structure the further oxide region 501 as he is already related to the example in 5 has already been discussed semiconductor structure. In addition, the in 11 illustrated semiconductor structure the passivation 301 on top of that on the insulation layer 207 and on parts of the pad 105 (Pad) is arranged, as it is already related to in 5 Comparative example has been discussed.

To form the field oxide was always used in connection with the embodiments described above, the LOCOS technology, which is always an education of ers th oxide layer 203 and the second oxide layer 205 pulls. However, it is conceivable to produce the oxide layers by means of other technologies in which, for example, the field oxides are produced by means of deposition processes.

Claims (13)

Semiconductor structure comprising: a substrate ( 101 ); a pad ( 105 ); wherein the substrate ( 101 ) below the pad ( 105 ) a trench ( 800 ), which is designed to provide a coupling capacitance between the substrate ( 101 ) and the pad ( 105 ), whereby the walls of the trench ( 800 ) are covered with an oxide layer, wherein between the pad ( 105 ) and the ditch ( 800 ) a deposited insulation layer ( 207 ), and wherein the insulating layer ( 207 ) an insulating web ( 801 ), which between the walls of the trench ( 800 ) covering oxide layers protrudes into the trench. A semiconductor structure according to claim 1, wherein the trench ( 800 ) a substrate web ( 601 ) having a portion of the substrate ( 101 ) and in the ditch ( 800 protrudes. A semiconductor structure according to claim 1 or 2, wherein one of the pads ( 105 ) connected circuit is a high frequency circuit. A semiconductor structure according to claim 3, wherein the connected Circuit is a high frequency transistor. Semiconductor structure according to claim 4, wherein the connected High frequency transistor is a MOS transistor. Semiconductor structure according to one of Claims 1-5, in which the insulating layer ( 207 ) on the substrate ( 103 ) and is disposed on the oxide layer. Method for producing a semiconductor structure, comprising the following steps: providing a substrate ( 101 ); Creating a trench ( 800 ) in the substrate ( 101 ); Generating an oxide layer on the substrate ( 101 ) such that the oxide layer covers the walls of the trench ( 800 ) and a recess remains in the trench; Depositing an insulating layer on the oxide layer to fill the recess and to cover the oxide layer with the insulating layer; and forming a pad ( 105 ) on the insulating layer above the trench ( 800 ). The method of claim 7, wherein the step of forming the oxide layer comprises a step of oxidizing a substrate region after a step of etching a trench ( 800 ) in the substrate ( 101 ) having. Method according to claim 7 or 8, wherein in the step of creating the trench ( 800 ) a substrate web ( 601 ), which is part of the substrate ( 101 ) and is in the trench, is formed. Method according to claim 8 or 9, wherein the substrate ( 101 ), and wherein the step of forming the oxide layer comprises a step of locally oxidizing silicon. Method according to one the claims 8-10, where a connected to the pad circuit is a high frequency circuit. Method according to claim 11, wherein the connected circuit is a high-frequency transistor. Method according to claim 12, wherein the connected high-frequency transistor is a MOS transistor is.