JPS5735339A - Semiconductor device and manufacture of the same - Google Patents
Semiconductor device and manufacture of the sameInfo
- Publication number
- JPS5735339A JPS5735339A JP11057280A JP11057280A JPS5735339A JP S5735339 A JPS5735339 A JP S5735339A JP 11057280 A JP11057280 A JP 11057280A JP 11057280 A JP11057280 A JP 11057280A JP S5735339 A JPS5735339 A JP S5735339A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- bonding pad
- epitaxial layer
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76245—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using full isolation by porous oxide silicon, i.e. FIPOS techniques
Abstract
PURPOSE:To shorten the heat treatment time by a method wherein a porous silicone insulating film is formed unde a bonding pad electrode and the circumference of the insulating film is constituted by N type semiconductor layer. CONSTITUTION:A porous silicon oxide film 12 and N type epitaxial layer 13, 14 are formed on a P type semiconductor substrate 11 and a silicon oxide film 15 is formed thereon. A bonding pad electrode 16, which is to be used as a terminal, leading the semiconductor element out, and a bonding pad portion 17 are formed in an N type epitaxial layer 13. According to this method parasitic capacity can be reduced and the parasitic capacity at the side of the thick oxidized film 12 becomes negligible advantageously because the N type epitaxial layer 14 exists on the side of the thick oxidized film 12 and PN junction is composed in a high concentration region of the surface of a P type seperation layer 25 and a depletion layer is formed. Thus the heat treament time can be shortened and the area of the semiconductor device can be reduced.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11057280A JPS6057701B2 (en) | 1980-08-11 | 1980-08-11 | Semiconductor device and its manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11057280A JPS6057701B2 (en) | 1980-08-11 | 1980-08-11 | Semiconductor device and its manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5735339A true JPS5735339A (en) | 1982-02-25 |
JPS6057701B2 JPS6057701B2 (en) | 1985-12-16 |
Family
ID=14539229
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11057280A Expired JPS6057701B2 (en) | 1980-08-11 | 1980-08-11 | Semiconductor device and its manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6057701B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004066385A2 (en) * | 2003-01-23 | 2004-08-05 | Infineon Technologies Ag | Semiconductor structure having a reduced connecting capacitance and method for producing the semiconductor structure |
-
1980
- 1980-08-11 JP JP11057280A patent/JPS6057701B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004066385A2 (en) * | 2003-01-23 | 2004-08-05 | Infineon Technologies Ag | Semiconductor structure having a reduced connecting capacitance and method for producing the semiconductor structure |
DE10302623A1 (en) * | 2003-01-23 | 2004-08-05 | Infineon Technologies Ag | Semiconductor structure with a reduced connection capacity and a method for producing the semiconductor structure |
WO2004066385A3 (en) * | 2003-01-23 | 2005-04-14 | Infineon Technologies Ag | Semiconductor structure having a reduced connecting capacitance and method for producing the semiconductor structure |
DE10302623B4 (en) * | 2003-01-23 | 2006-12-28 | Infineon Technologies Ag | Semiconductor structure with a reduced terminal capacitance and a method for producing the semiconductor structure |
Also Published As
Publication number | Publication date |
---|---|
JPS6057701B2 (en) | 1985-12-16 |
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