JPH10261671A - Semiconductor device and fabrication therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress leakages of a signal from a lead wire to the circuit part and from the circuit part to a lead wire, while preventing an electrode pad from being stripped by embedding a columnar insulating member into a semiconductor layer underlying the electrode pad. SOLUTION: Since a large number of columnar insulating members 24 are formed in an n-type epitaxial layer 12 surrounded by an isolator 22, the electrode area of parasitic capacitor, and thereby the parasitic capacitance, can be decreased. Since the leakage of signal can be suppressed, noise and modulation can be made small. Since the n-type epitaxial layer 12 surrounded by the isolator 22 is hard and the crystal is formed continuously, resistance is increased against a pressure being applied from above this restraining deformation. Since the n-type epitaxial layer 12 is not deformed, even if it is subjected to stresses at the time of bonding a lead wire 20, an electrode pad 16 can be prevented from being stripped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an electrode pad for connecting a lead wire by bonding and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional semiconductor device having an electrode pad will be described with reference to FIG. On a p-type semiconductor substrate 110,
An n-type epitaxial layer 112 is formed. On the n-type epitaxial layer 112, a silicon oxide film 114 is formed. An electrode pad 116 is formed on the silicon oxide film 114, and around the electrode pad 116,
An insulating film 118 is formed to cover the periphery of the electrode pad 116. A lead wire 120 is connected to the upper part of the electrode pad 116 by bonding. Also, n
Circuit section (not shown) via the epitaxial layer 112
In order to reduce the signal sneaking around, the electrode pad 11
An element isolator 122 made of polycrystalline silicon is formed so as to surround the n-type epitaxial layer 112 below 6.

An equivalent circuit of the conventional semiconductor device shown in FIG. 12 will be described with reference to FIG. As shown in FIG.
The electrode pad 116 includes a parasitic capacitance C ₀₁ between the electrode pad 116 and the n-type epitaxial layer 112, an impedance Z ₀₁ of the n-type epitaxial layer 112, and a parasitic capacitance at a junction between the n-type epitaxial layer 112 and the p-type semiconductor substrate 110. The capacitance C ₀₂ and the impedance Z ₀₂ of the p-type semiconductor substrate 110
Are connected in series and connected to the ground electrode GND.

On the other hand, the circuit section 126 is
It is considered that the parasitic capacitance C _{03 at} the junction with the p-type semiconductor substrate 110 and the impedance Z ₀₄ of the p-type semiconductor substrate 110 are connected in series and are connected to the ground electrode GND. Here, considering the impedance Z ₀₃ between the electrode pad 116 below the p-type semiconductor substrate 110 and the circuit portion 126 below the p-type semiconductor substrate 110, it is between the electrode pad 116 and the circuit section 126, the parasitic capacitance C _01, The connection is made via the impedance Z ₀₁ , the parasitic capacitance C ₀₂ , the impedance Z ₀₃ , and the parasitic capacitance C ₀₃ .

In the conventional semiconductor device, the parasitic capacitances C ₀₁ , C
_{Since the} signals ₀₂ and _C03 were large, the signal flowing through the lead wire 120 wrapped around the circuit portion 126, and the signal flowing through the circuit portion 126 wrapped around the lead wire 120, causing noise and modulation. Accordingly, a method has been proposed in which a parasitic capacitance between the electrode pad 116 and the surface of the p-type semiconductor substrate 110 is reduced by embedding an insulating layer made of thick polycrystalline silicon below the electrode pad 116. In the proposed method, a thick insulating layer is buried under the electrode pad 116 to increase the distance between the electrodes of the parasitic capacitance, so that the parasitic capacitance between the electrode pad 116 and the surface of the p-type semiconductor substrate 110 can be reduced. . For this reason, it is possible to reduce a signal wraparound from the lead wire 116 to the circuit portion 126 and a signal wraparound from the circuit portion 126 to the lead wire 120, and to reduce noise and modulation.

[0006]

However, in the proposed method, since the insulating layer of polycrystalline silicon is soft, the electrode pad and the insulating layer are deformed when the lead wire 120 is bonded to the electrode pad. In some cases, the electrode pad 116 was peeled off. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device in which a signal wraparound from a lead wire to a circuit portion and a signal wraparound from a circuit portion to a lead wire are small and an electrode pad is not peeled off.

[0007]

An object of the present invention is to provide a base substrate, a semiconductor layer formed on the base substrate, an electrode pad formed on the semiconductor layer via an insulating film, And a columnar insulating member embedded in the semiconductor layer. Thereby, since the columnar insulating member is embedded in the semiconductor layer, the parasitic capacitance can be reduced, and the signal sneak from the lead wire to the circuit part and the signal sneak from the circuit part to the lead wire can be reduced. And a semiconductor device with a small size can be provided. Further, since the semiconductor layer is hard and does not deform even when stress is applied during bonding of the lead wire, a semiconductor device in which the electrode pad does not peel off can be provided.

In the above-described semiconductor device, it is preferable that the semiconductor device includes a plurality of the insulating members, and the plurality of the insulating members are separated from each other by the continuous semiconductor layer. In the above semiconductor device, it is preferable that the plurality of insulating members are arranged in a matrix.

In the above semiconductor device, it is preferable that the base substrate is an SOI substrate. In the above-described semiconductor device, it is preferable that the insulating member is an insulating structure formed at the same time as an element isolator that defines an element region of the base substrate. In the above-described semiconductor device, it is preferable that the insulating member is formed of polycrystalline silicon.

In the above semiconductor device, it is desirable that the semiconductor layer and the underlying substrate have different conductivity types from each other. Further, the above object is to provide a semiconductor layer forming step of forming a semiconductor layer on a base substrate, an insulating film forming step of forming a first insulating film on the semiconductor layer, An etching step of patterning the semiconductor layer to form a hole reaching the base substrate; an insulating member forming step of selectively forming an insulating member in the hole; and a second insulating film on the insulating member. Forming an insulating film, and forming an electrode pad on the first and second insulating films above the insulating member. Is done.

In the above-described method for manufacturing a semiconductor device, it is preferable that a plurality of the holes are formed in a matrix in the etching step. In the above-described method for manufacturing a semiconductor device, it is preferable that, in the insulating member forming step, an element isolator defining an element region of the base substrate be formed at the same time.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] The semiconductor device according to a first embodiment of the present invention will be explained with reference to FIGS. FIG. 1 is a sectional view of the semiconductor device according to the present embodiment. FIG. 2 is an equivalent circuit of the semiconductor device shown in FIG.

An n-type epitaxial layer 12 is formed on a p-type semiconductor substrate 10. n-type epitaxial layer 1
2, a silicon oxide film 14 is formed. An electrode pad 16 is formed on the silicon oxide film 14, and an insulating film 18 is formed around the electrode pad 16 so as to cover the periphery of the electrode pad 16. A lead wire 20 is connected to the upper part of the electrode pad 16 by bonding.

Further, in order to reduce a signal from flowing to a circuit portion (not shown) via the n-type epitaxial layer 12, an element isolator 22 is provided so as to surround the n-type epitaxial layer 12 below the electrode pad 16. Are formed. Also,
In the n-type epitaxial layer 12 surrounded by the element isolator 22, a columnar insulating member 24 is formed to reach the p-type semiconductor substrate. At this time, a large number of insulating members 24 are formed in a matrix. Further, in the n-type epitaxial layer 12 surrounded by the element isolator 22, crystals are continuously formed.

The element isolator 22 and the insulating member 24
Is to reduce stress on other members due to thermal expansion,
It is desirable to form with a soft insulating material such as polycrystalline silicon. The equivalent circuit of the semiconductor device according to the present embodiment shown in FIG. 1 will be described with reference to FIG.

The electrode pad 16 has a parasitic capacitance C ₁₁ between the electrode pad 16 and the n-type epitaxial layer 12, an impedance Z ₁₁ of the n-type epitaxial layer 12, and a junction between the n-type epitaxial layer 12 and the p-type semiconductor substrate 10. a parasitic capacitance C ₁₂ parts, and the impedance Z ₁₂ of the p-type semiconductor substrate 10 are connected in series, is considered to be connected to the ground electrode GND.

On the other hand, the circuit section 26 has a parasitic capacitance C _{13 at} a junction between the circuit section 26 and the p-type semiconductor substrate 10 and an impedance Z ₁₄ of the p-type semiconductor substrate 10 connected in series.
It is considered that it is connected to the ground electrode GND. Here, the impedance Z between the p-type semiconductor substrate 10 below the electrode pad 16 and the p-type semiconductor substrate 10 below the circuit section 26 is set.
Considering the _13, between the electrode pad 16 and the circuit section 26, the parasitic capacitance C _11, the impedance Z _11, a parasitic capacitance C _12, the impedance Z _13, and will be connected via the parasitic capacitance C _13.

However, in the semiconductor device according to the present embodiment, since a large number of columnar insulating members 24 are formed in the n-type epitaxial layer 12 surrounded by the element separator 22, the electrodes of the parasitic capacitances C ₁₁ and C ₁₂ are formed. The area can be reduced, and the parasitic capacitances C ₁₁ and C ₁₂ can be reduced. Accordingly, the signal sneak from the lead wire 20 to the circuit part 26 and the signal sneak from the circuit part 26 to the lead wire 20 can be reduced, so that noise and modulation can be reduced.

Further, since the n-type epitaxial layer 12 surrounded by the element isolation body 22 is hard and has crystals formed continuously, the n-type epitaxial layer 12 has a high resistance to a pressure applied from above and is hardly deformed. Even if stress is applied during bonding of the lead wire 20, the electrode pad 16 and the n-type epitaxial layer 12 below the electrode pad 16 are not deformed, so that the electrode pad 16 can be prevented from peeling.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 to 5
Is a process sectional view illustrating the method for manufacturing the semiconductor device according to the present embodiment. First, the CVD is performed on the p-type semiconductor substrate 10.
(Chemical Vapor Deposition
An n-type epitaxial layer 12 is formed by the method (n) (see FIG. 3A).

Next, a silicon oxide film 14 is formed on the n-type epitaxial layer 12 (see FIG. 3B). Next, an SiN film 28 is formed on the silicon oxide film 14,
A resist 30 is applied, and thereafter, a pattern of trenches 32 surrounding electrode pads formed in a later step and a pattern of square holes 34 arranged in a matrix are
Pattern by lithography. (FIG. 3 (c)
reference).

Next, a trench 32 and a hole 34 are formed by anisotropic etching so as to reach the p-type semiconductor substrate 10 (see FIG. 4A). At this time, an element isolator defining an element region of the p-type semiconductor substrate 10 is also formed (not shown). Next, the silicon oxide film 14 is formed in the trench 32 and the hole 34. afterwards,
On the silicon oxide film 14, in the trench 32, and in the hole 3
Then, a polycrystalline silicon layer 36 is formed in 4 (see FIG. 4B).

Next, the polysilicon layer 36 above the upper surface of the silicon oxide film 14 is removed by polishing (see FIG. 4C). Next, the upper portion of the polycrystalline silicon layer 36 is oxidized to form the element isolator 22 and the insulating member 24 (see FIG. 5A). Next, the electrode pad 16 is formed above the insulating member 24. Thereafter, an insulating film 18 is formed around the electrode pad 16 so as to cover the periphery of the electrode pad 16 (see FIG. 5B).

Next, the lead wire 20 is connected to the upper part of the electrode pad 16 by bonding (see FIG. 5C). Thus, the semiconductor device according to the present embodiment can be manufactured. [Second Embodiment] The semiconductor device according to a second embodiment of the present invention will be explained with reference to FIGS. FIG. 6 is a sectional view of the semiconductor device according to the present embodiment. The same components as those of the semiconductor device according to the first embodiment shown in FIGS. 1 to 5 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

The main feature of the semiconductor device according to the present embodiment is that an SOI substrate is used instead of the base substrate of the semiconductor device according to the first embodiment. p-type semiconductor substrate 1
On the zero, a silicon oxide film 38 is formed. On the silicon oxide film 38, the n-type epitaxial layer 12 is formed. As in the first embodiment, a silicon oxide film 14 is formed on the n-type epitaxial layer 12. An electrode pad 16 is formed on the silicon oxide film 14, and an insulating film 18 is formed around the electrode pad 16 so as to cover the periphery of the electrode pad 16. A lead wire 20 is connected to the upper part of the electrode pad 16 by bonding.

As in the first embodiment, an element isolator 22 is formed so as to surround the n-type epitaxial layer 12 below the electrode pad 16. The columnar insulating member 2 is provided on the n-type epitaxial layer 12 surrounded by the element isolator 22.
4 is formed to reach the p-type semiconductor substrate. At this time, a large number of insulating members 24 are formed in a matrix. Further, in the n-type epitaxial layer 12 surrounded by the element isolator 22, crystals are continuously formed.

The element isolator 22 and the insulating member 24
Is to reduce stress on other members due to thermal expansion,
It is desirable to form with a soft insulating material such as polycrystalline silicon. The equivalent circuit of the semiconductor device according to the present embodiment is:
This is the same as the equivalent circuit of the semiconductor device according to the first embodiment.

Therefore, similarly to the semiconductor device according to the first embodiment, n surrounded by the electrode pad 16 and the element isolator 22 is used.
The parasitic capacitance between the n-type epitaxial layer 12 and the n-type epitaxial layer 12 surrounded by the element isolator 22 and the p-type semiconductor substrate 10 can be reduced. For this reason, it is possible to reduce the signal wraparound from the lead wire 20 to the circuit unit 26 and the signal wraparound from the circuit unit 26 to the lead wire 20, thereby reducing noise and modulation.

Further, similarly to the semiconductor device according to the first embodiment, the n-type epitaxial layer 12 surrounded by the element isolator 22 is hard and has crystals formed continuously. Highly resistant and difficult to deform. Even if stress is applied during the bonding of the lead wire 20, the electrode pad 16 and the n
Since the shaped epitaxial layer 12 is not deformed, peeling of the electrode pad 16 can be prevented.

Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 7 to 11 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. First, an SOI (Silicon On Insul) in which a single crystal n-type semiconductor layer 40 is formed on a p-type semiconductor substrate 10 with a silicon oxide film 38 interposed therebetween.
a) A substrate 42 is prepared (see FIG. 7A). S
The OI substrate 42 is formed, for example, by injecting oxygen into a bonded SOI substrate in which an n-type semiconductor layer 40 is bonded to a p-type semiconductor substrate 10 on which a silicon oxide film 38 is formed, or into a p-type single crystal silicon substrate. SIMOX (Separatio) in which a silicon oxide film is embedded inside the substrate
An (n Implanted Oxygen) substrate may be used.

Next, the n-type semiconductor layer 40 is formed by the CVD method.
An n-type epitaxial layer 12 is formed thereon (FIG. 7B)
reference). Next, a silicon oxide film 14 is formed on the n-type epitaxial layer 12 (see FIG. 7C). Next, a SiN film 28 is formed on the silicon oxide film 14, a resist 30 is applied, and then a pattern of trenches 32 surrounding electrode pads to be formed in a later process, and square holes arranged in a matrix are formed. The pattern 34 is patterned by lithography (see FIG. 8A).

Next, trenches 32 and holes 34 are formed on the surface of the silicon oxide film 38 by anisotropic etching (see FIG. 8B). At this time, an element isolator defining an element region of the p-type semiconductor substrate 10 is also formed (not shown). Next, the inside of the trench 32 and the hole 34
A silicon oxide film 14 is formed therein. Thereafter, a polycrystalline silicon layer 36 is formed on the silicon oxide film 14, in the trench 32, and in the hole 34 (see FIG. 9A).

Next, the polysilicon layer 36 above the upper surface of the silicon oxide film 14 is removed by polishing (see FIG. 9B). Next, the upper portion of the polycrystalline silicon layer 36 is oxidized to form the element isolation body 22 and the insulating member 24 (see FIG. 10A). Next, the electrode pad 16 is formed above the insulating member 24. Thereafter, an insulating film 18 is formed around the electrode pad 16 so as to cover the periphery of the electrode pad 16 (see FIG. 10B).

Next, a lead wire 20 is connected to the upper part of the electrode pad 16 by bonding (see FIG. 11). Thus, the semiconductor device according to the present embodiment can be manufactured. [Modified Embodiments] The present invention is not limited to the above embodiment, and various modifications are possible.

For example, in the first or second embodiment,
Although the insulating members are formed in a matrix, the insulating members may be arranged in any manner as long as the crystals of the epitaxial layer surrounded by the element separator are continuously formed. In the first or second embodiment, the material of the insulating member may not be polycrystalline silicon, but it is desirable to select an appropriate insulating material in consideration of stress on other members due to thermal expansion. .

In the first embodiment, a p-type epitaxial layer may be formed on an n-type semiconductor substrate. In the second embodiment, an SOI substrate in which a single-crystal p-type semiconductor layer is formed on an n-type or p-type semiconductor substrate via a silicon oxide film may be prepared, and a p-type epitaxial layer may be formed.

In the first or second embodiment, the conductivity type of the semiconductor substrate and the conductivity type of the epitaxial layer may be the same or different. . In the first embodiment, the n-type epitaxial layer is formed on the p-type semiconductor substrate. However, an n-type impurity is implanted above the p-type semiconductor substrate to form a buried layer such as a well or a buried diffusion layer. It may be formed.

In the second embodiment, a buried layer such as a well or a buried diffusion layer may be formed by implanting a p-type impurity above the n-type epitaxial layer.

[0039]

As described above, according to the present invention, since a large number of columnar insulating members are formed in the n-type epitaxial layer surrounded by the element isolator, the parasitic capacitance can be reduced, and the lead can be reduced. It is possible to provide a semiconductor device in which signal wraparound from a line to a circuit portion and signal wraparound from a circuit portion to a lead wire are small. Further, since the n-type epitaxial layer surrounded by the element separator is hard and does not deform even when stress is applied during bonding of the lead wire, a semiconductor device in which the electrode pad does not peel off can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit of the semiconductor device shown in FIG.

FIG. 3 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 4 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 5 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the first embodiment of the present invention;

FIG. 6 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a process sectional view (part 1) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention;

FIG. 8 is a process sectional view (part 2) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 9 is a process sectional view (part 3) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 10 is a process sectional view (part 4) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a process sectional view (part 5) illustrating the method for fabricating the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a sectional view showing a conventional semiconductor device.

FIG. 13 is an equivalent circuit of the conventional semiconductor device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... p-type semiconductor substrate 12 ... n-type epitaxial layer 14 ... silicon oxide film 16 ... electrode pad 18 ... insulating film 20 ... lead wire 22 ... element isolator 24 ... insulating member 26 ... circuit part 28 ... SiN film 30 ... resist 32 ... trench 34 ... hole 36 ... polycrystalline silicon layer 38 ... silicon oxide film 40 ... n-type semiconductor layer 42 ... SOI substrate 110 ... p-type semiconductor substrate 112 ... n-type epitaxial layer 114 ... silicon oxide film 116 ... electrode pad 118 ... insulation film 120 ... lead 122 ... isolation member 126 ... circuit section _{C 01, C 02, C 03} ... parasitic capacitance _{C 11, C 12, C 13} ... parasitic capacitance _{Z 01, Z 02, Z 03} , Z 04 ... impedance Z _{11, Z 12, Z 13,} Z 14 ... impedance GND ... ground electrode

Claims (10)

[Claims] A base substrate, a semiconductor layer formed on the base substrate, an electrode pad formed on the semiconductor layer via an insulating film, and embedded in the semiconductor layer below the electrode pad. A semiconductor device having a columnar insulating member. 2. The semiconductor device according to claim 1, further comprising a plurality of said insulating members, wherein said plurality of insulating members are separated from each other by said continuous semiconductor layer. . 3. The semiconductor device according to claim 2, wherein the plurality of insulating members are arranged in a matrix. 4. The semiconductor device according to claim 1, wherein said base substrate is an SOI substrate. 5. The semiconductor device according to claim 1, wherein the insulating member is an insulating structure formed simultaneously with an element isolator defining an element region of the base substrate. A semiconductor device characterized by the above-mentioned. 6. The semiconductor device according to claim 1, wherein said insulating member is made of polycrystalline silicon. 7. The semiconductor device according to claim 1, wherein said semiconductor layer and said base substrate have different conductivity types from each other. 8. A semiconductor layer forming step of forming a semiconductor layer on a base substrate, an insulating film forming step of forming a first insulating film on the semiconductor layer, the first insulating film and the semiconductor Pattern the layers and
An etching step for forming a hole reaching the base substrate; an insulating member forming step for selectively forming an insulating member in the hole; and an insulating film forming step for forming a second insulating film on the insulating member. And an electrode pad forming step of forming an electrode pad on the first and second insulating films above the insulating member. 9. The method of manufacturing a semiconductor device according to claim 8, wherein in the etching step, a plurality of the holes are formed in a matrix. 10. The method of manufacturing a semiconductor device according to claim 8, wherein in the insulating member forming step, an element isolator defining an element region of the base substrate is formed simultaneously. Production method.