JPH0325973A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the area of a chip of a semiconductor memory, etc., by forming a circuit having a large surface step like a peripheral circuit on a region etched from a semiconductor substrate, and forming a circuit having a small surface step like a memory cell on a region not deleted. CONSTITUTION:A silicon substrate 1 is silicon-etched, and a shallow trench region 3 is formed. The region 3 is a region to become a peripheral circuit, and the other part becomes a memory cell forming part. A silicon nitride film 5 is grown, and rotatably coated with a photoresist film 6. A separating region 7 is formed to form a gate electrode 8 and an electrode wiring layer 81. An interlayer insulating film 9 is formed on the surface. Then, a metal wiring material is deposited by sputtering, rotatably coated with a photoresist film 11, and a metal wiring layer 10 is patterned. After the layer 10 is formed, a protective film 12 is formed to be completed.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF APPLICATION IN INDUSTRY-L The present invention relates to minute semiconductor devices, particularly semiconductor memory devices.

Conventional technology The integration of semiconductor devices continues to evolve. Particularly in the case of half-bark type IF packaging, the current goal is to reduce the chip area as much as possible and improve the chip yield. In a semiconductor memory device, a memory cell portion occupies most of the chip area. Therefore, the key to manufacturing semiconductor memory devices is how to make memory cells small and stable. Conventionally, the minimum design rules for the device have been used for memory cells, and design rules with a slight margin have been used for peripheral circuits other than memory cells. The reason for this is that the memo cell part is formed by repeating the same pattern, resulting in an overall shape with few steps, whereas the peripheral circuit part has a mixture of various patterns and tends to have a very uneven shape. Minimal design rules cannot be adopted. FIG. 2 shows a cross-sectional structure of a conventional semiconductor memory device. Figure 2a is a cross-sectional view of the memory cell portion, Figure 2b
is a sectional view of a peripheral circuit portion.

Note that 1 is a silicon substrate, 2 is an isolation region, 3 is a gate electrode, 4 is an interlayer insulating film, 5 is a metal wiring layer, and 6 is a protective film. Ru.

Further, the surface of the silicon substrate 1 is as shown in FIG. It is also the same surface as b.

As described above, the cross-sectional structures of the memory cell portion and the peripheral circuit portion are quite different. As can be seen from these figures, the memory cell portion is formed in a constant continuous pattern, whereas the peripheral circuit portion currently has a fairly complex cross-sectional structure.

Problems to be Solved by the Invention However, in conventional structures, tightening the design rules for the peripheral circuit section hardly leads to a reduction in the chip area, and in the end, unless unreasonable design rules are used for the memory cell section, the chip area will decrease. could not be achieved. The present invention solves the above problems,
Although the minimum design rule of the conventional method is used for the peripheral circuit portion, an even smaller design rule can be used for the memory cell portion, and a large effect can be obtained in reducing the chip area of the semiconductor memory device.

Means for Solving the Problems In the semiconductor device of the present invention, a circuit portion with a large surface step, such as a peripheral circuit portion, is formed in a shallow trench region where a silicon substrate is shallowly cut, and a memory cell, for example, is formed in an area where the silicon substrate is not cut. A circuit portion having a smaller surface level difference than the circuit portion described above is formed.

Effect: In the structure of the present invention, a step is created in the semiconductor substrate between the memory cell forming area and the peripheral circuit forming area, and the thickness of the photoresist film during patterning is different between the memory cell forming area and the peripheral circuit forming area. come. In other words, it is possible to reduce only the thickness of the photoresist film in the area where the memory cell is to be formed. The thinner the photoresist film, the higher the resolution and the more finely patterned the memory cell area becomes possible.

Generally, the memory cell portion of a semiconductor memory device has a similar pattern repeated, and even if the thickness of the photoresist film is made thinner than that of the peripheral circuit portion, no problem will occur because the surface unevenness is small.

On the other hand, peripheral circuits generally have complex patterns and locally convex parts. Therefore, if the thickness of the photoresist film is made thinner, inconveniences may occur, but in the present invention, the photoresist film becomes thicker in the peripheral circuit portion, so that inconveniences are eliminated.

Embodiment An embodiment of the semiconductor device of the present invention will be described with reference to the drawings. A cross-sectional view of a semiconductor memory device using the present invention is shown in FIG. 1h, and a process cross-sectional view of the manufacturing method thereof is shown in FIG.
Shown in h. This semiconductor memory device includes an isolation region 7, a gate electrode 8, an electrode wiring layer 81, an interlayer insulating film 1, a metal insulation
! A peripheral circuit portion is formed by III 10 and a protective film 12, and a memory cell portion is formed by an isolation region 7, a gate electrode 8, an interlayer insulating film 9, a metal wiring layer 10, and a protective film 12 on the surface of region B other than region A. This is the structure formed.

Next, a manufacturing method for obtaining this structure will be explained.

First, a silicon oxide film 2 is selectively formed on a silicon substrate 1, and 0.5 μm silicon etching is performed using this as a mask to form a shallow trench region 3 (FIG. 1a). Portion 3 is the area where the peripheral circuit will be formed, and the other parts will be the memory cell formation area.After removing the silicon oxide film, oxidation is performed, and a silicon nitride film 5 is grown to a thickness of 150 nm using the LPCVD method. , 7-1. A resist film 6 is spin-coated to a thickness of 1 μm (FIG. 1h).

At this time, the film thickness of the photoresist film 5 is approximately 0.5 μm in the memory cell forming area and approximately 1.0 μm in the peripheral circuit forming area.
different from. Therefore, when the silicon nitride film 5 is patterned, finer patterning is naturally possible in the area where the memory cell is to be formed (FIG. 1C). continue,
Oxidation is performed using the silicon nitride film 5 as a mask to form isolation regions 7 (FIG. 1d). Next, game 1 on the surface
After forming the oxide film, a polycrystalline silicon film is selectively formed to form the gate electrode 8 and the electrode wiring layer 81 (first
Figure e). Then, an interlayer insulating film 9 is formed on the surface (FIG. 1f). Next, metal wiring material is deposited by sputtering,
A photoresist film 11 is spin-coated to a thickness of 1.5 μm, and the metal wiring layer 10 is patterned (first [Jg).

As shown in FIG. 1g, the thinnest portion of the photoresist film on the metal wiring material is 0.6 μm in both the memory cell portion and the peripheral circuit portion. By providing a step difference between the memory cell formation portion and the peripheral circuit formation portion in this way, the minimum thickness of the photoresist film can be made uniform in the subsequent process where the step difference is large. In other words, it is possible to form patterns in both the memory cell portion and the peripheral circuit portion with the minimum necessary photoresist film thickness, and miniaturization can be achieved.

After forming the metal wiring layer 10, the protective film 12 is formed and completed (FIG. 1h).

Note that in the embodiment, a semiconductor memory device was explained, but
The present invention is not limited to this, and the present invention can be applied as long as there are circuit parts with large and small surface irregularities.

Effects of the Invention As described above, by using the present invention, it is possible to easily miniaturize circuit parts with small surface irregularities such as memory cell parts and circuit parts with large surface irregularities such as peripheral circuit parts, and it is possible to miniaturize circuit parts with large surface irregularities such as peripheral circuit parts. This has a great effect on miniaturization.

[Brief explanation of drawings]

FIG. 1 is a process cross-sectional view showing a method of manufacturing a semiconductor memory device using the present invention, and FIG. 2 is a cross-sectional view of a conventional semiconductor memory device. 1...Silicon substrate, 2...Silicon oxide film, 3...Shallow trench region, 4...
... Silicon oxide film, 5 ... Silicon nitride film, 6 ... Photoresist film, 7 ...
... Separation region, 8 ... Gate electrode, 9 ...
...Interlayer insulating film, 10...Metal wiring layer, 1
1... Photoresist film, 12... Protective film, 81... Electrode wiring layer.

Claims (2)

[Claims] (1) A circuit portion with a large surface step is formed in a recessed region on a semiconductor substrate, and a circuit portion with a smaller surface step than the circuit portion is formed on the semiconductor substrate other than the recessed region. Characteristic semiconductor devices. (2) A semiconductor device characterized in that a peripheral circuit portion is formed in a recessed region on a semiconductor substrate, and a memory circuit portion is formed on the semiconductor substrate other than the recessed region.