JPH09509792A - 支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法 - Google Patents
支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法Info
- Publication number
- JPH09509792A JPH09509792A JP8520325A JP52032596A JPH09509792A JP H09509792 A JPH09509792 A JP H09509792A JP 8520325 A JP8520325 A JP 8520325A JP 52032596 A JP52032596 A JP 52032596A JP H09509792 A JPH09509792 A JP H09509792A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- wafer
- insulating
- protective
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000000463 material Substances 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 239000010410 layer Substances 0.000 claims abstract description 165
- 239000011241 protective layer Substances 0.000 claims abstract description 25
- 235000012431 wafers Nutrition 0.000 claims description 84
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 20
- 230000001681 protective effect Effects 0.000 claims description 20
- 229910052710 silicon Inorganic materials 0.000 claims description 20
- 239000010703 silicon Substances 0.000 claims description 20
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 12
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 9
- 239000011810 insulating material Substances 0.000 claims description 6
- 239000011574 phosphorus Substances 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 claims description 5
- 239000000126 substance Substances 0.000 abstract description 7
- 238000005530 etching Methods 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 230000005669 field effect Effects 0.000 description 5
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 3
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 3
- 239000003513 alkali Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052708 sodium Inorganic materials 0.000 description 3
- 239000011734 sodium Substances 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229920003002 synthetic resin Polymers 0.000 description 2
- 239000000057 synthetic resin Substances 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000010297 mechanical methods and process Methods 0.000 description 1
- 230000005226 mechanical processes and functions Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000003678 scratch resistant effect Effects 0.000 description 1
Classifications
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H01L2221/68363—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.半導体装置を製造するにあたり、この方法が、第1の側に、絶縁層上に位置 する半導体物質の最上層を備えた半導体ウェーハで開始し、その後半導体素子お よび導電性トラックをこの半導体ウェーハの第1の側上に形成し、半導体ウェー ハのこの第1の側に支持ウェーハを接着し、物質を、半導体ウェーハの他方の第 2の側から、絶縁層が露出するまで除去する方法であって、 方法を開始する半導体ウェーハの絶縁層が、絶縁層でありかつ保護層である ことを特徴とする半導体装置の製造方法。 2.絶縁保護層が、保護物質のサブ層および絶縁物質のサブ層を有することを特 徴とする請求の範囲1記載の方法。 3.保護層のサブ層を、絶縁物質のサブ層により、いずれかの側に接着すること を特徴とする請求の範囲2記載の方法。 4.保護層のサブ層を、酸化ケイ素のサブ層により、いずれかの側に接着するこ とを特徴とする請求の範囲3記載の方法。 5.保護層のサブ層を、窒化ケイ素の層またはリンガラスの層あるいは窒化ケイ 素の層とリンガラスの層とから成る二重層により形成することを特徴とする請求 の範囲4記載の方法。 6.方法を開始する半導体ウェーハをウェーハ接着により得、これにより、第1 のケイ素ウェーハの1つの側に、酸化ケイ素の層、保護物質の層および酸化ケイ 素の層を連続的に設け、これにより、第2のウェーハの1つの側に酸化ケイ素の 層を設け、その後、これら2つのウェーハを、層を設けるこれらの側で、互いに 接着することを特徴とする請求の範囲5記載の方法。 7.第1のケイ素ウェーハ上の保護物質の層を、窒化ケイ素の層またはリンガラ スの層あるいは窒化ケイ素の層とリンガラスの層とから成る二重層により形成す ることを特徴とする請求の範囲6記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AT94203751.6 | 1994-12-23 | ||
EP94203751 | 1994-12-23 | ||
PCT/IB1995/001080 WO1996020497A1 (en) | 1994-12-23 | 1995-11-29 | Method of manufacturing semiconductor devices with semiconductor elements formed in a layer of semiconductor material glued on a support wafer |
Publications (1)
Publication Number | Publication Date |
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JPH09509792A true JPH09509792A (ja) | 1997-09-30 |
Family
ID=8217491
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8520325A Pending JPH09509792A (ja) | 1994-12-23 | 1995-11-29 | 支持ウェーハ上に接着した半導体物質の層中に半導体素子が形成した半導体装置の製造方法 |
Country Status (5)
Country | Link |
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US (2) | US5780354A (ja) |
EP (1) | EP0746875B1 (ja) |
JP (1) | JPH09509792A (ja) |
DE (1) | DE69525739T2 (ja) |
WO (1) | WO1996020497A1 (ja) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2744285B1 (fr) * | 1996-01-25 | 1998-03-06 | Commissariat Energie Atomique | Procede de transfert d'une couche mince d'un substrat initial sur un substrat final |
WO1997034317A1 (en) * | 1996-03-12 | 1997-09-18 | Philips Electronics N.V. | Method of manufacturing a hybrid integrated circuit |
JP3565090B2 (ja) * | 1998-07-06 | 2004-09-15 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
WO2000065655A1 (en) | 1999-04-23 | 2000-11-02 | Koninklijke Philips Electronics N.V. | A semiconductor device with an operating frequency larger than 50mhz comprising a body composed of a soft ferrite material |
DE19918671B4 (de) * | 1999-04-23 | 2006-03-02 | Giesecke & Devrient Gmbh | Vertikal integrierbare Schaltung und Verfahren zu ihrer Herstellung |
TW455964B (en) * | 2000-07-18 | 2001-09-21 | Siliconware Precision Industries Co Ltd | Multi-chip module package structure with stacked chips |
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JP2003291343A (ja) * | 2001-10-26 | 2003-10-14 | Seiko Epson Corp | 液体噴射ヘッド及びその製造方法並びに液体噴射装置 |
FR2871291B1 (fr) * | 2004-06-02 | 2006-12-08 | Tracit Technologies | Procede de transfert de plaques |
US7268012B2 (en) * | 2004-08-31 | 2007-09-11 | Micron Technology, Inc. | Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby |
DE102007034306B3 (de) * | 2007-07-24 | 2009-04-02 | Austriamicrosystems Ag | Halbleitersubstrat mit Durchkontaktierung und Verfahren zur Herstellung eines Halbleitersubstrates mit Durchkontaktierung |
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US4468857A (en) * | 1983-06-27 | 1984-09-04 | Teletype Corporation | Method of manufacturing an integrated circuit device |
US4870475A (en) * | 1985-11-01 | 1989-09-26 | Nec Corporation | Semiconductor device and method of manufacturing the same |
JPS63308386A (ja) * | 1987-01-30 | 1988-12-15 | Sony Corp | 半導体装置とその製造方法 |
US5065222A (en) * | 1987-11-11 | 1991-11-12 | Seiko Instruments Inc. | Semiconductor device having two-layered passivation film |
JPH0344067A (ja) * | 1989-07-11 | 1991-02-25 | Nec Corp | 半導体基板の積層方法 |
JP2617798B2 (ja) * | 1989-09-22 | 1997-06-04 | 三菱電機株式会社 | 積層型半導体装置およびその製造方法 |
US5362667A (en) * | 1992-07-28 | 1994-11-08 | Harris Corporation | Bonded wafer processing |
US5289031A (en) * | 1990-08-21 | 1994-02-22 | Kabushiki Kaisha Toshiba | Semiconductor device capable of blocking contaminants |
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US5270221A (en) * | 1992-11-05 | 1993-12-14 | Hughes Aircraft Company | Method of fabricating high quantum efficiency solid state sensors |
JP3158749B2 (ja) * | 1992-12-16 | 2001-04-23 | ヤマハ株式会社 | 半導体装置 |
US5426072A (en) * | 1993-01-21 | 1995-06-20 | Hughes Aircraft Company | Process of manufacturing a three dimensional integrated circuit from stacked SOI wafers using a temporary silicon substrate |
JPH06296023A (ja) * | 1993-02-10 | 1994-10-21 | Semiconductor Energy Lab Co Ltd | 薄膜状半導体装置およびその作製方法 |
JP3265718B2 (ja) * | 1993-06-23 | 2002-03-18 | 株式会社日立製作所 | Si転写マスク、及び、Si転写マスクの製造方法 |
JP4060882B2 (ja) * | 1995-05-10 | 2008-03-12 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 電子装置の製造方法 |
-
1995
- 1995-11-29 JP JP8520325A patent/JPH09509792A/ja active Pending
- 1995-11-29 EP EP95936730A patent/EP0746875B1/en not_active Expired - Lifetime
- 1995-11-29 WO PCT/IB1995/001080 patent/WO1996020497A1/en active IP Right Grant
- 1995-11-29 DE DE69525739T patent/DE69525739T2/de not_active Expired - Lifetime
- 1995-12-21 US US08/576,538 patent/US5780354A/en not_active Expired - Lifetime
-
1998
- 1998-05-18 US US09/080,784 patent/US6104081A/en not_active Expired - Lifetime
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US6104081A (en) | 2000-08-15 |
US5780354A (en) | 1998-07-14 |
EP0746875B1 (en) | 2002-03-06 |
DE69525739D1 (de) | 2002-04-11 |
EP0746875A1 (en) | 1996-12-11 |
WO1996020497A1 (en) | 1996-07-04 |
DE69525739T2 (de) | 2002-10-02 |
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