JPH09172006A - 半導体素子の素子分離膜の形成方法 - Google Patents

半導体素子の素子分離膜の形成方法

Info

Publication number
JPH09172006A
JPH09172006A JP8309271A JP30927196A JPH09172006A JP H09172006 A JPH09172006 A JP H09172006A JP 8309271 A JP8309271 A JP 8309271A JP 30927196 A JP30927196 A JP 30927196A JP H09172006 A JPH09172006 A JP H09172006A
Authority
JP
Japan
Prior art keywords
film
forming
pattern
material layer
resistant material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP8309271A
Other languages
English (en)
Japanese (ja)
Inventor
Meisho Chin
沈明燮
Gentaku Sai
崔源澤
▲呉▼京錫
Kyoseki Go
Kentetsu Shin
申賢哲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of JPH09172006A publication Critical patent/JPH09172006A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)
JP8309271A 1995-11-28 1996-11-20 半導体素子の素子分離膜の形成方法 Withdrawn JPH09172006A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019950044268A KR0165483B1 (ko) 1995-11-28 1995-11-28 반도체소자의 소자분리막 형성방법
KR95-44268 1995-11-28

Publications (1)

Publication Number Publication Date
JPH09172006A true JPH09172006A (ja) 1997-06-30

Family

ID=19436057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8309271A Withdrawn JPH09172006A (ja) 1995-11-28 1996-11-20 半導体素子の素子分離膜の形成方法

Country Status (2)

Country Link
JP (1) JPH09172006A (ko)
KR (1) KR0165483B1 (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100440266B1 (ko) * 1997-12-31 2004-09-18 주식회사 하이닉스반도체 반도체 소자의 필드 산화막 형성 방법

Also Published As

Publication number Publication date
KR970030643A (ko) 1997-06-26
KR0165483B1 (ko) 1999-02-01

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20040203