JPH0846091A - ボールグリッドアレイ半導体装置 - Google Patents

ボールグリッドアレイ半導体装置

Info

Publication number
JPH0846091A
JPH0846091A JP6175606A JP17560694A JPH0846091A JP H0846091 A JPH0846091 A JP H0846091A JP 6175606 A JP6175606 A JP 6175606A JP 17560694 A JP17560694 A JP 17560694A JP H0846091 A JPH0846091 A JP H0846091A
Authority
JP
Japan
Prior art keywords
wiring board
semiconductor device
package
semiconductor chip
thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6175606A
Other languages
English (en)
Japanese (ja)
Inventor
Akiro Sumiya
彰朗 角谷
Ichiro Anjo
一郎 安生
Masachika Masuda
正親 増田
Hiromichi Suzuki
博通 鈴木
Akira Haruta
亮 春田
Junichi Arita
順一 有田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6175606A priority Critical patent/JPH0846091A/ja
Priority to TW084107217A priority patent/TW296473B/zh
Priority to KR1019950021276A priority patent/KR960005965A/ko
Publication of JPH0846091A publication Critical patent/JPH0846091A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/04Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP6175606A 1994-07-27 1994-07-27 ボールグリッドアレイ半導体装置 Pending JPH0846091A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP6175606A JPH0846091A (ja) 1994-07-27 1994-07-27 ボールグリッドアレイ半導体装置
TW084107217A TW296473B (enExample) 1994-07-27 1995-07-12
KR1019950021276A KR960005965A (ko) 1994-07-27 1995-07-20 반도체 장치

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6175606A JPH0846091A (ja) 1994-07-27 1994-07-27 ボールグリッドアレイ半導体装置

Publications (1)

Publication Number Publication Date
JPH0846091A true JPH0846091A (ja) 1996-02-16

Family

ID=15999040

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6175606A Pending JPH0846091A (ja) 1994-07-27 1994-07-27 ボールグリッドアレイ半導体装置

Country Status (3)

Country Link
JP (1) JPH0846091A (enExample)
KR (1) KR960005965A (enExample)
TW (1) TW296473B (enExample)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237142A (ja) * 2000-02-22 2001-08-31 Shizuki Electric Co Inc フィルムコンデンサ及び樹脂成形部品
JP2010050488A (ja) * 2009-11-30 2010-03-04 Panasonic Corp 半導体装置およびその製造方法
JP2010177388A (ja) * 2009-01-29 2010-08-12 Panasonic Corp 半導体装置及びその製造方法
CN102668042A (zh) * 2009-12-24 2012-09-12 株式会社村田制作所 电子元器件的制造方法
JP2023006455A (ja) * 2021-06-30 2023-01-18 キオクシア株式会社 半導体デバイス及び電子デバイス
JPWO2024177013A1 (enExample) * 2023-02-20 2024-08-29

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001237142A (ja) * 2000-02-22 2001-08-31 Shizuki Electric Co Inc フィルムコンデンサ及び樹脂成形部品
JP2010177388A (ja) * 2009-01-29 2010-08-12 Panasonic Corp 半導体装置及びその製造方法
JP2010050488A (ja) * 2009-11-30 2010-03-04 Panasonic Corp 半導体装置およびその製造方法
CN102668042A (zh) * 2009-12-24 2012-09-12 株式会社村田制作所 电子元器件的制造方法
US9005736B2 (en) 2009-12-24 2015-04-14 Murata Manufacturing Co., Ltd. Electronic component manufacturing method
JP2023006455A (ja) * 2021-06-30 2023-01-18 キオクシア株式会社 半導体デバイス及び電子デバイス
US12374594B2 (en) 2021-06-30 2025-07-29 Kioxia Corporation Semiconductor device and electronic device
JPWO2024177013A1 (enExample) * 2023-02-20 2024-08-29

Also Published As

Publication number Publication date
TW296473B (enExample) 1997-01-21
KR960005965A (ko) 1996-02-23

Similar Documents

Publication Publication Date Title
KR100551641B1 (ko) 반도체 장치의 제조 방법 및 반도체 장치
US7662672B2 (en) Manufacturing process of leadframe-based BGA packages
US8253232B2 (en) Package on package having a conductive post with height lower than an upper surface of an encapsulation layer to prevent circuit pattern lift defect and method of fabricating the same
US7160759B2 (en) Semiconductor device and method of manufacturing the same
US9130064B2 (en) Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier
US5953589A (en) Ball grid array semiconductor package with solder balls fused on printed circuit board and method for fabricating the same
JP3494593B2 (ja) 半導体装置及び半導体装置用基板
KR980012316A (ko) 반도체 장치 및 그 제조 방법
JP2915282B2 (ja) プラスチックモールドした集積回路パッケージ
US7579676B2 (en) Leadless leadframe implemented in a leadframe-based BGA package
KR19980055815A (ko) 볼 그리드 어레이 반도체 패키지
KR19990085107A (ko) 반도체칩 패키지 및 그 제조방법
JPH0846091A (ja) ボールグリッドアレイ半導体装置
KR100642748B1 (ko) 리드 프레임과 패키지 기판 및 이들을 이용한 패키지
JP4626063B2 (ja) 半導体装置の製造方法
JP3875407B2 (ja) 半導体パッケージ
JP3334958B2 (ja) 半導体パッケージ及び半導体パッケージの製造方法
JPH08148526A (ja) 半導体装置
JPH08340069A (ja) リードフレーム及びこれを用いた半導体装置
JP5587464B2 (ja) 半導体装置の製造方法
JP2002151627A (ja) 半導体装置、その製造方法および実装方法
KR100195511B1 (ko) 리드 프레임을 이용한 볼 그리드 어레이 패키지
JP2004172647A (ja) 半導体装置
KR950010866B1 (ko) 표면 실장형(surface mounting type) 반도체 패키지(package)
KR100668865B1 (ko) 듀얼 본드 핑거 에프비지에이 패키지