JPH08297594A - Diagnostic device - Google Patents

Abstract

PURPOSE: To diagnose all ports from one unit of main body system device having a diagnostic process without reconnecting a cable when a device to be diagnosed which has plural ports is diagnosed. CONSTITUTION: With a diagnostic start signal from the main body system device 200, an acceptance register 1A is set and the number of a port which begins to be diagnosed is set in an initial value register 3 and a counter 9. With a diagnosis end signal from the main body system device, the counter 9 is made to count up and ports to be diagnosed are selected in order. A decoder 8 decodes the value of the counter 9 to generate and send a report correspondence diagnosis signal to the device to be diagnosed. When the value of the counter 9 reaches a value of the initial value register 3, a comparing circuit 12 generates an end signal and informs a device 300 to be diagnosed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic device used when diagnosing a device to be diagnosed, and particularly to a device to be diagnosed having a plurality of access ports from a main system device having a diagnostic processor. It relates to a diagnostic device used.

[0002]

2. Description of the Related Art Conventionally, when diagnosing a diagnostic target device having a plurality of access ports from a main system device having a diagnostic processor, one main system device is installed and each of the main system device and the diagnostic target device is installed. The diagnostics are carried out by sequentially connecting the ports to and by connecting the cables. Alternatively,
A plurality of main system devices are installed, and each main system device is connected to a different port of the device to be diagnosed for diagnosis.

Further, in the technique described in Japanese Patent Laid-Open No. 01-183751 (shown in FIG. 4), all the ports in the device to be diagnosed are connected in series in the device to be diagnosed and a cable is provided between the ports outside the device to be diagnosed. The data control unit writes data to the head input end of all ports connected in series, and the writing and reading are repeated to read at the next port, and diagnosis is performed from the terminal device of the main system device. .

[0004]

In the above-mentioned conventional diagnostic method, in order to diagnose all the ports of the device to be diagnosed from one main system device having the diagnostic processor, the cables for all the ports are reconnected. Is required and the diagnosis time is long.

In addition, when the main system devices are installed by the number of ports and the devices are connected to each port for diagnosis, the installation area increases and the diagnosis cost also increases.

Further, the technique disclosed in Japanese Patent Laid-Open No. 01-183751 has a drawback in that a portion of the hardware that cannot be diagnosed remains because the diagnosis is performed by a connection different from the case where the device to be diagnosed actually operates.

[0007]

The first diagnostic device of the present invention comprises: (a) each of the diagnostics set by these signals provided corresponding to each of the processor port diagnostic start signals from a plurality of diagnostic processors. A plurality of acceptance registers which are reset by each of the processor port diagnosis end signals from the processor and output a port diagnosis execution signal respectively, and (b) indicate the port number to be first diagnosed by inputting the port diagnosis execution signal. An encoder that outputs a first initial port signal, (c) an initial value register that inputs the first initial port signal and outputs a second initial port signal, and (d) all of the processor port diagnostic end signals A first logical sum circuit that generates a logical sum of the above and outputs it as a port diagnosis end logical sum signal; and (e) the second initial port signal and the addition signal. And (f) the counter input signal is selected by the port diagnosis end logical sum signal and output as a counter input signal, and (f) the counter input signal is fetched by the port diagnosis end logical sum signal and output as a diagnosis execution port signal. A counter, (g) an adder that inputs the diagnosis execution port signal and outputs a signal obtained by adding 1 to the signal as the addition signal, and (h) decodes the diagnosis execution port signal as a port corresponding diagnosis execution signal. A decoder for outputting, (i) a second logical sum circuit for generating a logical sum of all of the processor port diagnosis execution signals from the diagnosis processor and outputting a port diagnosis execution logic sum signal, and (j) the port A logical product of each of the corresponding diagnosis execution signals and the port diagnosis execution logical sum signal is generated, and the port correspondence diagnosis signal is transmitted to the device under diagnosis. A first AND circuit which forces, the register for outputting a comparison circuit valid signal is set by the (k) said port diagnosis end logical sum signal,
(L) When the comparison circuit valid signal is set, a comparison circuit that compares the second initial port signal with the diagnosis execution port signal and outputs the result as an all-ports diagnosis end signal to the device under diagnosis, (M) A diagnostic data selection circuit that selects one of the processor diagnostic data from each diagnostic processor according to the first initial port signal and outputs it as diagnostic data to the device under diagnosis.

A second diagnostic device of the present invention is, in addition to the first diagnostic device, an inverter circuit for generating an inverted signal of the all-port diagnostic end signal, an output of the inverter circuit and each of the port diagnostics. A second AND circuit that generates a logical product with the running signal and outputs a non-diagnostic signal to each diagnostic processor.

[0009]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

Referring to FIG. 1, the acceptance register 1A,
1B, 1C and 1D are connected to a main body device having a diagnostic processor. The encoder 2 encodes the output of the acceptance register, and the initial value register 3 holds the output of the encoder. The first OR circuit 4 is connected to the main body device 20.
It is connected to 0, and its output controls the selector 5 (selection circuit) and the counter 6. The selector 5 selects one of the outputs of the encoder 2 and the adder circuit 7, the counter 6 holds the output of the selector 5, and the adder 7 adds "1" to the output of the counter 6. The second logical sum circuit 9 creates a logical sum of the signals from the main system device, and the output thereof is logically ANDed with the respective outputs of the decoder 8 by the first logical product circuits 10A, 10B, 10C and 10D to perform diagnosis. It is output to the target device 300. The register 11 is set by the output of the first OR circuit 4, and its output becomes the enable signal of the comparison circuit 12. The comparison circuit 12 compares the outputs of the initial value register 3 and the counter 6 and outputs the result to the diagnosis target device 300. The inverter circuit 13 inverts the output of the comparison circuit 12, and the output of the inverter circuit 13 and the outputs of the reception registers 1A, 1B, 1C and 1D are second AND circuits 14A, 14B, 1
The logical product is taken by 4C and 14D and output to the main system device 200. The processor diagnostic data from the main system device 200 is selected by the selector 15 and the diagnostic target device 30 is selected.
It is output to 0.

FIG. 2 is a system configuration diagram showing the connection between the diagnostic device 100 of the present invention shown in FIG. 1, the main system 200, and the device 300 to be diagnosed.

FIG. 3 is a timing diagram showing the operation of the embodiment of the present invention.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3.

For the sake of convenience, a case where the main system device is connected to the acceptance register 1A of the diagnostic device will be described.

Main system device 200 having a diagnostic processor
When the processor port diagnosis start signal 20A is output from the CPU, the acceptance register 1A is set to "1". 1A
The port diagnosis in-progress signal 24A, which is the output of, is output to the encoder 2.

The encoder 2 has a port diagnostic execution signal 24.
The port number of the diagnosis target device 300 that starts the diagnosis is encoded from the values of A, 24B, 24C, and 24D.
In this case, only 24A is "1", and "0" is output from the encoder 2 as the first initial port signal 25. This first initial port signal is received and held by the initial value register 3.

The selector 5 selects the first initial port signal 25 from the encoder 2 and outputs the counter input signal 26. The counter input signal 26 is set in the counter 6 at the same time when the initial value register 3 is set, and the diagnostic execution port signal 27 is output.

The diagnostic execution port signal 27 is input to the decoder 8 and decoded. Port corresponding diagnostic execution signals 28A, 28B, 28C and 2 which are outputs of the decoder 8
8D corresponds to each port of the diagnosis target device 300,
Only the corresponding port number of the diagnosis is decoded to be "1".

Next, the main body system device 200 outputs the processor diagnostic execution signal 20C after an appropriate time from outputting the processor port diagnostic start signal 20A. This signal is output while performing diagnostics on the port. In the second AND-OR circuit 9, processor diagnostic execution signals 20C, 21C, 22C and 23C from all the main system devices
The logical sum of is taken. In this case, the value of 20C is directly output as the logical sum signal 29 during the port diagnosis execution.

The logical product of each of the port-corresponding diagnosis execution signals 28A, 28B, 28C and 28D from the decoder 8 and the port-diagnosis execution logic sum signal 29 is obtained by the first AND circuit 10A, 10B, 10C, 10D. Then, the port corresponding diagnostic signals 32A, 32B, 32C and 32D are output. These 32A to 32D correspond to the ports to be diagnosed, and the device to be diagnosed 300 receives this signal at the corresponding ports and carries out the diagnosis. in this case,
Only 10A becomes "1" and port 0 is diagnosed. As the diagnostic data, the processor diagnostic data 20D from the main body device 200 is selected by the diagnostic data selection circuit 15 by the first initial port signal 25, and is output as diagnostic data 35 to the diagnostic target device 300. The diagnosis target device 300 performs the diagnosis of the port section and the inside by using the diagnosis data 35.

Next, when the diagnosis of the port 0 is completed, the main body device 200 turns off the processor diagnosis execution signal 20C. As a result, the port corresponding diagnostic signal 32A is turned off. The diagnosis target device recognizes this and finishes the diagnosis of the port.

After a suitable time, the main unit 200
Outputs the processor port diagnosis end signal 20B. The acceptance register 1A is reset by this 20B, and the port diagnosis in-progress signal 24A becomes "0". In addition, processor diagnosis end signals 20B, 21B from the main system device,
The logical sum of 22B and 23B is taken by the first logical sum circuit 4 and output as the port diagnosis end logical sum signal 30.

At the same time that the diagnosis acceptance register 1A is reset, the selector 5 selects the addition signal 31 of the output of the adder 7, that is, the value obtained by adding "1" to the counter, by the port diagnosis end logical sum signal 30. The counter 6 is set.

At the same time, the register 11 is set,
The comparison circuit valid signal 34 output from the register 11 becomes "1", and the comparison circuit 12 becomes valid. At this point, the output second initial port signal 33 of the initial value register 3 is "0", and the diagnostic execution port signal 27 of the output of the counter 6 is "1". Therefore, the all-port diagnosis end signal of the output of the comparison circuit 12 is "0", which indicates that there is a port whose diagnosis has not been completed yet.

Next, the main body system device 200 starts the diagnosis of the port 1 by using the process support diagnosis start signal 20.
Output A. As a result, the diagnosis of port 1 is started as in the case of port 0. In this case, since the value of the counter 6 is "1", the port corresponding diagnostic signal 32B is output. When the diagnosis is completed, the main body system device 200 outputs the processor port diagnosis end signal 20B and the counter 6 is counted up to "2".

Similarly, the diagnosis of port 2 and port 3 is executed. The counter 6 returns to "0" by the processor port diagnosis end signal 20B indicating the end of the diagnosis of the port 3.
Here, a match is detected in the comparison circuit 12, and the all-port diagnosis end signal 30 is output to the diagnosis target device 300. As a result, the diagnosis target device 300 recognizes the end of diagnosis of all ports.

Further, the inverter output signal 36 which is the output of the inverter circuit 13 becomes "0", and the second AND circuit 14A is ANDed with the port diagnostic execution signal 24A to obtain the port diagnostic non-execution signal 20E. It becomes "0". This signal is received by the main system device 200 and recognizes that the main system device 200 has completed the diagnosis of all ports.

The case where the main system device is connected to the reception register 1A has been described above.
Even when connected to B, 1C, and 1D, diagnosis of all ports is possible in the same manner. When connected to 1B, 1C, and 1D, the port diagnosis in-progress signals that are the outputs of the encoder 2 become "1", "2", and "3", respectively, and the ports that start diagnosis are port 1 and port, respectively. 2, port 3
Becomes

[0030]

As described above, the diagnostic device of the present invention is controlled by the processor diagnostic start signal and the processor diagnostic end signal from the main system device so that the diagnostic port is automatically changed. Since all the ports of the diagnosis target device can be diagnosed in the main body system device without connecting cables, there is an effect that the diagnosis time can be shortened.

Further, since the diagnosis can be made with one main body apparatus, there is an effect that the installation area can be reduced and the amount of the main body apparatus can be reduced.

Further, since the same connection as in the actual operating state is made, there is an effect that all the hardware of the device to be diagnosed can be diagnosed without omission.

[Brief description of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

FIG. 3 is a timing diagram showing the operation of the embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

1A, 1B, 1C, 1D Reception register 2 Encoder 3 Initial value register 4, 9 Logical sum circuit 5, 15 Selector 6 Counter 7 Adder 8 Decoder 10A, 10B, 10C, 10D Logical product circuit 11 Register 12 Comparison circuit 13 Inverter circuit 14A, 14B, 14C, 14D AND circuit 20A, 21A, 22A, 23A Processor port diagnostic start signal 20B, 21B, 22B, 23B Processor port diagnostic end signal 20C, 21C, 22C, 23C Processor port diagnostic in-progress signal 20D, 21D , 22D, 23D Processor diagnosis data signal 20E, 21E, 22E, 23E Port diagnosis non-execution signal 24A, 24B, 24C, 24D Port diagnosis execution signal 25, 27 Initial port signal 26 Counter input signal 28A, 28B, 2 C, 28D port corresponding diagnostic execution signal 29 Port diagnostic under execution logical sum signal 30 Port diagnostic end logical sum signal 31 Addition signal 32A, 32B, 32C, 32D Port corresponding diagnostic signal 33 Second initial port signal 34 Comparison circuit valid signal 35 diagnostic data 36 inverter output signal 100 diagnostic device 200, 201, 202, 203 main system device 300 diagnostic target device

Claims (2)

[Claims] (A) Port diagnosis is set by these signals provided corresponding to each of the processor port diagnostic start signals from a plurality of diagnostic processors and reset by each of the processor port diagnostic end signals from each of the diagnostic processors. (C) a plurality of acceptance registers that respectively output running signals; (b) an encoder that inputs the port diagnostic running signal and outputs a first initial port signal indicating a port number to be diagnosed first; An initial value register for inputting the first initial port signal and outputting a second initial port signal, and (d) generating all logical sums of the processor port diagnosis end signals and outputting them as port diagnosis end logical sum signals. A first logical sum circuit, and (e) one of the second initial port signal and the addition signal, the port diagnosis end logical sum signal A counter selection circuit for selecting and outputting as a counter input signal, (f) a counter for fetching the counter input signal by the port diagnosis end logical sum signal and outputting as a diagnosis execution port signal, and (g) the diagnosis execution port signal. An adder that outputs a signal that is input and adds 1 to this as the addition signal; (h) a decoder that decodes the diagnosis execution port signal and outputs it as a port corresponding diagnosis execution signal; and (i) from the diagnosis processor No. 2 that generates a logical sum of all the processor port diagnosis in progress signals and outputs the port diagnosis in progress logic sum signal
And (j) a logical product of each of the port-corresponding diagnostic execution signals and the port-diagnostic executing logical sum signal is generated, and the port-corresponding diagnostic signal is output to the device under diagnosis.
AND circuit, (k) a register for outputting a comparison circuit valid signal which is set by the port diagnosis end logical sum signal, and (l) when the comparison circuit valid signal is set, the second initial port signal Of the processor diagnostic data from each of the diagnostic processors, and a comparison circuit for comparing the result with the diagnostic execution port signal and outputting the result as an all-port diagnostic end signal to the device under diagnosis.
And a diagnostic data selection circuit which outputs the diagnostic data to the device to be diagnosed as a diagnostic data by the initial port signal. 2. An inverter circuit for generating an inversion signal of the all-port diagnosis end signal, and a logical product of an output of the inverter circuit and each of the port diagnosis execution signals to generate a diagnosis non-completion signal for each diagnostic processor. 2. The diagnostic device according to claim 1, further comprising: