JPH0772788A - Programmable controller and module discriminating method - Google Patents

Abstract

PURPOSE:To extend interface modules in number without increasing signal lines to a CPU module. CONSTITUTION:When interface modules 100a and 100b are connected to the CPU module 200, the interface modules 100a and 100b are provided with module discrimination signal generating means 130a and 130b which generate signals for discriminating their modules, and the means 130a and 130b are connected to each other between the interface modules 100a and 100b. A module discrimination signal generated by one interface module 100b is outputted to the other interface module 100a, which generates its module discrimination signal. The interface modules 100a and 100b generates the module discrimination signals individually and automatically, so the signal lines to the CPU modules need not be increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller and a method of identifying a module used in the programmable controller.

[0002]

2. Description of the Related Art A programmable controller comprises a CPU module which is a central processing unit, and an interface module which is connected to and controlled by the CPU module. In this programmable controller, it is necessary to recognize what kind of interface module is connected. Therefore, it is common to provide a circuit for generating and outputting an ID code (recognition code) unique to the interface module. Has been done in.

FIG. 5 shows a conventional programmable controller disclosed in Japanese Patent Laid-Open No. 63-280303.
CPU module 10 and interface module 2
0 and 0 are connected. The CPU module 10 includes a CPU 17 that performs main control, a storage unit that includes a RAM 15 and a ROM 16, an address output unit 11 that outputs an address signal, a module decoder 12 that selects an interface module, and an input port 13 that receives data. And an output port 14 for outputting data. On the other hand, the interface module is composed of a data selection circuit 21 for selecting data according to an address and an ID code generation circuit 22 for generating an ID code for an address signal.

In the programmable controller having such a configuration, the CPU module 10 activates the module decode signal Bm of the recognition target module and the initial reset signal IR to recognize the interface module 20, and outputs a predetermined address signal.
Receiving this, the interface module 20 judges that it is a recognition request by the initial reset signal IR, and the ID code D corresponding to the interface module is C
It is sent to the CPU (calculation means) 17 of the PU module 10, and the calculation means recognizes the interface module based on this ID code D. This makes an independent ID
Unique ID of the interface module 20 without the need for dedicated signal lines for code or dedicated input ports
Code recognition is possible.

[0005]

However, in the conventional configuration, since the module decode signal Bm of the interface module 20 is connected to the CPU module 10 in parallel, the interface module 2
The number of module decode signals Bm also increases as 0 increases. As a result, the expandability of the programmable controller is the module decode signal B of the CPU module 10.
There is a problem that the limit is generated depending on the number of m.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a programmable controller and a module identification method capable of expanding an interface module without increasing the module decode signal.

[0007]

A programmable controller according to the present invention includes a CPU for performing arithmetic control, a storage means for storing data, an address output device for outputting an address signal, and a data input / output for inputting / outputting a data signal. CPU module having a CPU, an input / output processing circuit that is connected to a data input / output unit of the CPU module and processes signals input and output, and an address decoder that is connected to an address output unit of the CPU module to identify an address signal Department,
And an interface module having module identification signal generating means for generating a module identification signal for identifying the module. Further, in the module identification method of the present invention, the interface module controlled by the CPU module is provided with module identification signal generation means for generating a module identification signal for identifying the module, and the module identification signal generation means is provided between a plurality of interface modules. Are connected to each other, and the module identification signal generated by one interface module is sent to the module identification signal generation means of the adjacently connected interface module, and the interface module generates its own module. .

[0008]

In such a structure, the interface module has a module identification signal generating means for generating a module identification signal for identifying its own module, and the own module identification signal generated by one interface module is adjacent to the module identification signal. Sent to another interface module that is connected to the interface module. By receiving this module identification signal, the interface module generates its own module identification signal. By performing such processing, each interface module has an independent module identification signal, so that the CPU module can identify the interface module. Therefore, many interface modules can be connected to the CPU module, and the programmable controller can be expanded.

[0009]

First Embodiment FIG. 1 shows a programmable controller according to a first embodiment of the present invention. In this embodiment, the CPU module 2
00 to two interface modules 100a, 1
00b is connected. The CPU module 200 controls the entire programmable controller, and includes a CPU 205 for main control and a RAM 2
03 and ROM 204, an address output unit 201 for outputting an address signal, and a data input / output unit 202 for inputting / outputting a data signal.

On the other hand, each interface module 10
Reference numerals 0a and 100b are for performing processing of various signals input / output in parallel, A / D conversion, and D / A conversion, and an input / output processing unit 110 for processing input / output signals.
a, 110b and address decoding units 120a, 120b for identifying address signals, and module identification signal generation means 130a, 130b for generating module identification signals for identifying modules. The input / output processing units 10a and 110b of these interface modules 100a and 100b are connected to the data input / output unit 202 of the CPU module 200, and the address decoding unit 12
0a and 120b are connected to the address input / output unit 201 of the CPU module 200. Further, the module identification signal generating means 130a in the interface module 100a is the interface module 100b.
It is mutually connected to the module identification signal generating means 130b.

In the above configuration, the interface module 100b is the final module, nothing is connected to the Cn- ₂ terminal of the module identification signal generating means 130b of the interface module 100b, and no signal is connected to the Cn- ₂ terminal. Does not enter. As a result, the module identification signal generation means 130b knows that its own module is the final module, and generates its own module identification signal according to a pre-defined rule. Then, the module identification signal generating means 130b sends the generated module identification signal to the interface module 100a at the next stage. The module identification signal generation means 130a of the interface module 100a, to which this module identification signal is input, generates its own module identification signal according to the same rule. Through the above processing, each interface module can hold an independent individual module identification signal.
In this case, even if there is a single interface module, there is no problem because this module generates the module identification signal as the final module. With the above configuration, the programmable controller can automatically identify each module and can greatly expand the interface module.

[0012]

Second Embodiment FIG. 2 shows an interface module according to a second embodiment of the present invention. As the CPU module in this embodiment, the same one as in the first embodiment can be used, so the illustration is omitted. The portion including the state bus transceiver 111 is the input / output processing unit 110, which transmits input data to the CPU module. A portion including the 3-8 decoder 121 and the 4-bit comparator 122 is an address decoding unit 120, which selects input / output data according to an address signal and a module identification signal generated by a module identification signal generation unit 130 described later. The module identification signal generation means 130 has a 4-bit adder 131, and Cn
1 is added to the signal input from in, and it is output from Cn out as its own module identification signal,
This module identification signal is sent to the address decoding unit 1 at the same time.
Output to 20. In this case, Cnin is pulled up by the resistor 132. 3-state bus transceiver 1
The part composed of 41 is a status code generator 140, which transmits an ID code and the like to the CPU module. The address signal line An and the data signal line Dn are pulled up on the CPU module side.

In the above configuration, in the interface module of the final module, no signal is input because nothing is connected to Cn in of the module identification signal generating means 130. Moreover, since this Cn in is pulled up, the data of Cn in is hexadecimal "F".
And is input as the terminals A0 to A3 of the 4-bit adder 131. Also, the terminals B0 to B3 of the 4-bit adder 131
Since "1" is always input to, 4-bit adder 1
The output terminals S0 to S3 of 31 become “0”, and Cn ou
It is output from t. This number becomes a module identification signal and is input to the Q0 to Q3 terminals of the 4-bit comparator 122. The other input terminal P of the 4-bit comparator 122
Address signal lines A3 to A6 are connected to 0 to P3, and the P = Q terminal of the 4-bit comparator 122 becomes "0" when the address signal lines A3 to A6 are "0". Also, 3-
When the input terminal G is "0", the 8-decoder 121 selects the output corresponding to the input of the terminals A, B and C from the terminals Y0 to Y7 and outputs "0". The 3-state bus transceivers 111 and 141 are connected to the terminal Y0 of the 3-8 decoder 121.
When the input terminal G connected to ~ Y7 is "0", the data is output to the data line. As a result, the address decoding unit 120 of the final module outputs the I / O data when the address signal is 0 to 6 and the ID when the address signal is "7".
The code data will be output to the data line.

In the interface module connected to the next stage, Cn in input to the 4-bit adder 131 is "0". By the same processing as described above, the module identification signal of the module of this interface module becomes "1", whereby I / O data is obtained when the address signal is "8" to "E", and I / O data is obtained when the address signal is F. The ID code data is output to the data line. That is, the interface module is switched every time the address signal increases by 8. This makes it possible to know the nth ID code data by requesting data with the address signal set to 8n + 7 (n = 0, 1, 2, 3, ...).

According to the present embodiment as described above, the CPU of the CPU module can access the interface module in the same manner as the memory access to the ROM or RAM. Further, since the address number of each interface module to be connected is automatically generated, the user does not need to manage this. Further, by accessing a specific address (8n + 7), the ID code data of each interface module can be obtained with 8 bits, and thus the type of interface module can be determined up to 255 types. Since the data signal line Dn is pulled up, the ID code data when the interface module is not connected is “FF”. Therefore, by incrementing the address number by 7 in increments of 8 and fetching the ID code data until the data becomes "FF", the type and number of connected interface modules can be known.

[0016]

Third Embodiment FIG. 3 shows an interface module according to the third embodiment of the present invention, and the CPU module having the same configuration as that of the first embodiment is used. In FIG. 3, 3
The portion including the state bus transceiver 111 is the input / output processing unit 110, which transmits input data to the CPU module. 3-8 decoder 121 and 4-bit comparator 1
The part composed of 22 is the address decoding part 120,
Input / output data is selected by the address signal and the module identification signal generated by the module identification signal generating means 130 described later. The module identification signal generating means is composed of a 4-bit counter 133 and a 4-input OR circuit 134. The signal input from Cn in is used as a count enable signal for the 4-bit counter 133 to count the recognition clock, and the count value is used by the address decoding unit. 1
Output to 20. Cn out is a 4-input OR circuit 1
34 provides the logical sum of the 4-bit output of the 4-bit counter 133. Note that Cn in is pulled up by the resistor 132. The portion including the 3-state bus transceiver 141 is the status code generation unit 140, and I
The D code or the like is transmitted to the CPU module. The address signal line An and the data signal line Dn are pulled up on the CPU module side. System reset CPU
In addition to being connected to the reset signal of the module, the recognition clock and latch signal are connected to the output port of the CPU module. Further, Cn out of the interface module closest to the CPU module is connected to the input port of the CPU module. Also, this input port is pulled up in the CPU module.

FIG. 4 shows a flow chart of the operation in this embodiment. First, the system is reset. This is power on reset when the system is started up from the place where it is connected to the reset signal of the CPU module. As a result, the output of the 4-bit counter 133 of all interface modules becomes "0", and Cn out is also reset to "0", that is, low level. Next, the number counter is reset to 0 and the latch signal is kept at high level. When a rising edge is given to the recognition clock, an interface module in which Cn in is at a high level, that is, an interface module in which nothing is connected to Cn in at the final stage and is at a high level due to a pull-up resistor (interface module- The 4-bit counter 133 of n) counts +1 and outputs "1".
At this time, Cn out also becomes high level, and Cnin of the interface module (interface module-n-1) connected next also becomes high level. Further, when a rising edge is applied to the recognition clock, the output of the 4-bit counter 133 of the interface module-n becomes "2", and the interface module-n-
The output of the 1-bit 4-bit counter 133 is “1”. Cn out input to the CPU module as described above
Is monitored and the rising edge is continuously applied to the recognition clock until the level becomes high, so that the output of the 4-bit counter 133 of the interface module -n is "n" and the output of the interface module -n-1 is "n-1". , And similarly, the output of the interface module closest to the CPU module becomes “1”. As a result, different numerical values are output from each interface module. Then, this numerical value becomes the module identification signal and the terminals Q0 to Q4 of the 4-bit comparator 122
Input to Q3. Address signal lines A3 to A6 are connected to the other input terminals P0 to P3 of the 4-bit comparator 122, and when the address signal lines A3 to A6 match the module identification signal, P of the 4-bit comparator 122 = Q
The terminal becomes "0". Also, the 3-8 decoder 121
When the input terminal G is "0", the outputs corresponding to the input terminals A, B and C are selected from the terminals Y0 to Y7 and "0" is output. The 3-state bus transceivers 111 and 141 output data to the data line when the input terminal G connected to the terminals Y0 to Y7 of the 3-8 decoder 121 is "0". As a result, the I / O data is input / output when the module identification signal + (0 to 6) address signal is applied, and the ID code is output to the data line when the module identification signal +7 address signal is applied. That is, the address signal is 8n + 7 (where n = 0, 1, 2, 3, ...
It is possible to know the nth ID code data by requesting the data as ().

This embodiment also has the same effect as that of the second embodiment. That is, C of the CPU module
The PU can access the interface module in the same way as the memory access to the ROM and RAM, and the address number of each interface module to be connected is automatically generated. Is unnecessary, and a specific address (8n + 7)
The ID code data of each interface module can be obtained in 8 bits by accessing the.
Up to 55 types can be determined. Since the data signal line is pulled up, the ID code data when the interface module is not connected is "F
F ”. Therefore, by incrementing the address number by 7 in increments of 8 and fetching the ID code data until the data becomes "FF", the type and number of connected interface modules can be known. Furthermore, only one signal line Cn is required to connect each interface, and the wiring can be simplified.

[0019]

As described above, according to the present invention, since the module decode signal is not used, the interface module can be freely expanded without increasing the module decode signal, and the connected interface module can be expanded. Is automatically recognized, so that the user can use the interface module without being aware of the expansion of the interface module, and convenience in use is increased.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of an interface module according to a second embodiment.

FIG. 3 is a circuit configuration diagram of an interface module according to a third embodiment.

FIG. 4 is a flowchart showing the operation of the third embodiment.

FIG. 5 is a block diagram showing a conventional programmable controller.

[Explanation of symbols]

 100 interface module 110 input / output processing unit 111 3-state bus transceiver 120 address decoding unit 121 3-8 decoder 122 4-bit comparator 130 module identification signal generating means 131 4-bit adder 132 resistor 133 4-bit addition counter 134 4 input logic Sum circuit 140 Status code generator 141 Three-state bus transceiver 200 CPU module 201 Address output device 202 Data input / output device 203 RAM 204 ROM 205 CPU

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichi Arai 2-43-2 Hatagaya, Shibuya-ku, Tokyo Inside Olympus Optical Co., Ltd.

Claims (2)

[Claims] 1. A CPU module having a CPU for performing arithmetic control, a storage means for storing data, an address output device for outputting an address signal, and a data input / output device for inputting / outputting a data signal, and the CPU module. An input / output processing circuit which is connected to the data input / output device of the module and processes a signal input / output, an address decoding unit which is connected to the address output device of the CPU module and identifies an address signal, and a module identification for identifying the module A programmable controller, comprising: an interface module having module identification signal generation means for generating a signal. 2. An interface module controlled by a CPU module is provided with module identification signal generation means for generating a module identification signal for identifying a module, and the module identification signal generation means is mutually connected between a plurality of interface modules. Then, the module identification signal generated by one interface module is sent to the module identification signal generating means of the adjacently connected interface module, and the interface module generates its own module.