KR920003018Y1 - Memory sharing circuit between various type cpus - Google Patents

Abstract

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Description

Memory sharing circuit between different models of CPU

1 is a circuit diagram according to the present invention.

2 is a truth table of the control logic unit 80 in FIG.

3A and 3B are operational waveform diagrams of respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: first CPU 20: second CPU

30: shared memory 40: first decoder

50: first CPU memory selection control unit 60: second decoder

70: second CPU memory selection control unit 80: control logic unit

90: first address bus driver 92: 1a address bus driver

94: 1b address bus drive unit 100: 1st data bus transceiver unit

102: 1a data bus transceiver unit 104: 1b data bus transceiver unit

110: second address bus driver 112: second address bus driver

114: second bus address drive unit 120: second data bus transceiver unit

122: 2b data bus transceiver section 124: 2b data bus transceiver section

130: first CPU access control unit 140: second CPU access control unit

150: first CPU standby signal generator 160: second CPU standby signal generator

G1, G4: Endgate G2-G3, G5-G6: Oagate

TB1-TB8: tri-state buffer R1-R4: resistance

The present invention relates to a memory sharing circuit among the different types of CPUs (Central Processing Unit). Especially, in a digital system using a CPU, the memory sharing of two CPUs having different data sizes is used. It relates to a circuit for controlling the.

In digital systems using multiple CPUs, memory sharing between two CPUs is generally performed between synchronous CPUs that handle data of the same size.

In addition, as described above, by using memory sharing between CPUs of the same type, the use of shared memory by the two CPUs is properly controlled so that smooth memory sharing is achieved without data collision.

On the other hand, the conventional memory sharing method as described above has a problem of controlling by using a dedicated IC (Intergrated Circuit) or a specially designed memory or designing a separate interface circuit for memory sharing. In addition, in order to realize memory sharing between an 8-bit CPU and a 16-bit CPU, the memory sharing method of the same type CPU and another dedicated IC or a complicated circuit should be used. There was a flaw.

Accordingly, an object of the present invention is to provide a memory sharing circuit capable of sharing a memory between two different CPU types in a digital system using different CPU types.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a circuit diagram according to the present invention, in which the size of data to be processed is the first CPU 10 having 8 bits and the second CPU 20 having 16 bits, the first RAM 32, and the second RAM 34. Memory enable signal of the first CPU 10 and the shared memory unit 30 And a first RAM selection signal for selecting the first RAM 32 of the first CPU 10 based on the address and the address. And a second RAM selection signal for selecting the second RAM 34. A first decoder (40) for outputting the first decoder, a first CPU memory selection controller (50) for controlling the output of the first decoder (40), and a memory enable signal of the second CPU (20). And a first RAM selection signal for selecting the first RAM 32 by the second CPU 20 according to And a second RAM selection signal for selecting the second RAM 34. A second decoder 60 for outputting a signal, a second CPU memory selection controller 70 for controlling the output of the second decoder 60, an output of the first CPU memory selection controller 50, and a second CPU memory selection; Input the output of the control unit 70 and the first CPU bus enable signal by a predetermined control logic (Logic) And second CPU bus enable signal And the first RAM enable signal And second RAM enable signal The control logic unit 80 for generating a signal and the first CPU bus enable signal of the control logic unit 80 A first address bus driver 90 and a data bus, each of which is configured as a first bus address driver 92-94 and a data bus, which connect an address bus to the first CPU 10 by means of the first bus 10, respectively. The first data transceiver section 100, consisting of the first 1a, 1b data bus transceiver (102-104) and the second CPU enable signal of the control logic (80) Connecting the second address bus driver 10 and the data bus including the second bus drivers 112 to 114 to connect the address bus to the second CPU 20 to the second CPU 20. A second data bus transceiver unit 120 including the second and second data bus transceiver units 122-124, and a first CPU bus enable signal of the control logic unit 80; Or second CPU bus enable signal A first CPU access control unit 130 and a second CPU access control unit 140 controlling the access of the shared memory 30 by the first CPU 10 or the second CPU 20 by Waiting signal when the first CPU 10 attempts to access the shared memory unit 30 while the CPU 20 is accessing the shared memory 30. The first CPU standby signal generator 150 to wait for the first CPU 10 to generate the first CPU 10, the first CPU 10 is accessing the shared memory unit 30, the second CPU 20 is shared memory unit Wait signal when trying to access 30 And a second CPU wait signal generator 160 to wait for the second CPU 20 to wait.

Shared memory unit 30 of the configuration of Figure 1 is a chip Selection First and second ram enable signals of the control logic unit 80 input to the Output Enable Signal Stage Selected by Reed signal of the first CPU 10 or the second CPU 20 to the Input and write enable signal Light signal And a first RAM 32 and a second RAM 34 connected to the address bus and the data bus.

The first CPU memory selection control unit 50 is connected to an output terminal of the first decoder 50 and an input terminal of the control logic unit 80 and the second CPU bus enable signal. By the first and second RAM selection signals, respectively Resistor connected to the output terminal of the third state buffer (TB1, TB2) and the third state buffer (TB1, TB2) for controlling the output pull-up (Pull Up) of the output of the third state buffer (TB1-TB2) It consists of (R1, R2).

The second CPU memory selection control unit 70 is connected to an output terminal of the second decoder 60 and an input terminal of the control logic unit 80, and enables the first CPU bus enable signal. The first and second RAM selection signal by respectively Resistors R3 and R4 connected to output terminals of the third state buffers TB3 and TB4 and the output terminals of the third state buffers TB3 and TB4 to pull up the outputs of the third state buffers TB3 and TB4, respectively. It is composed of

The control logic unit 80 may be configured of a programmable array logic (PAL) or a predetermined logic IC to control the use of the shared memory 80 of the first CPU 10 and the second CPU 20. In the present invention, the PAL10H8 Configure using

The first CPU access control unit 130 is the first CPU enable signal of the control logic unit 80 Read signal of the first CPU And light signal It consists of a third state buffer (TB5, TB6) for controlling each.

The second CPU access control unit 140 performs a second CPU enable signal of the control logic unit 80. Read signal of the second CPU And light signal It consists of a third state buffer (TB7, TB8) for controlling each.

The first CPU standby signal generation unit 150 is composed of an AND gate G1 and an OR gate G2-G3.

The second CPU standby signal generator 160 is composed of an AND gate G4 and an oragate G5-G6.

2 is a truth table of the control logic of the control logic unit 80 in the first diagram, and (A) shows an initial state of the control logic unit 80. As shown in FIG.

(B) shows a first RAM selection signal of the first CPU 10 or the second CPU 20 when one CPU of the first CPU or the second CPU 20 intends to use the shared memory unit 30. And second RAM selection signal Control signal to use the shared memory unit 30 by the CPU requesting the use of the shared memory unit 30 for the input of Indicates the status of outputting.

(C) shows a first RAM selection signal of the first CPU 10 and the second CPU 20 when the first CPU 10 and the second CPU 20 want to use the shared memory unit 30 at the same time. And second RAM selection signal Control signal so that the second CPU 20 having a high priority with respect to the input of the shared memory unit 30 uses the shared memory unit 30; Indicates the status of outputting.

(D) is a signal combination when the first CPU 10 having the size of data to be processed is to use the first RAM 32 and the second RAM 34 of the shared memory unit 30 simultaneously. Since the first CPU 10 having 8 bits does not require the use of the first RAM 32 and the second RAM 34 at the same time, all the control signals as in the initial state of (A). Output to the disabled state of logic " 1 ".

When the first CPU 10 and the second CPU 20 intend to use the shared memory unit 30 simultaneously, the priority of using the shared memory unit 30 may be changed according to the designer's intention. have.

3A and 3B are operation waveform diagrams of the respective parts of FIG. 1, and FIG. 3A is a waveform when the first CPU 10 and the shared memory unit 30 are to be used in the state (B) of FIG. It is shown.

3B shows the state (C) of FIG. 2, that is, when the first CPU 10 and the second CPU 20 want to use the shared memory unit 30 at the same time, the second CPU 20 has a priority. The waveforms when using (30) are shown.

Hereinafter, an operation example of FIG. 1 according to the present invention will be described in detail with reference to the truth table of FIG. 2 and the operation waveforms of FIGS. 3A and 3B.

The power is now on and the first CPU 10 is an address and memory enable signal. Outputs the first decoder 40 to operate the first RAM selection signal. Or second RAM selection signal Outputs Meanwhile, the first RAM selection signal from the first CPU 10 Or second RAM selection signal Is output, the second CPU bus enable signal as shown in FIG. 2B. Is a logic " 1 ", so that the third state buffer TB1-TB2 is enabled so that the first or second RAM select signal Is input to the control logic unit 80 to request the use of the shared memory unit 30. Therefore, as shown in FIG. 2b, the control logic unit 80 enables the first CPU bus enable signal. Is output as a logic " 0 ", so that the first CPU address bus driver 90 and the first data transceiver unit 100 are enabled so that the address bus and data bus are coupled to the first CPU 10.

In addition, the third state buffer TB5-TB6 is also enabled to read signal of the first CPU 10. And light signal Also connected to the shared memory unit 30.

And the first CPU bus enable signal. The second CPU is inputted to the OR gate G5-G6 of the second CPU standby signal generator 160 and the second CPU 20 attempts to use the shared memory unit 30 being used by the first CPU 10. Wait signal at 20 Prepare to generate. In addition, the third state buffer TB5-TB6 is disabled to prevent the state change of the control logic unit 80 caused by the use of the second CPU 20. Meanwhile, the second CPU bus enable signal Is a logic " 1 " as shown in FIG. 2B, so that the address bus and data bus of the second CPU 20 are separated from the shared memory section 30, and the lead signal is And light signal Is also separated. In addition, since logic "1" is input to the oragate G2-G3 of the standby signal generator 150 of the first CPU 10, the standby signal of the first CPU 10 is input. Becomes the shape logic "1 " so that the first CPU 10 is not in the standby state, and the third state buffers TB1-TB2 are also in the enable state.

Therefore, the first CPU 10 receives the first RAM selection signal. Or second RAM selection signal Selects and uses the first RAM 32 or the second RAM 34 of the shared memory unit 30.

On the other hand, while the shared memory unit 30 is being used by the first CPU 10 as described above, the second CPU 20 uses the address and memory enable signal to duplicate the shared memory unit 30. Outputs the first RAM selection unit as shown in FIG. 3a by the second decoder 60. Or second RAM selection signal Is output, the first CPU bus enable signal that is logical " 0 " Since the third state buffer TB3-TB4 is disabled by the control logic unit 80, the first and second RAM selection signals Is not entered. Therefore, the shared memory unit 30 continues to be used by the first CPU 10.

The first and second RAM selection signals Is the first CPU bus enable signal. And the second CPU standby signal generator 160 is input to the standby signal generator 160 to wait for the signal. Is output as a logic " 0 " as shown in (j) of FIG.

Now when the use of the shared memory unit 30 of the first CPU 10 is completed, the first CPU bus enable signal Becomes a logic " 1 " as shown in Fig. 3A, and the third state buffer TB3-TB4 is enabled. Therefore, the first and second RAM select signals output from the second decoder 60. Is the first CPU bus enable signal, which is input to the control logic unit 80 and becomes logic " 1 ". Standby signal of the second CPU standby signal generator 160 by Becomes logic "1" again. Therefore, the second CPU 20 is released from the standby state and the second CPU bus enable signal as shown in the true state of FIG. 2b and (g) of FIG. 3a. 0 becomes the logic " 0 " so that the second CPU 20 uses the shared memory unit 30 in the same manner as the first CPU 10 uses the shared memory unit 30. FIG.

In addition, when the second CPU 20 uses the shared memory unit 30 and the first CPU 10 requests redundancy, the operation of the second CPU 20 when the shared memory unit 30 of the first CPU 10 is used. ) Requires the use of a duplicate, the same operation as described above.

On the other hand, the state of FIG. 2C, that is, the case where the first CPU 10 and the second CPU 20 request the use of the shared memory unit 30 at the same time will be described.

The first RAM selection signal of the first CPU 10 from the first decoder 40 by the first CPU 10 or the second CPU 20. Or second RAM selection signal Outputs a signal and a first RAM selection signal of the second CPU 20 from the second decoder 60. And the second ram selection signal In this case, the control logic unit 80 operates as in the truth table of FIG. 2C to cause the second CPU 20 having a higher priority to use the shared memory unit 30 first. In addition, when the second CPU 20 completes the use of the shared memory unit 30, the first CPU 10 uses the shared memory unit 30.

That is, the first and second RAM selection signals of the second CPU 20 as shown in FIG. Second CPU bus enable signal of logic " 0 " Is output from the control logic unit 80. Therefore, the standby signal generated by the first CPU standby signal generator 150 Is output and input to the first CPU 10, the first CPU 10 is in a standby state.

In addition, the first CPU bus enable signal And second CPU bus enable signal By the operation of FIG. 2B, the same operation as in the case of using the shared memory unit 30 by one CPU is performed.

Now when the use of the shared memory unit 30 of the second CPU 20 is completed, the second CPU bus enable signal as shown in FIG. 3B (h). Becomes the logic " 1 " again, and the first CPU wait signal generator 150 waits for the logic " 1 " Is output.

Therefore, the first CPU 10 is released from the standby state and the first bus enable signal as shown in (g) of FIG. 3b by the operation of the logic controller 80. Becomes a logic " 0 " so that the first CPU 10 uses the shared memory unit 30.

As described above, in the present invention, in a digital system using two types of CPUs having different sizes of data, the design can be simplified as a circuit for controlling the sharing of memory by this type of CPU by control logic. And the cost can be reduced.

Claims (5)

In a memory sharing control circuit between different types of CPUs, a sharing constituted by a first CPU 10 and a second CPU 20 having different sizes of data to be used, and a first RAM 32 and a second RAM 34. Memory enable signal of the memory unit 30 and the first CPU 10 And a first RAM selection signal for selecting the first RAM 32 by the first CPU 10 based on the and address. And a second RAM selection signal for selecting the second RAM 34. The first decoder 40 for outputting the first, the first CPU memory selection control unit 50 for controlling the output of the first decoder 40, and the memory enable signal of the second CPU 20 And a first RAM selection signal for selecting the first RAM 32 by the second CPU 20 according to And a second RAM selection signal for selecting the second RAM 34. Outputs the second decoder 60 outputting the second decoder, the second CPU memory selection controller 70 controlling the output of the second decoder 60, the first CPU memory selection controller 50, and the second CPU memory selection. Input of the output of the control unit 70 and the first CPU bus enable signal by a predetermined control logic And second CPU bus enable signal And the first RAM enable signal And second RAM enable signal The control logic unit 80 for generating a signal and the first CPU bus enable signal of the control logic unit 80 The first address bus driver 90 for connecting an address bus to the first CPU 10 and a first data transceiver transceiver 100 for connecting a data bus to the first CPU 10 by Second CPU bus enable signal of direct portion 80 The second address bus driver 110 connecting the address bus to the second CPU 20 and the second data transceiver transceiver 120 connecting the data bus to the second CPU 20, and the control logic part. (1) First CPU bus enable signal Or second CPU bus enable signal The first CPU access control unit 130 and the second CPU access control unit 140 for controlling the access of the shared memory unit 30 by the first CPU 10 or the second CPU 20 by the second CPU ( Waiting signal when the first CPU 10 attempts to access the shared memory unit 30 while 20 is accessing the shared memory unit 30. Generates a first CPU standby signal generation unit 150 to wait for the first CPU 10, the first CPU 10 is using the shared memory unit 30, the second CPU 20 is the shared memory unit Wait signal when trying to access 30 Memory sharing circuit between different types of CPUs, characterized in that consisting of a second CPU standby signal generator 160 for generating a second to wait for the second CPU (20). 2. The signal of claim 1, wherein the first CPU memory selection control unit 50 is connected to an output terminal of the first decoder 50 and an input terminal of the control logic unit 80. The first and second RAM selection signal by respectively It is composed of three state buffer (TB1, TB2) for controlling the, and resistors (R1, R2) connected to the output terminals of the three state buffer (TB1, TB2), respectively, pulls up the output of the three state buffer (TB1-TB2) Memory sharing circuit between different types of CPU, characterized in that. The control circuit of claim 1, wherein the second CPU memory selection control unit 70 is connected to an output terminal of the second decoder 60 and an input terminal of the control logic unit 80. The first and second RAM selection signal by respectively It is composed of three state buffer (TB3, TB4) for controlling the, and resistors (R3, R4) connected to the output terminal of the three state buffer (TB3, TB4), respectively, pulls up the output of the three state buffer (TB3, TB4) Memory sharing circuit between different types of CPU, characterized in that. The enable signal of claim 1, wherein the first CPU access control unit 130 is a first CPU of the control logic unit 80. By the first CPU lead signal And light signal Memory sharing circuit between different types of CPU, characterized in that consisting of three state buffer (TB5, TB6) for controlling each. The enable signal of claim 1, wherein the second CPU access control unit 140 is a second CPU of the control logic unit 80. 2nd CPU lead signal by And light signal Memory sharing circuit between different types of CPU, characterized in that consisting of three state buffer (TB7, TB8) for controlling each.