JP2723822B2 - Diagnostic device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a diagnostic device used for diagnosing a device to be diagnosed, and particularly to a diagnostic device having a plurality of access ports from a main unit having a diagnostic processor. It relates to the diagnostic device used.

[0002]

2. Description of the Related Art Conventionally, when diagnosing a device to be diagnosed having a plurality of access ports from a main device having a diagnostic processor, one main device is installed, and each of the main device and the device to be diagnosed is individually diagnosed. The ports are sequentially connected to each other by reconnecting cables to perform diagnosis. Or,
A plurality of this system is installed, and each main system is connected to a different port of the device to be diagnosed to perform diagnosis.

In the technique described in Japanese Patent Application Laid-Open No. 01-183751 (shown in FIG. 4), all ports in a device to be diagnosed are connected in series within the device to be diagnosed, and cables are connected between ports outside the device to be diagnosed. The data controller writes data from the data control unit to the first input terminal of all the ports connected in series, and repeats writing and reading so as to read at the next port, and diagnoses from the terminal device of the main unit. .

[0004]

In the conventional diagnostic method described above, in order to diagnose all ports of a device to be diagnosed from one main unit having a diagnostic processor, reconnection of cables for all ports is performed. However, there is a disadvantage that the diagnosis time is long.

[0005] Further, in the case where the main system devices are installed by the number of ports and connected to each port for diagnosis, there is a disadvantage that the installation area increases and the diagnosis cost also increases.

Further, the technique described in Japanese Patent Application Laid-Open No. 01-183751 has a drawback in that the diagnosis is performed with a connection different from the case where the apparatus to be diagnosed actually operates, so that a part of hardware that cannot be diagnosed remains.

[0007]

A first diagnostic apparatus according to the present invention comprises the steps of: (a) setting each of the diagnostic ports set by a corresponding one of processor port diagnostic start signals from a plurality of diagnostic processors; A plurality of receiving registers that are reset by each of the processor port diagnosis end signals from the processor and output a port diagnosis execution signal, respectively, and (b) input the port diagnosis execution signal and indicate a port number to be diagnosed first. An encoder that outputs a first initial port signal; (c) an initial value register that inputs the first initial port signal and outputs a second initial port signal; and (d) all of the processor port diagnostic end signal. A first OR circuit that generates a logical sum of the first and second port signals and outputs the result as a port diagnosis end logical sum signal; And (f) fetching the counter input signal by the port diagnosis end OR signal and outputting it as a diagnosis execution port signal. A counter; (g) an adder for inputting the diagnosis execution port signal and adding 1 to the signal to output the added signal as the addition signal; and (h) decoding the diagnosis execution port signal to generate a port corresponding diagnosis execution signal. A decoder for outputting, and (i) a second OR circuit for generating a logical sum of all the processor port diagnosis execution signals from the diagnostic processor and outputting a port diagnosis execution OR signal, and (j) the port. A logical product of each of the corresponding diagnostic execution signals and the logical sum signal during the port diagnostic execution is generated, and the port corresponding diagnostic signal is transmitted to the device to be diagnosed. A first AND circuit which forces, the register for outputting a comparison circuit valid signal is set by the (k) said port diagnosis end logical sum signal,
(L) when the comparison circuit valid signal is set, a comparison circuit that compares the second initial port signal with the diagnosis execution port signal and outputs a result as an all port diagnosis end signal to the device to be diagnosed; (M) a diagnostic data selection circuit for selecting any one of the processor diagnostic data from each diagnostic processor based on the first initial port signal and outputting the selected diagnostic data to the device to be diagnosed as diagnostic data.

A second diagnostic apparatus according to the present invention, in addition to the first diagnostic apparatus, includes an inverter circuit for generating an inverted signal of the all port diagnostic end signal, an output of the inverter circuit, and each of the port diagnostics. A second logical product circuit that generates a logical product of the active signal and the diagnostic non-completion signal to each diagnostic processor.

[0009]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

Referring to FIG. 1, a receiving register 1A,
1B, 1C and 1D are connected to a main unit having a diagnostic processor. The encoder 2 encodes the output of the receiving register, and the initial value register 3 holds the output of the encoder. The first OR circuit 4 includes a main unit 20
0, the output of which controls the selector 5 (selection circuit) and the counter 6. The selector 5 selects one of the outputs of the encoder 2 and the adding circuit 7, the counter 6 holds the output of the selector 5, and the adder 7 adds “1” to the output of the counter 6. The second OR circuit 9 forms a logical sum of the signals from the main unit, and its output is ANDed with each output of the decoder 8 by the first AND circuits 10A, 10B, 10C and 10D, and diagnosed. It is output to the target device 300. The register 11 is set by the output of the first OR circuit 4, and the output becomes an enable signal of the comparison circuit 12. The comparison circuit 12 compares the output of the initial value register 3 with the output of the counter 6 and compares the result with the main unit 200 and
Output to the inverter circuit 13 . Inverter circuit 13
Is obtained by inverting the output of the comparison circuit 12 and its output and the outputs of the receiving registers 1A, 1B, 1C and 1D are ANDed by the second AND circuits 14A, 14B, 14C and 14D, Is output. This system device 20
The processor diagnosis data from 0 is selected by the selector 15 and output to the diagnosis target device 300.

FIG. 2 is a system configuration diagram showing connections between the diagnostic apparatus 100 of the present invention, the main system 200, and the apparatus 300 to be diagnosed shown in FIG.

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3.

For the sake of convenience, a case where the main system is connected to the receiving register 1A of the diagnostic device will be described.

Main device 200 having diagnostic processor
Outputs processor port diagnosis start signal 20A, reception register 1A is set to "1". 1A
Is output to the encoder 2.

The encoder 2 has a port diagnosis execution signal 24
The port number of the diagnosis target device 300 for starting diagnosis from the values of A, 24B, 24C, and 24D is encoded.
In this case, only 24A is “1”, and “0” is output from the encoder 2 as the first initial port signal 25. This first initial port signal is received by the initial value register 3 and held.

In the selector 5, the first initial port signal 25 from the encoder 2 is selected and a counter input signal 26 is output. The counter input signal 26 is set in the counter 6 at the same time when the initial value register 3 is set, and a diagnosis execution port signal 27 is output.

The diagnostic execution port signal 27 is input to the decoder 8 and is decoded. Port corresponding diagnosis executing signals 28A, 28B, 28C and 2 which are outputs of the decoder 8
8D corresponds to each port of the diagnosis target device 300,
Decoding is performed so that only the port number corresponding to the port number to be diagnosed becomes “1”.

Next, the main unit 200 outputs a processor diagnosis execution signal 20C after an appropriate time after outputting the processor port diagnosis start signal 20A. This signal is output during execution of port diagnosis. In the second AND circuit 9, the processor diagnosis in-progress signals 20C, 21C, 22C and 23C from all the main system devices are output.
Is ORed. In this case, the value of 20C is output as it is as the logical sum signal 29 during the execution of the port diagnosis.

The logical product of each of the port corresponding diagnosis execution signals 28A, 28B, 28C and 28D from the decoder 8 and the port diagnosis execution OR signal 29 is determined by the first AND circuits 10A, 10B, 10C and 10D. The port corresponding diagnostic signals 32A, 32B, 32C and 32D are output. 32A to 32D correspond to ports to be diagnosed, and the diagnosis target device 300 receives this signal at each corresponding port and performs diagnosis. in this case,
Only 10A becomes '1' and port 0 is diagnosed. As the diagnostic data, the processor diagnostic data 20 </ b> D from the main unit 200 is selected by the diagnostic data selection circuit 15 by the first initial port signal 25, and is output to the diagnostic target device 300 as the diagnostic data 35. The diagnosis target device 300 performs a diagnosis of the port and the inside based on the diagnosis data 35.

Next, when the diagnosis of the port 0 is completed, the main unit 200 turns off the processor diagnosis execution signal 20C. As a result, the port corresponding diagnosis signal 32A is turned off. The device to be diagnosed recognizes this and ends the diagnosis of the port.

After a suitable time, the main system 200
Outputs a processor port diagnosis end signal 20B. The reception register 1A is reset by this 20B, and the port diagnosis execution signal 24A becomes "0". Also, processor diagnosis end signals 20B, 21B from the main unit,
The OR of 22B and 23B is taken by the first OR circuit 4 and output as the port diagnosis end OR signal 30.

At the same time as the diagnosis acceptance register 1A is reset, the selector 5 selects the addition signal 31 of the output of the adder 7, that is, the value obtained by adding "1" to the counter, by the port diagnosis end OR signal 30. It is set in the counter 6.

At the same time, a register 11 is also set,
The comparison circuit valid signal 34 output from the register 11 becomes “1”, and the comparison circuit 12 becomes valid. At this point, the output second initial port signal 33 of the initial value register 3 is “0”, and the diagnostic execution port signal 27 of the output of the counter 6 is “1”. Therefore, the all-port diagnosis end signal output from the comparison circuit 12 is “0”, indicating that there is a port whose diagnosis has not been completed.

Next, all the ports which are the outputs of the comparison circuit 12
All diagnosis has not been completed yet by the diagnosis end signal 37.
Main device 200 that recognizes that a port exists
Is a trigger that triggers port 1 diagnostics.
The support support diagnosis start signal 20A is output again . Thereby, the diagnosis of the port 1 is started as in the case of the port 0. In this case, since the value of the counter 6 is "1", the port corresponding diagnostic signal 32B is output. When the diagnosis is completed, the main unit 200 outputs a processor port diagnosis end signal 20B, and the counter 6 is counted up to “2”.

In the same manner, diagnosis of port 2 and port 3 is executed. The counter 6 returns to '0' in response to the processor port diagnosis end signal 20B indicating the end of the port 3 diagnosis.
Here, the comparison circuit 12 detects a match, and outputs an all port diagnosis end signal 30 to the diagnosis target device 300. Thereby, the diagnosis target device 300 recognizes the end of the diagnosis of all the ports.

Also, the inverter output signal 36, which is the output of the inverter circuit 13, becomes "0", and the second logical product circuit 14A performs a logical product with the port diagnostic execution signal 24A, and the port diagnostic non-executable signal 20E is obtained. It becomes '0'. This signal is received by main unit 200, and recognizes that main unit 200 has completed diagnosis of all ports.

The case where the main unit is connected to the reception register 1A has been described above.
Similarly, all ports can be diagnosed when connected to B, 1C, and 1D. 1B, 1C, and 1D, the port diagnosis in-progress signals output from the encoder 2 are "1", "2", and "3", respectively, and the ports for starting diagnosis are port 1 and port 1, respectively. 2, port 3
Becomes

[0030]

As described above, the diagnostic apparatus according to the present invention is configured such that the port to be diagnosed is automatically changed by the processor diagnostic start signal and the processor diagnostic end signal from the main system, so that one diagnostic apparatus is provided. Since all ports of the device to be diagnosed can be diagnosed by the main system device without changing the cable, there is an effect that the diagnosis time can be shortened.

Further, since the diagnosis can be performed with one main unit, the installation area can be reduced and the cost of the main unit can be reduced.

Further, since the same connection as in the actual operation state is performed, there is an effect that all the hardware of the device to be diagnosed can be diagnosed without omission.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is a system configuration diagram of an embodiment of the present invention.

FIG. 3 is a timing chart showing the operation of one embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional technique.

[Explanation of symbols]

1A, 1B, 1C, 1D Receiving register 2 Encoder 3 Initial value register 4, 9 OR circuit 5, 15 Selector 6 Counter 7 Adder 8 Decoder 10A, 10B, 10C, 10D AND circuit 11 Register 12 Comparison circuit 13 Inverter circuit 14A, 14B, 14C, 14D AND circuit 20A, 21A, 22A, 23A Processor port diagnosis start signal 20B, 21B, 22B, 23B Processor port diagnosis end signal 20C, 21C, 22C, 23C Processor port diagnosis execution signal 20D, 21D , 22D, 23D Processor diagnosis data signal 20E, 21E, 22E, 23E Port diagnosis non-execution signal 24A, 24B, 24C, 24D Port diagnosis execution signal 25, 27 Initial port signal 26 Counter input signal 28A, 28B, 2 C, 28D port corresponding diagnosis execution signal 29 port diagnosis execution logical sum signal 30 port diagnosis end logical sum signal 31 addition signal 32A, 32B, 32C, 32D port corresponding diagnosis signal 33 second initial port signal 34 comparison circuit enable signal 35 diagnostic data 36 inverter output signal 100 diagnostic device 200, 201, 202, 203 main system device 300 device to be diagnosed

Claims (2)

(57) [Claims] (A) A port diagnostic which is set by each of the processor port diagnostic start signals from a plurality of diagnostic processors and is reset by each of the processor port diagnostic end signals from each of the diagnostic processors. (B) a plurality of receiving registers for respectively outputting the execution signal, (b) an encoder for receiving the port diagnosis execution signal and outputting a first initial port signal indicating a port number to be diagnosed first; An initial value register for receiving the first initial port signal and outputting a second initial port signal; and (d) generating a logical sum of all of the processor port diagnostic end signals and outputting the result as a port diagnostic end logical OR signal. A first logical sum circuit, and (e) a port diagnostic end logical sum signal for selecting one of the second initial port signal and the addition signal. A counter selecting circuit for selecting and outputting the counter execution signal as a counter input signal; (f) a counter for taking in the counter input signal by the port diagnosis end OR signal and outputting it as a diagnosis execution port signal; (H) a decoder that decodes the diagnostic execution port signal and outputs it as a port-corresponding diagnostic in-progress signal, Of the processor port diagnosis execution signal and outputs the port diagnosis execution OR signal.
And (j) generating a logical product of each of the port-corresponding diagnosis execution signals and the port-diagnosis execution OR signal, and outputting the port-corresponding diagnostic signal to the device to be diagnosed.
(K) a register that is set by the port diagnosis end logical sum signal and outputs a comparison circuit valid signal; and (l) the second initial port signal when the comparison circuit valid signal is set. A comparison circuit that compares the diagnosis execution port signal with the diagnosis execution port signal and outputs the result to the device to be diagnosed as an all port diagnosis end signal; and (m) any one of the processor diagnosis data from each of the diagnosis processors.
And a diagnostic data selection circuit for selecting the diagnostic data according to the initial port signal and outputting the diagnostic data to the diagnostic device as diagnostic data. 2. An inverter circuit for generating an inverted signal of the all port diagnosis end signal, and a logical product of an output of the inverter circuit and each of the port diagnosis execution signals to generate a diagnosis non-completion signal for each diagnosis processor The diagnostic device according to claim 1, further comprising a second AND circuit that outputs the result to the second AND circuit.