JP2715872B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to an improvement in a test circuit in a microprogram type information processing apparatus.

[0002]

2. Description of the Related Art An example of a test circuit of this type of information processing apparatus is disclosed in Japanese Patent Application Laid-Open No. 62-278645. Referring to FIG. 5 which shows a block diagram of a main part of the information processing apparatus described in the publication, the information processing apparatus includes an instruction ROM 11, an instruction register 12, a microprogram R
OM (hereinafter, referred to as micro-ROM) address register 13, micro-ROM unit 14 including a decoder and micro-ROM, latch circuit 15, control signal generation circuit 1
7. Micro ROM address selection circuit, latch circuit 20
And an external input terminal group (hereinafter referred to as an external terminal) 21. The output of the instruction ROM 11 is set in the instruction register 12, and the output of the instruction register 12 is stored in the micro ROM address register 13 in response to the clock inversion φ. It is supplied to the micro ROM address selection circuit 19.

On the other hand, after a test address signal supplied from an external terminal 21 is also latched by a latch circuit 20,
It is supplied to the micro ROM address selection circuit 19. When the outputs of the micro ROM address register 13 and the latch circuit 20 are high (H) level in response to a test signal TEST1 supplied from a test terminal among the external terminals 21, the output of the latch circuit 20 is low. At the time of the (L) level, the address values set in the micro ROM address register 12 are respectively selected and supplied to the micro ROM unit 14.

[0004] Of the output of the micro ROM section 14, a signal of several bits is stored in the micro ROM address register 13 as the value of the next address, and the remaining bits are supplied to a control signal generating circuit 17 to generate a control signal. It has a configuration.

The operation will be described with reference to FIG. 5 again. When a normal instruction is executed, the TEST1 signal is fixed at L level. The instruction code read from the instruction ROM 11 is set in the instruction register 12,
Since one signal is at L level, the contents of the instruction register 12 are transferred to the micro ROM address register 13.

The micro-ROM address selection circuit 19 selects an address value set in the micro-ROM address register 13 and starts executing a series of micro-steps specific to the instruction.

[0007] The contents of the head address are read from the micro ROM 14 and latched by the latch circuit 15. The control signal generation circuit 17 outputs a control signal 18 based on the information latched by the latch circuit 15.

On the other hand, the next micro ROM address is determined by the output signal 16 of several bits of the latch circuit 15, and the micro step is subsequently executed.

In the test mode, the TEST1 signal is set to H level. Since the TEST1 signal is at the H level, the micro ROM address selection circuit 19
1. The test address value supplied from 1 and latched by the latch circuit 20 is selected, the operation is performed irrespective of the instruction-specific execution flow of the instruction execution, and the micro steps specified by the input address are sequentially executed. Is done.

[0010]

In recent years, microcomputers have included complicated instructions, and microsteps have become more complicated. As a result, the number of bits of the address of the microinstruction has increased. For example, if there is a 2K-step microinstruction, the address of the microinstruction becomes 11 bits. In addition, despite the complicated functional blocks incorporating a timer, a serial interface, and the like, it has become necessary to reduce the size of the package in order to meet the demand for downsizing the device.

However, the conventional information processing apparatus requires a terminal for inputting the address of the microinstruction, and has a disadvantage that the number of terminals is increased.

An object of the present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to enable a test to be executed without increasing the number of external terminals dedicated to a test of an information processing apparatus.

[0013]

An information processing apparatus according to the present invention has a start address of a predetermined microstep during a normal operation.
Address is read from the instruction ROM and the micro ROM address is read.
Supplied to the microprogram ROM via the
And the following steps
Microprocessor specified based on the output of the program ROM
Predetermined microsteps are sequentially performed by the program ROM address
Is executed, and when testing ,
Micro program ROM address to specify everything
Input from external terminals sequentially, and
Address selected by the micro ROM address selection circuit
In information processing apparatus microstep is Ru are successively performed are the micro step at the time the test, the Ma
Only the start address of the microprogram ROM address is
Input from the external terminal, during normal operation and test operation
At each of the start addresses or at the following steps
Use switching means to select one of the descending addresses
In the following steps, the microprogram R
Micro-program ROM address based on output from OM
Is specified . Further, the switching means, said microprogram ROM address switch circuit and a microprogram ROM register between the microprogram ROM address selection circuit and said microprogram ROM portion is inserted, in response to instruction start signal, the micro program ROM address switching circuit Ru is configured to supply to the micro ROM register selects one of the outputs of the micro plug ram ROM address selection circuit and the microprogram ROM unit. Further, after being latched by the start address Gala latch circuit supplied from the external terminal during the test, the external terminals Ru used for either input or output terminal of the predetermined signal.

Further, the means includes the microprogram ROM address selection circuit and the microprogram R.
The microprogram ROM address switching circuit and the microprogram ROM register are inserted between the microprogram ROM address switching circuit and the OM unit. It is characterized in that at least one of the outputs of the microprogram ROM address selection circuit is selected and supplied to the microROM register.

Still further, after the execution start address given from the external terminal is latched by the second latch circuit, the external terminal is used as either an input terminal or an output terminal of a predetermined signal. Features.

[0016]

Next, an embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1, which is a block diagram of a first embodiment of the present invention, the difference from the conventional example is that the micro RO
An M address switching circuit 22 and a switching circuit 23 are newly added, and one of the output of the control signal generation circuit 17 and at least one of the output signals of the internal circuit 24 are selected by the switching circuit 23 and output to the external terminal 21. It was done.

That is, the micro-ROM address selecting circuit 19 and the micro-ROM section 14
An address switching circuit 22 and a micro ROM address register are inserted, and in response to an instruction start signal MSTART supplied from an execution unit (not shown) at the instruction start timing, the micro ROM address switching circuit 22 outputs the output of the latch circuit 15 and the micro ROM. By selecting at least one of the outputs of the ROM address selection circuit 19, the micro RO
It is supplied to the M register 13. At least one of a predetermined control signal 18 provided by the control signal generation circuit 17 and a predetermined signal output from the internal circuit 24 is responsive to a second test signal TEST2 supplied from the outside so that the result can be monitored. It is configured to be selected by the switching circuit 23 and output to the external terminal 21.

The rest of the configuration is the same as that of the conventional example, and the same components are denoted by the same reference numerals and description of the configuration will be omitted.

The operation will be described with reference to FIG. 2 showing a timing chart for explaining the operation at the time of normal operation in addition to FIG. 1 and FIG. 3 showing a timing chart for explaining the operation at the time of test. The TEST1 signal is fixed at the L level.

[0020] Since the instruction code read from the instruction ROM11 there is a is but TEST1 signal supplied to the instruction register 12 is L level, the contents a1 of the instruction register 12 Ma
It is supplied to the micro ROM address switching circuit 22. At the instruction start timing, the instruction start signal MSTART becomes H level, and the contents a1 of the instruction register 12 are stored in the micro ROM.
The data is transferred to the address register 13 and the execution of a series of micro steps unique to the instruction is started.

The contents a1 of the head address are read from the micro ROM section 14 and latched by the latch circuit 15. The control signal generation circuit 17 outputs a control signal 18 based on the information (a1) latched by the latch circuit 15.

After the start of the execution of the microstep, the instruction start signal MSTART becomes L level, and the latch circuit 15
The output 16 for several bits determines the next micro-ROM address a2, and the micro-steps are subsequently executed.

At the time of a test, the TEST1 signal is set to the H level. Referring to FIG. 3, in response to the H level of the TEST1 signal , the micro ROM address selection circuit 19 selects the address value A1 input from the external terminal 21 and latched by the latch circuit 20.

At the instruction start timing, the instruction start signal MST
ART goes high, the contents of the latch circuit 20 are transferred to the micro ROM address register 13, and the execution of the micro step with the micro address A1 supplied from the external terminal 21 as the head address is started.

The start address A from the micro ROM 14
1 (A1) is read out and latched by the latch circuit 15. The control signal generation circuit 17 outputs a control signal 18 based on the information (A1), (A2),... Latched by the latch circuit 15.

After the start of the execution of the microstep, the instruction start signal MSTART becomes L level, and the latch circuit 15
The output 16 for several bits determines the next micro ROM address A2, and the execution of the micro step is subsequently performed.

After the instruction start timing, the control signal 18
Is output from the external terminal 21, and the control signal 18 or the output signal of the internal circuit 24 can be monitored from outside the information processing apparatus.

Referring to FIG. 4 which shows a block diagram of the second embodiment of the present invention, the control signal 18 is not output to the external terminal 21 and only signals from other blocks are connected.

Therefore, in the test mode, the external terminal 21 is used for inputting a test signal of another block or as a terminal for monitoring an output signal except for the start timing of an instruction in the test mode. In the case of this example, since the switching circuit 23 is not required, the input terminal of the control signal (TEST2) and the wiring thereof are also unnecessary.

[0030]

As described above, in the conventional information processing apparatus, at the time of a test, only the execution start address of a predetermined microprogram processing is inputted from an external terminal, and the next microprogram processing following this execution start address is performed by the microcontroller. There is provided a means for selecting and executing the next micro step based on the data read from the ROM section. Therefore, conventionally, during testing, the external terminal is
Although it could be used only for the address input of M, the use of the circuit of the present invention makes it possible to use the external terminals for inputting the micro-ROM address and monitoring the control signals. The number can be reduced.

When used as an input / output terminal for a test signal of another functional block, two blocks can be tested at the same time, and the test time can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation during a normal operation in the first embodiment.

FIG. 3 is a timing chart for explaining an operation during a test in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating an example of a conventional information processing apparatus.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Instruction ROM 12 Instruction register 13 Micro ROM address register 14 Micro ROM part 15, 20 Latch circuit 16 Number of bits of output of micro ROM part 17 Control signal generation circuit 18 Control signal 19 Micro ROM address selection circuit 21 External terminal 22 Micro ROM Address switching circuit 23 Test signal (TEST1) 24 Switching circuit 25 Internal circuit

Claims (3)

(57) [Claims] 1. A predetermined microstep during normal operation.
Start address is read from the instruction ROM and
Microprogram R via ROM address selection circuit
OM unit, and from the next step onwards
The macro specified based on the output of the micro program ROM
Lee Black program ROM address in Jo Tokoro micro-stearyl
Steps are performed sequentially, and a test micro
Micro program R for specifying all steps
OM addresses are sequentially input from external terminals and
These addresses are used to select the micro ROM address.
Is Ru executed sequentially selected by the micro-steps択回path
In information processing apparatus, a micro step at the time of the test, the microprocessor
Only the start address of the program ROM address is
Input during normal operation and test operation
Of the start address or the address after the next step
Using switching means for selecting one of the
From the next step on, the output of the microprogram ROM
The microprogram ROM address is specified based on the
An information processing apparatus characterized by being performed. Wherein said switching means, the said microprogram ROM address selection circuit microprogram R
Microprogram ROM address switch circuit and a microprogram ROM register between the OM unit is inserted, in response to instruction start signal, the microprogram ROM address switch circuit said micro plug ram RO
M address selection circuit and microprogram RO
The information processing apparatus 請 Motomeko 1, wherein that will be configured to select one of the outputs of the M unit is supplied to the micro ROM register. 3. After being latched in the start address Gala latch circuit supplied from the external terminal during the test,
The external terminal is any information processing apparatus is that請 Motomeko 1 wherein using the input or output terminal of the predetermined signal.