JPH04355829A - Program switching system - Google Patents

Abstract

PURPOSE:To shorten the time for program development and to improve the reliability of each software by performing the operation between one of two program memories, and a CPU by a switching control part in accordance with a program select signal. CONSTITUTION:When a switching instruction is sent from a subscriber terminal 1 to a CPU 3 through a signal level converting part 2, the CPU 3 sends a program select signal SEL to a switching control part 4. When receiving this signal SEL, the switching control part 4 gives an operating signal to prescribed one of two program memories 5 and 6 to designate it. Data processing is performed between only the designated program memory and the CPU 3 through a data bus and an address bus. Thus, a desired program is automatically executed from the subscriber terminal. When a power-on reset signal accompanied with power-on is given to the switching control part 4, one preliminarily determined program memory can be operated.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a program switching system, and more particularly to a system for switching a CPU program in a subscriber system transmission device.

[0002] In subscriber-based transmission equipment, it is necessary to prepare a test program at the time of factory shipment and a program used during normal operation, and it is necessary to switch between these two programs by some means. be.

0003

[Prior Art] As shown in FIG.
0 is attached to execute a predetermined processing operation with the CPU 10, and when no abnormality is detected, the program memory 20 is removed and the memory 30 storing the program for normal operation is attached in its place and the subscriber terminal (
(not shown), etc.

0004

[Problem to be Solved by the Invention] However, if the program memories 20 and 30 are alternately replaced in this way,
Executing the process of the PU 10 is troublesome, and there are problems in that replacement causes problems due to poor contact.

Accordingly, it is an object of the present invention to realize a program switching method that can automatically switch between two program memories.

[0006]

[Means and operations for solving the problems] A basic configuration diagram of the system of the present invention is shown in FIG. 2 and 3 are CPUs connected to the signal level converter 2;
Reference numeral 4 designates a switching control section that receives a program selection signal SEL.A or SEL.B from the CPU 3, and 5 and 6 designate program memories in which connection of a data bus and an address bus with the CPU 3 is switched by the switching control section 4.

In such a configuration, first, a switching command is sent from the subscriber terminal 1 to the CPU 3 via the signal level converter 2.
When the program selection signal SEL.A or SEL.B is sent to the switching control section 4, the CPU 3 sends the program selection signal SEL.A or SEL.B.

[0008] Upon receiving this program selection signal, the switching control unit 4 specifies a predetermined one of the two program memories 5 and 6 by giving a signal to enable operation, so that only the specified program memory is connected to the CPU 3. Data processing is executed between the two via the data bus and address bus.

[0009] In this way, a desired program can be automatically executed from the subscriber terminal.

Furthermore, in the present invention, when a power-on reset signal accompanying power-on is applied to the switching control section 4, the switching control section 4 can enable one predetermined program memory.

[0011]

[Embodiment] Fig. 2 shows an embodiment of a CPU processing program used in the program switching method according to the present invention shown in Fig. 1. First, Fig. 2(a) schematically shows the main program. , and is canceled by a reset signal RST from the switching control section 4, which will be described later (step S1
), then ROM5 or 6 as program memory
The operation according to the program stored in is executed (step S2). This occurs at power-up or when the RO
This is to eliminate program errors by initializing the program before switching when switching from one program of M5 and M6 to the other.

Furthermore, in the interrupt routine shown in FIG. 2(b), when a switching command signal is received from the subscriber terminal 1 via the signal level converter 2 while the program processing is being executed by the ROM 5 or 6. This is to interrupt the processing routine of step S2 to switch between ROMs 5 and 6, and when a command signal is first received from terminal 1 (step S11), this command signal is used as a command to switch between ROMs 5 and 6. It is determined whether or not it is a signal (step S12), and when it is found that it is a switching command signal, next, for example, if it is ROM5 that is currently being processed, a ROM6 different from this ROM5 is selected. It is determined whether or not it is the specified switching command signal (step S13), and if it is found that another ROM is specified, the program selection signal SEL・B (in this example) is set in response to the switching command signal.
(see FIG. 4) is output (step S14).

FIG. 3 shows an embodiment of the switching control section 4 shown in FIG. 40, 41, an AND gate 42 which inputs the output signal of the OR gate 41 and a power-on reset signal accompanying power-on, and the OR gate 40 and
NAND gate 43 inputting each output signal of gate 42
A flip-flop (hereinafter simply referred to as FF )4
4 and D terminal are always fixed at H level (+5V) and NAN
An FF 45 which inputs the output signal of the D gate 43 to the clock terminal CK and gives the output signal from the Q terminal to the OR gates 40 and 41 in common, a pulse generator 46 which generates a pulse OSC of a constant period, and a pulse generator 46 from the FF 45. A hexadecimal counter 47 which inputs the Q output signal of 1 to the clear terminal CLR and generates an output divided by 16 in response to the pulse OSC as the above-mentioned reset signal RST of the CPU 3, and a carry output signal of the counter 47 and an inverter 49. and a NAND gate 48 which receives a power-on reset signal and applies it to the reset terminal R of the FF 45.

The operation of this embodiment of the switching control section 4 will be explained with reference to the time chart shown in FIG. still,
The symbols of each signal shown in FIG. 4 correspond to those shown in FIG. 3, respectively.

First, when the power is turned on as shown in FIG. 4, an L-level power-on reset signal is applied to the AND gate 42 of the switching control section 4 for a certain period of time after the power is turned on. The output signal of FF 42 also becomes L level for this fixed period, and the reset terminal R of the negative logic FF 44 becomes L level, so its inverted Q terminal, that is, the enable selection signal OE becomes H level, and ROM 5 is enabled as shown in the figure. state. In addition, in such an initial state, the program selection signals SEL・A and SEL・B
Both are at H level.

Thereafter, when a switching command signal to select the ROM 6 is given to the CPU 3 from the terminal 1, the process shown in FIG.
b) The program selection signal SEL is activated by the interrupt routine of
・B changes from H level to L level. The same is true for the program selection signal SEL.A, and the data state during that time is undefined as indicated by diagonal lines in the figure.

As a result, the FF 44 is set and its enable selection signal OE goes to L level, and the FF 44 is switched to select the ROM 6. For this enable selection signal OE, an inverter may be inserted in only one line to one ROM so that it becomes enabled when it receives an H level, or it may be set in accordance with the H/L level in each ROM. You may also enable it.

At this time, if the power-on reset signal rises to H level as shown in the figure, the NAN
The output signal a of the D gate 43 rises from the L level to the H level, but as a result the Q output b of the FF 45 rises, the output signal a of the NAND gate 43 falls again.

Furthermore, the Q output b of the FF 45 is output to the counter 47.
When the counter 47 becomes a clear signal, it starts counting from the time it is cleared, and when it counts 7 pulses OSC, it starts the reset pulse RST, and when it counts 15 pulses, it starts counting down (at the time when the frequency is divided by 16). This resets and initializes the CPU 3. Further, as shown in the figure, when the counter 47 counts 15 pulses OSC from the start of counting, the carry output becomes H level, the output c of the NAND gate 48 falls to L level, resets the FF 45, and outputs its Q output b. L
Since the counter FF 47 is cleared, the output c of the NAND gate 48 returns to the H level. In this way, based on the switching command signal, the RO
Switching of M5 and M6 and resetting of CPU3 will be performed.

[0020]

As described above, according to the program switching method according to the present invention, when a switching command signal is sent from a subscriber terminal to a CPU via a signal level conversion section, the CPU sends a program selection signal to a switching control section. Since the switching control unit is configured to enable one of the two program memories to operate with the CPU in response to the program selection signal, the factory test mode and the normal operation mode can be changed. Alternatively, the maintenance mode at the time of shipment and the mode during normal operation can be stored in separate memories and automatically switched from the subscriber terminal side, thereby shortening the program development time and improving the reliability of each software.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle configuration of a program switching method according to the present invention.

[Fig. 2] CP used in the program switching method according to the present invention
It is a processing flowchart figure of U.

FIG. 3 is a circuit diagram showing an embodiment of a switching control section used in the program switching method according to the present invention.

FIG. 4 is a time chart diagram for explaining the operation of a switching control section used in the present invention.

FIG. 5 is a block diagram showing a conventional example.

[Explanation of symbols]

1 Subscriber terminal 2 Signal level conversion section 3 CPU 4 Switching control section 5, 6 Program memory In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] [Claim 1] When a switching command signal is sent from a subscriber terminal (1) to a CPU (3) via a signal level conversion unit (2), the CPU (3) sends a program selection signal to a switching control unit (4). and the program selection signal causes the switching control unit (4) to select the two program memories (5, 6).
) is enabled to operate between the CPU (3) and the CPU (3). 2. The switching control unit (4) enables one predetermined program memory to operate with the CPU (3) by a power-on reset signal. program switching method.