JPH05334113A - Microcomputer - Google Patents

Abstract

PURPOSE:To provide a microcomputer capable of easily executing a detailed test and executing a test in a real time. CONSTITUTION:A test clock with (n) times the period of an operation clock of the microcomputer is inputted to a test clock generating circuit 120, the address information of a microsequencer 102 is outputted to the external through an address latch circuit 106 synchronously with a latch clock 108 to be an output from the circuit 120 and a testing microprogram is inputted to a data latch circuit 107 synchronously with a latch clock 109 based upon the outputted address information, so that internal logic which can not be verified by a normal test can be tested. In addition, a test microprogram can be executed in a real time without interrupting the operation of a microcomputer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer of a microprogram type which can be easily tested.

[0002]

2. Description of the Related Art In a conventional microcomputer, when an internal logic is tested, a test program is written in an external memory, the microcomputer is made to execute the test program, and a bus monitor and signal input / output terminals are observed. An indirect test method is adopted in which the behavior of logic is estimated and judged.

The instruction processing operation in the conventional microcomputer will be described with reference to FIG. FIG. 4 is a block diagram showing a main part of a conventional microcomputer 100. The microcomputer 100 has a CPU 10
1 and a port circuit 123 and a bus control circuit 124, which are connected by an internal bus 125.

The CPU 101 is a micro sequencer 10
2, an arithmetic processing unit 103, an instruction queue 104, and a program counter (hereinafter referred to as PC) 105,
It is connected by the internal bus 126.

The micro sequencer 102 includes an instruction decoder 110, a micro instruction register (hereinafter referred to as MIR) 111, and a micro program RO.
An M (hereinafter referred to as μROM) 112, a store latch MSTL (hereinafter referred to as MSTL) 113 that latches the output of the μROM, and a selector 115.

The instruction code stored at the address indicated by the PC 105 in the program memory is fetched into the instruction queue 104 and input to the instruction decoder 110. The instruction decoder 110 converts the input instruction code into a start address (hereinafter referred to as an entry) of an execution procedure (microprogram) for each instruction stored in the μROM 112. This entry is stored in the MIR 111 and specifies the start address of the microprogram in the μROM 112. Then, the contents of the microprogram stored in the start address are MS
It is stored in the TL 113.

The contents stored in the MSTL 113 include control signals for various parts of the microcomputer for executing processing, and address information of the microprogram to be executed next (hereinafter referred to as the next address). The arithmetic processing unit 103 performs processing based on the control signal output from the MSTL 113. During execution of one macro instruction, the selector 115 selects the next address which is the output signal of the MSTL 113, the next address output from the MSTL 113 is stored in the MIR 111, and the next microprogram process is performed. At the end of one macro instruction, the output of the next instruction decoder 110 is MIR by the selector 115.
The microprogram processing of the next instruction stored in 111 is started.

At the time of testing, a test signal 135 is externally applied.
Is input, the control operation of the microsequencer 102 is indirectly observed by monitoring the internal bus 125 from the port circuit 124. When performing a more detailed test, the operation clock is temporarily stopped and the internal bus 12
A test for special data is performed by directly writing test data from the outside to each unit connected to 5 via the port circuit 124.

[0009]

As described above, the conventional microcomputer does not have a test function at the level of the micro sequencer 102 that directly controls hardware, and the bus state and terminal state related to instruction execution are not provided. The test is indirectly executed by observing.

Therefore, there is a drawback that it is not easy to test a sequential circuit that changes depending on the combination of instructions and a logic that does not have a data path to the internal bus. In addition, it is necessary to combine a plurality of instructions to perform a test, which is redundant and inefficient. Further, when the test data is sent to the internal unit by a method such as stopping the clock, there is a drawback that the instruction execution operation for interrupting the operation cycle related to the normal instruction execution cannot be observed in real time.

It is an object of the present invention to provide a microcomputer capable of efficiently performing a test and monitoring the operation of instruction execution in real time by eliminating the above drawbacks.

[0012]

A feature of the present invention is that a central processing unit including at least a microprogram ROM and a microsequencer and a microcomputer in which a test input port circuit and an output port circuit are integrated on the same chip, N times the microcomputer (n
Is a natural number) from the outside, a first latch clock and a second latch clock for an internal test are generated, and the micro instruction register is synchronized with the first latch clock. First means for latching the output address data by an address latch circuit and outputting the output to the outside through the output port circuit, and the microcomputer executing the information based on the information output by the first means. The test microprogram to be input is input through the input port circuit, latched by the data latch circuit in synchronization with the second latch clock, and either the output thereof or the output of the microprogram ROM is selected. Second means for performing the test in real time by the microcomputer. It is to run a microprogram.

[0013]

1 is a block diagram of a microcomputer 100 as a first embodiment of the present invention.

First, the microcomputer 100 of the present invention.
The instruction processing operation in FIG. 1 will be described with reference to FIG. The microcomputer 100 includes a CPU 101,
Port circuits 121, 122, 124, bus control circuit 12
3 and are connected by a test clock generation circuit 120 and an internal bus 125.

The CPU 101 is a micro sequencer 10
2, the arithmetic processing unit 103, the instruction queue 104, and the CP
The U105, the address latch circuit 106, and the data latch circuit 107 are included, and the microsequencer 102, the arithmetic processing unit 103, the instruction queue 104, and the PC 105 are connected by an internal bus 125.

The micro sequencer 102 includes an instruction decoder 110, an MIR 111, a μROM 112, and a μR.
MSTL113 which latches the output of OM, and selector 1
It is composed of 14, 115.

An external test microprogram memory and an interface logic circuit are connected to the microaddress output terminal 133 and the microdata input terminal 134 (both not shown).

When executing the instruction execution process, the instruction code stored at the address indicated by the PC 105 in the program memory is fetched into the instruction queue 104, and the instruction decoder 1
It is input to the selector 115 via 10. The instruction decoder 110 converts the input instruction code into a microprogram entry for each instruction stored in the μROM 112. This entry is stored in the MIR 111 at the timing (operation clock f2) shown in FIG.
Specify the start address of the microprogram in (Fig. 2M
Output of IR111). Then, the contents of the microprogram stored at the start address (the output of the μROM 112) are stored in the MSTL 113 via the selector 114 by the latch clock of the MSTL 113 shown in FIG.

The contents stored in the MSTL 113 include control signals for each part of the microcomputer for executing processing and next address information. The arithmetic processing unit 103 performs processing based on the control signal output from the MSTL 113. During execution of one macro instruction, the selector 115 outputs the next address output from the MSTL 113 (see FIG. 2M).
(STL113 output) is selected, the next address output from the MSTL113 is stored in the MIR111, and the next microprogram process is performed. At the end of one macro instruction, the selector 115 selects the next instruction decoder 1
The output of 10 is stored in the MIR 111 to start the microprogram processing of the next instruction.

In the normal operation, the output of the selector 114 selects the input from the μROM 112 (the output of the μROM 112 in FIG. 2).

During the test, a test signal 135 is externally applied.
Is input, the control operation of the micro sequencer 102 is indirectly observed by monitoring the internal bus 125 from the port circuit 121. To perform a more detailed test, do the following.

The test signal 136 is input, and the test clock (test clock f1 in FIG. 1) is input to the test clock generation circuit 120 from the tect clock terminal 132.
Here, the frequency f1 of the test clock is input as f1 = f2 × 2 (m / n) with respect to the word length m of the micro program and the operation clock frequency f2 of the microcomputer 100 (operation clock f2 in FIG. 3). (Round up to the nearest whole number). Here, n represents the number of bits of the micro data output terminal 134.

For example, if the word length is 40 bits and the number of micro data output terminals 134 is 8, f1
= F2 × 2 × (40/8) = 10f1 and the frequency 10 times that of f2 is input.

Based on the test clock f1, the test clock generating circuit 120 is set to the first timing at the timing shown in FIG.
Latch clock (hereinafter simply referred to as the latch clock)
108 (FIG. 3, latch clock 108) and second latch clock (hereinafter simply referred to as latch clock) 109
(Latch clock 109 in FIG. 3) is output and transmitted to the address latch 106 and the data latch 107, respectively.

The address latch circuit 106 is the MIR 111.
Output of MIR111 (Figure 3 MIR111 output)
It is latched at the timing of 8 and is output to the outside from the address output terminal 133 via the output port circuit 121 (see FIG. 3).
Output of address latch 106).

Based on the address information output from the address terminal 133, a test microprogram is externally transmitted to the microdata input terminal 134 in a time division manner. The data latch 107 latches the test microprogram (input data of the data latch 107 of FIG. 3) input from the microdata input terminal 134 based on the latch clock 109 via the port circuit 122 and transmits it to the selector 114.

The MSTL 113 outputs the output of the selector 114 (see FIG. 3) as in the microprogram processing operation of a normal instruction.
(MSTL113 input) is latched by the MSTL113 latch clock shown in FIG. 3 and transmitted to each control circuit of the microcomputer 100 as the next address and control information (MSTL113 output in FIG. 3).

[0028]

In the interrupt processing system in the microcomputer of the present invention, a test signal is input and the test clock f1 is input from the test clock terminal (at this time, the relationship between the test clock f1 and the operation clock f2 is f1 = f).
2 × (word length of microprogram / number of bits of microdata output) is input to the test clock generation circuit.

Based on the test clock f1, the test clock generation circuit outputs a latch clock, and the address latch latches the output of MIR by the latch clock and outputs it from the address output terminal to the outside through the output port circuit.

Based on the output information, a test microprogram is input from the outside through the microdata input terminal and the input port circuit, latched by the data latch circuit, and the output is input to the selector. The output of the selector is configured to be sent to each control circuit of the microcomputer as the next address and control information by the MSTL.

That is, it is possible to execute an external test microprogram while directly operating a microsequencer for controlling hardware. For this reason, it is easy to set fine test data for a logic having no data path to the sequential circuit and the internal bus, and the test efficiency is good. Moreover, since the test data is sent to the internal unit without stopping the clock, the instruction execution can be observed in real time.

[Brief description of drawings]

FIG. 1 is a block diagram of a microcomputer according to a first embodiment of the present invention.

FIG. 2 is an operation timing chart of a micro sequencer included in a CPU.

FIG. 3 is an operation timing chart when the test microprogram of the microsequencer is executed.

FIG. 4 is a block diagram of a conventional microcomputer.

[Explanation of symbols]

100 Microcomputer 101 CPU 102 Microsequencer 103 Arithmetic Processing Unit 104 Instruction Queue 105 Program Counter 106 Address Latch 107 Data Latch Circuits 108, 109 Latch Clock 110 Instruction Decoder 111 MIR (Micro Instruction Register) 112 μROM (Micro Program ROM) 113 MSTL 114 , 115 selector 121, 122, 124 port circuit 123 bus control circuit 125 internal bus 129 test clock generation circuit 131 input / output port 132 test clock terminal 133 micro address output terminal 134 micro data input terminal 135, 136 test signal

Claims (1)

[Claims] 1. A microcomputer in which a central processing unit including at least a microprogram ROM and a microsequencer and a test input port circuit and a test port circuit are integrated on the same chip, n times as large as the microcomputer (n is a natural number). ) Is input from the outside to generate a first latch clock and a second latch clock for an internal test, and
Means for latching the address data output from the microinstruction register by the address latch circuit in synchronization with the latch clock, and outputting the output to the outside through the output port circuit; and the first means. The test microprogram executed by the microcomputer based on the information output by the above is input through the input port circuit, latched by the data latch circuit in synchronization with the second latch clock, and A second means for selecting any one of the output of the microprogram ROM, and the microcomputer executes the test microprogram in real time.