JP2002007156A - Microprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To instantaneously update the erroneous program area of a mask ROM without making it necessary to newly manufacture an LSI, or spending any excessive costs. SOLUTION: In a data register 13, the start address of the update area of a mask instruction ROM is set through DTI, TMS, and TCK being JTAG terminals in a debug event point register 14, and address break is set in a debug control register 15, and an update program is set in a debug instruction memory 16. When the execution of the instruction of a mask instruction ROM 31 under the control of a CPU core 30 reaches the front of start address of the update area, an update program is executed by a debug control part 20. When the update program is ended, the execution is started from the next program in the update area of the mask instruction ROM 31.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor for accessing a built-in debug function via a JTAG terminal and updating a program in a mask ROM.

[0002]

2. Description of the Related Art In a microprocessor such as a CPU or a DSP, a mask ROM product having a built-in mask ROM is used as a memory because cost can be reduced during mass production. In addition, recent microprocessors include ICE
Built-in debugging function instead of the international standard IEEE
E1149.1 boundary scan (commonly known as JTA
The use of G) to access debug functions is increasing.

[0003]

However, in the case of a mask ROM product according to the prior art, if an error (bug) is found in the program after manufacturing the LSI, the LSI is manufactured again in order to recreate the mask ROM portion. I have to fix it. For this reason, the manufacturing period and manufacturing cost of the LSI are unnecessarily increased, and the formal release time of the device is delayed, which also affects the device cost.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and there is no need to manufacture a new LSI, and it is possible to instantaneously update an erroneous program area of a mask ROM without extra cost. It is an object of the present invention to provide a microprocessor capable of performing the following.

[0005]

In order to solve the above-mentioned problems, according to the present invention, a mask instruction ROM storing a program, a CPU core for executing the program of the mask instruction ROM, A microprocessor having a debug function accessible using a JTAG terminal, a setting means for setting a start address of an update area of the mask instruction ROM and an update program in the debug function, and a mask by the CPU core. When the program execution of the instruction ROM reaches the start address of the update area set in the debug function unit, the update program set in the debug function unit is executed, and when the update program ends,
Debug control means for executing the next program in the update area of the mask instruction ROM.

Further, according to the invention described in claim 2, according to claim 1,
In the above described microprocessor, the start address and the update program are supplied from the JTAG terminal.

[0007] According to the third aspect of the present invention, the first aspect of the present invention.
The microprocessor according to any one of claims 1 to 3, further comprising an instruction RAM in which instructions can be externally set by self boot or host boot, and when the debug function unit does not have a sufficient capacity to store the update program, the Part in the instruction RAM,
The address is set so that the update program is executed continuously.

In order to solve the above-mentioned problems, according to the invention of claim 4, the first processor which mainly performs digital signal processing, the second processor which mainly performs control processing, and the first processor In a microprocessor including a mask instruction ROM storing a program to be executed by a processor and a debug function unit accessible using a JTAG terminal, an update area of the mask instruction ROM is controlled according to control of the second processor. Update control means for generating a start address and an update program; and the mask instruction RO generated by the update control means.
Setting means for setting a start address of an M update area and an update program in the debug function unit;
When the program execution of the mask instruction ROM by the U core reaches the start address of the update area set in the debug function unit, the update program set in the debug function unit is executed, and the update program ends. Then, there is provided a debug control means for executing from the program next to the update area of the mask instruction ROM.

Further, according to the invention described in claim 5, according to claim 4,
Any one of a start address and an update program of the update area of the mask instruction ROM from the JTAG terminal, and a start address and an update program of the update area of the mask instruction ROM from the update control means. The setting means sets the start address and the update program of the update area of the mask instruction ROM selected by the selection means in the debug function unit.

In the present invention, the start address of the update area of the mask instruction ROM 31 (the part incorrect as a program) and the update program are set in the debug function unit through the JTAG terminal, and the debug control means controls the CPU core. When the program execution of the mask instruction ROM reaches up to the start address of the update area set in the debug function unit, the update program set in the debug function unit is executed. The program is executed from the next program in the update area of the mask instruction ROM. Therefore, it is not necessary to manufacture a new LSI, and it is possible to update an incorrect program area of the mask ROM instantaneously without extra cost.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. A. Configuration of Embodiment FIG. 1 is a block diagram showing an overall configuration according to an embodiment of the present invention. In the figure, the TAP controller 10
Are the mode signals S2 and TC to TMS which is the JTAG terminal.
When the clock signal S3 is supplied to K, the control signal S18 is transmitted to the instruction register 11 and the control signal S17 is transmitted to the data register 13. When the control signal S18 is supplied to the instruction register 11, the JTAG terminal T
An instruction based on the data signal S1 supplied to DI is set. The instruction decoder 12 decodes the instructions set in the instruction register 11.
The data register 13 selects a desired register according to the decoded instruction. In a register selected from among the data registers 13, data based on the data signal S1 supplied to the TDI is set by a control signal S17. CPU core 30, debug control unit 2
0, a mask instruction ROM 31, and an instruction RAM 32 are connected by an address / data bus 33. While the CPU core 30 is executing the mask instruction ROM 31, the debug control unit 20 sets the break condition set in the data register 13;
Execute the program.

B. Next, the operation of the above-described embodiment will be described. Here, FIG. 2 is a flowchart for explaining the operation of the present embodiment. FIG. 3 is a timing chart.
The microprocessor has a built-in debug function using JTAG, which is a TD which is a JTAG terminal.
I, TMS, TCK, TAP controller 10, instruction register 11, instruction decoder 12, data register 1
3. It is realized by using the debug control unit 20. JTAG is a common name of the boundary scan defined in the international standard IEEE1149.1, and the debug function uses a private instruction provided in IEEE1149.1 so that a device designer can independently determine it. The instruction setting of the instruction register 11, the selection of the data register 13, and the data setting are performed by the IEEE1.
T with the procedures and interfaces defined in 149.1
This is done through DI, TMS, and TCK.

A program error is found in the mask instruction ROM 31, and the memory area is changed from the XX address to the Y address.
Up to the Y address. First, a start address XX of a memory area to be updated is set in the debug point event register 14 (S1). The procedure is as shown in FIG.
By supplying the mode signal S2 to the TMS and the clock signal S3 to the TCK, an instruction (for example, 20h) for selecting the debug event point register is set in the instruction register 11 by the control signal S18 from the TAP controller 10. Are decoded by the instruction decoder 12, and the debug event point register 14 is selected from the data register 13.
Then, in the debug point register 14, the start address XX of the memory area to be updated is set as a break address value by the control signal S17.

Similarly, an instruction address break which is a cause of a break is set in the debug control register 15 (S2), and an update program is set in the debug instruction memory 16 (S2).
3). Here, the capacity of the update program is an area from the XX address to the YY address, but there is a case where a sufficient memory area is not secured in the debug instruction memory 16 which is originally used for debugging. If the area of the debug instruction memory 16 is sufficient, the last instruction of the debug instruction memory 16 includes a JUMP to the address next to YY.
Set an instruction. If the area of the debug instruction memory 16 is not enough, a JUMP instruction to the address ZZ of the instruction RAM 32 is set in the last instruction of the bag instruction memory 16. The instruction RAM 32 has a smaller capacity than the mask instruction ROM 31, but instructions can be externally set by self boot or host boot. Here, the update program is booted in advance in the area from the address ZZ. A JUMP instruction to the address next to the address YY is set in the last instruction of the update program to be booted in the instruction RAM 32.

When the setting through JTAG is completed, C
The PU core 30 executes the program of the mask instruction ROM 31 through the address / data bus 30 (S
4). When the program is executed up to just before the address XX, an instruction address break occurs by the debug control unit 20 (S5), and the update program set in the debug instruction memory 16 is executed (S6). When the update program is stored in the area of the debug instruction memory 16, after the last instruction of the debug instruction memory 16 is executed, the address Y of the mask instruction ROM 31 is changed.
The program is executed from the address following Y (S7,
S8). On the other hand, if the update program does not fit in the area of the debug instruction memory 16, the update program
6, the program is executed from the address following the address YY of the mask instruction ROM 31 (S7, S7).
8).

C. Another Embodiment Next, another embodiment of the present invention will be described. FIG.
FIG. 9 is a block diagram showing a configuration according to another embodiment of the present invention. Note that the same reference numerals are given to portions corresponding to FIG. In this other embodiment, a DSP core 34 that mainly performs digital signal processing and a main CPU 50 that mainly performs control processing as a master processor are mounted, that is, a plurality of processor cores are mounted on one chip. Is assumed. In the above-described embodiment, the update program is provided by JTA from outside.
Although the setting is performed through the G terminal, in the present embodiment, the setting is performed by the main CPU 50 controlling the program update controller 54.

In the instruction break address register 51, a start address of a memory area of the mask instruction ROM 31 which must be updated is set by the main CPU 50 via an address / data bus 55. Update program start address register 5
In 2, the start address of the update program booted in advance in the instruction RAM 32 by the main CPU 50 via the address / data bus 55 is set. The selector 40 has JTAG terminals TMS, TCK, TDI
Signals S2, S3, S1 inputted from outside through
One of signals S56 (corresponding to signal S2), S57 (corresponding to signal S3), and S58 (corresponding to signal S1) generated internally from the program update controller 54 is
The selection is made by a selection signal supplied from the external terminal MUX41. When a JTAG emulator is connected to TMS, TCK, or TDI and debugging is performed, TMS, TC
Signals S2 and S externally supplied via K and TDI
3. Select S1. On the other hand, when the DSP core 34 and the main CPU 50 are in actual operation and it is desired to update a program area having a mask instruction ROM, the signals S56, S57, S57 generated by the program update controller 54 are generated.
Select 58. The signal S selected by the selector 40
42 (signal S2 or signal S56) and signal S43 (signal S3 or signal S57)
The signal S44 (the signal S1 or the signal S58) is supplied to the instruction register 11 and the data register 13.

The selector 40 is a JTAG terminal TM
Signals S2, S supplied via S, TCK, TDI
3, S1 is output, and the operation of updating the incorrect program area of the mask instruction ROM 31 is the same as that of the above-described embodiment, and thus the description is omitted. Hereinafter, the program update controller 54 uses the signals S56, S57, and S58 corresponding to the JTAG signal to output the mask instruction RO.
The operation of updating the incorrect program area of M31 will be described.

The main CPU 50 sets the start address of the memory area of the mask instruction ROM 31 which needs to be updated in the instruction break address register 51 through the address / data bus 55.
Similarly, the update program start address register 52
In the instruction RAM 32, the start address of the pre-booted update program is set. When the main CPU 50 accesses the start command register 53 through the address / data bus 55, the program update controller 54 controls the signals S56, S57,
S58 is generated.

Next, signals S56, S57, S58 from the program update controller 54 are selected by the selector 40.
Is selected, and the signals S56 and S57 are changed to the signals S42 and S43.
Is supplied to the TAP controller 10 and the signal S5
8 is supplied to the instruction register 11 and the data register 13 as a signal S44. In the data register 13,
The start address of the memory area to be updated is set in the debug event point register 14, the instruction address break is set in the debug control register 15, and the start address of the update program previously booted in the instruction RAM 32 is set in the debug instruction memory 16. Is set. Hereinafter, the operation is similar to that of the above-described embodiment.

In the above-described other embodiment, a control hardware for updating a program is required to be provided on a board outside the chip in the above-described embodiment, but a plurality of processor cores are mounted. In such a chip, by controlling one as a master processor, there is no need to provide control hardware on an external board, and the contents of the mask ROM can be arbitrarily updated.

[0022]

As described above, according to the present invention,
By using JTAG to access a function block originally built as a debugging function, a microprocessor with a built-in mask ROM, which can reduce the cost during mass production, can be newly added to LSIs for program errors (bugs). It is possible to obtain the advantage that the program can be updated instantaneously without the need to manufacture the program and without any extra cost. Also, since the JTAG terminal and the hardware resources as the JTAG function are originally built in as the on-chip debug function of the microprocessor, sharing can be achieved, and there is no need to provide extra terminals and hardware, and the case where sharing is not possible. This has the advantage that the number of development steps can be reduced and the chip unit cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining the operation of the present embodiment.

FIG. 3 is a timing chart for explaining the operation of the present embodiment.

FIG. 4 is a block diagram illustrating a configuration according to another embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 TAP controller (setting means) 11 Instruction register (setting means) 12 Instruction decoder (setting means) 13 Data register (debug function unit) 14 Debug event point register 15 Debug control register 16 Debug instruction memory 20 Debug control unit (debug control means) ) 30 CPU core 31 Mask instruction ROM 32 Instruction RAM 33 Address / data bus 34 DSP core (first processor) 40 Selector (selection means) 50 Main CPU (second processor) 51 Instruction break address register 52 Update program start address Register 53 Start command register 54 Program update controller

Claims (5)

[Claims] 1. A mask instruction RO in which a program is stored.
M and a CP for executing the program of the mask instruction ROM
A microprocessor including a U-core and a debug function unit accessible using a JTAG terminal; a setting unit configured to set a start address of an update area of the mask instruction ROM and an update program in the debug function unit; When the program execution of the mask instruction ROM by the CPU core reaches the start address of the update area set in the debug function unit, the update program set in the debug function unit is executed, and the update program ends. Then, a debug control means for executing the program from the program next to the update area of the mask instruction ROM is provided. 2. The microprocessor according to claim 1, wherein the start address and the update program are supplied from the JTAG terminal. 3. An instruction RA whose instruction can be externally set by self boot or host boot.
M, when the debugging function unit does not have a sufficient capacity to store the update program, a part of the update program is stored in the instruction RAM, and the address is set so that the update program is continuously executed. 2. The microprocessor according to claim 1, wherein the setting is performed. 4. A first processor for mainly performing digital signal processing, a second processor for mainly performing control processing, a mask instruction ROM in which a program executed by the first processor is stored, and a JTAG. A microprocessor having a debug function unit accessible using a terminal; an update control unit configured to generate a start address of an update area of the mask instruction ROM and an update program under control of the second processor; The mask instruction R generated by the control means;
Setting means for setting the start address of the update area of the OM and the update program in the debug function unit; and executing the program of the mask instruction ROM by the CPU core by setting the start address of the update area in the debug function unit. And debug control means for executing the update program set in the debug function section when the program reaches the previous time, and executing the program from the next program in the update area of the mask instruction ROM when the update program ends. And a microprocessor. 5. A start address of an update area of said mask instruction ROM from said JTAG terminal and an update program, and said mask instruction RO from said update control means.
Selecting means for selecting one of a start address of an update area of M and an update program, wherein the setting means comprises: a start address of an update area of the mask instruction ROM selected by the selection means; 5. The microprocessor according to claim 4, wherein (a) and (b) are set in the debug function unit.