JP3951371B2 - Watchdog timer and microcomputer - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a watchdog timer for resetting or interrupting a CPU when the CPU runs away and a microcomputer having such a watchdog timer.
[0002]
[Prior art]
Conventionally, a watchdog timer disclosed in Japanese Patent Laid-Open No. 3-194628 has been proposed. This is configured to stop the watchdog timer by setting the signal level of a specially provided external terminal to a high level during emulation, and only gives a signal for switching to the external terminal. This will make debugging easier.
[0003]
[Problems to be solved by the invention]
However, in the above configuration, a signal for stopping the watchdog timer must be given to the external terminal of the watchdog timer, and the connection is extremely troublesome.
[0004]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a watchdog timer and such a watch that can easily perform a function test without troublesome connection during debugging of program development. The object is to provide a microcomputer equipped with a dog timer.
[0005]
[Means for Solving the Problems]
According to the first aspect of the present invention, when the CPU is operating normally, the CPU accesses the watch dog timer every predetermined period, so that the counting means repeatedly executes the counting operation. In this case, the count value of the watchdog timer never becomes the limit value.
[0006]
When the CPU runs away, the CPU does not access the watchdog timer, so the count value of the counting means becomes the limit value. As a result, the counting means outputs an abnormal signal to the CPU, so that the runaway state stops when the CPU is reset or interrupted.
[0007]
When the counting operation of the counting means is temporarily stopped to check the operation of the watchdog timer during emulation, the first data is written to the stop command generating means by executing the emulation program by the CPU.
[0008]
Then, since the stop command generating means outputs a stop command to the counting means, the counting means stops the counting operation. In this state, the operating state of the watchdog timer is checked.
[0009]
When restarting the counting operation of the counting means, the CPU writes the second data to the stop command generating means. Then, the stop command generating means stops outputting the stop command to the counting means. As a result, the counting means resumes the counting operation.
[0014]
In this case , when checking the output state of the stop command by the stop command output means , the CPU executing the emulation program accesses the control circuit .
Then, the control circuit gives a command to the output status output means, and the output status output means outputs the output status of the stop command by the stop command generating means accordingly, so that the CPU changes the output status of the stop command by the output. Can be confirmed.
[0015]
Also, when you want to check the count value of the count means, CPU running emulation program to access the control circuit.
Then, the control circuit gives a command to the count value output means, and the count value output means outputs the count value of the count means accordingly, so that the CPU can check the count value of the count means by the output. .
Therefore, since the watchdog timer can be stopped or restarted at any timing by executing the emulation program by the CPU, debugging of program development can be performed without connecting wiring to the watchdog timer.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic configuration of a one-chip microcomputer and an electrical configuration of a watchdog timer included in the one-chip microcomputer. In FIG. 1, a one-chip microcomputer 1 includes a watchdog timer 6 in addition to a CPU 2, a ROM 3 storing a program, a RAM 4 for storing working data, and a peripheral circuit 5.
[0017]
The CPU 2, the ROM 3, the RAM 4, the peripheral circuit 5, and the watchdog timer 6 are connected through a system bus such as an address bus 7 and a data bus 8, so that data can be exchanged between the CPU 1 and them through the system bus. It has become.
[0018]
The watchdog timer 6 is mainly composed of a count enable generating circuit 9 (corresponding to a stop command output means, hereinafter referred to as a CE generating circuit), a down counter 10 (corresponding to a counting means), and a control circuit 11.
[0019]
In the CE generation circuit 9, the data input terminal D of the latch circuit 12 is connected to DB0 of the data bus 8 (bit 0 of the data bus), and the bit of the data bus DB0 at the timing when the clock terminal C becomes high level. The pattern is stored in the latch circuit 12 and output from the output terminal Q.
[0020]
A system reset signal is input to the reset terminal R of the latch circuit 12 when the power is turned on, and the output level of the output terminal Q of the latch circuit 12 is low when the system is started.
[0021]
The output terminal of the AND circuit 13 is connected to the clock terminal C of the latch circuit 12. An address bus decoder 14 (hereinafter referred to as “A bus decoder”) and a data bus key pattern decoder 15 (hereinafter referred to as “D bus key pattern decoder”) are connected to the input terminals of the AND circuit 13. The write signal IWRE and the CPU driving clock signal CK1 are input.
[0022]
The A bus decoder 14 is for detecting that the bit pattern of the address bus 7 has become a predetermined pattern. For example, if the address preset in the CE generation circuit 9 is [041C] h, the address data is [041C]. A high level signal is output in the state of h.
The D bus key pattern decoder 15 is for detecting that the bit pattern of the data bus 8 has become a predetermined pattern.
[0023]
FIG. 2 shows a specific circuit of the D bus key pattern decoder 15. In FIG. 2, the output from the AND circuit 13 is set to a high level when the data buses DB5 (bit 5) to DB1 (bit 1) have a predetermined key pattern. That is, the data buses DB1, DB3, DB5 are directly connected to the input terminal of the AND circuit 16, and the data buses DB2, DB4 are connected to the input terminal of the AND circuit 16 via the inverter 17.
[0024]
Therefore, in such a connection relationship, the AND condition of the AND circuit 16 is satisfied and a high level signal is output only when the bit patterns of DB5 to DB1 are [10101] b, and the other bit patterns Then, the AND circuit 16 does not output a high level signal.
[0025]
With the above configuration, the CE generation circuit 9 is in a state where the bit pattern of the address bus 7 is [041C] h and the bit patterns of DB5 to DB0 of the data bus 8 are [101011] b (first access condition This corresponds to a first data write operation), and is referred to as a high-level count enable signal (hereinafter referred to as a CE signal) at the timing when the write signal IWRE is input from the CPU 2 and the clock signal CK1 is input.
[0026]
The CE generation circuit 9 is in a state where the bit pattern of the address bus 7 is [041C] h and the bit pattern of DB5 to DB0 of the data bus 8 is [101010] b (second access condition, second The output of the CE signal is stopped when the write signal IWRE is input from the CPU 2 and the clock signal CK1 is input.
[0027]
The CE signal from the CE generation circuit 9 is given to the buffer circuit 18. The output terminal of the buffer circuit 18 is connected to a predetermined data bus, and the CPU 2 can read the output level of the buffer circuit 18 through the data bus 8.
[0028]
In the down counter 10, the selector 19 inputs the data on the side determined by the control circuit 11 and latches it by the latch unit 20, thereby updating the value of the down counter 10. That is, the selector 19 selects and outputs the input data from the input terminal IN0 when the selection terminal S is at the low level, and selects the input data at the input terminal IN1 when the selection terminal S is at the high level. And output it. In this case, the input terminal IN1 of the selector 19 is connected to the data bus 8, and the initial count value from the CPU 2 is taken into the down counter 10 through the data bus 8 at the timing when the selection terminal S becomes high level. It has become.
[0029]
The latch unit 20 latches and stores the output data from the selector 19 at the input timing of the CPU driving clock CK1, and outputs the stored data. In this case, the latch unit 20 outputs a borrow signal (corresponding to an abnormal signal) to the CPU 2 when the stored data becomes zero.
[0030]
The decrement unit 21 receives the output data from the latch unit 20 and outputs a value obtained by subtracting 1 from the input data.
The latch unit 22 stores the output data from the decrement unit 21 at the timing when a high level is input to the C terminal, and outputs the stored data. The output terminal of the latch unit 22 is connected to the input terminal IN 0 of the selector 19.
[0031]
With the above configuration, the count value of the down counter 10 is set by the CPU 2 at a predetermined timing, and the count value is decremented by 1 every predetermined period.
[0032]
The buffer circuit 23 is a circuit for the CPU 2 to read the count value of the down counter 10, and outputs the count value from the down counter 10 to the CPU 2 through the data bus 8 at the timing when the WDT read signal is input from the control circuit 11. .
[0033]
On the other hand, the AND circuit 24 generates a pulse signal for the down counter 10 to execute a decrement operation, and prohibits the output of the pulse signal to the down counter 10 in accordance with the CE signal output from the CE generation circuit 9. Have In other words, the input terminal of the AND circuit 24 is connected so as to input the CE signal from the CE generation circuit 9 via the inverter 25, and the clock signal CK2 for driving the CPU and the timer clock signal from the control circuit 11 are input. Connected to input.
[0034]
Therefore, the AND circuit 24 is configured so that the AND condition is satisfied at the timing when the clock signal CK2 is input in the non-output state of the high-level CE signal from the CE generation circuit 9 and the timer clock signal is input from the control circuit 11, and the high-level signal Is output to the down counter 10.
[0035]
The control circuit 11 is for controlling the operation of the entire watchdog timer 6. That is, the control circuit 11 outputs a count value write signal to the down counter 10 at a timing when a read signal is given in a state where a predetermined address is accessed by the CPU 2.
The control circuit 11 has a function of outputting a timer clock signal to the AND circuit 24, for example, every 1 μs.
[0036]
Further, the control circuit 11 outputs a CE read signal at a timing when a read signal is given from the CPU 2 in a state where a predetermined address set to itself is accessed. In this case, the CE read signal is applied to the control terminal of the buffer circuit 18, and the output state of the CE signal from the CE generation circuit 9 is changed from the buffer circuit 18 to the data bus when the level of the control terminal is high. 8 to the CPU 2.
[0037]
Further, the control circuit 11 outputs a WDT read signal at the timing when the read signal is given from the CPU 2 in a state where a predetermined address set to itself (different from the CE read signal output address) is accessed. In this case, the WDT read signal is given to the control terminal of the buffer circuit 23, and the count value of the down counter 10 is output from the buffer circuit 23 to the CPU 2 through the data bus 8 with the level of the control terminal being high. Is done.
[0038]
Furthermore, the control circuit 11 has a sequencer function for adjusting the timing when the count initial value write timing for the watchdog timer 10 and the output timing of the timer clock signal for the down counter 10 overlap by the CPU 2.
[0039]
The watchdog timer 6 configured as described above is for detecting the runaway of the CPU 2, and when the CPU 2 is operating normally, the watchdog timer value before the watchdog timer value becomes zero. Is updated by the CPU 2.
[0040]
Specifically, if the update value (count initial value) is set to [C000] h, for example, when the CPU 2 runs away, the watchdog timer value is not updated before it becomes [0000] h. The timer value becomes 0, and a borrow signal is generated from the down counter 10 of the watchdog timer 6 so that an interrupt is issued to notify the CPU 2 of a runaway, or the reset is forcibly reset.
[0041]
As described above, the addresses set in the watchdog timer 5 are arranged in the memory space, but are set so as not to coincide with the addresses in the ROM 3 or the RAM 3.
[0042]
Next, the operation of the above configuration will be described.
When developing a program using the one-chip microcomputer 1, it is necessary to inspect the operation with an emulation program for debugging. In this case, the execution method of the emulation program can be stored in the ROM 3 in advance, or the emulation program can be transferred and executed on the RAM via serial communication with an external personal computer or the like. There is a method to use.
[0043]
The CPU 2 first writes [C000] h to the watchdog timer 6 in accordance with the execution of the emulation program. Then, under the control of the control circuit 11, [C000] h is written in the latch unit 20 of the down counter 10.
Here, since the control circuit 11 outputs the timer clock signal every 1 μs, the down counter 10 subtracts 1 from [C000] h every 1 μs.
[0044]
On the other hand, since the CPU 2 rewrites [C000] h to the watchdog timer 6 every predetermined period, the count initial value is written to the watchdog timer 6 every predetermined period. As a result, since the count value of the watchdog timer 6 does not become 0, the borrow signal is not output from the watchdog timer 6 to the CPU 2, and the CPU 2 continues the operation of the emulation program.
[0045]
When the CPU 2 stops the watchdog timer 6 in order to check the function of the watchdog timer 6 according to the execution of the emulation program, the CPU 2 executes an operation of writing [002B] h to the address [041C] h. (See FIG. 3).
[0046]
As a result, the bit pattern of the address bus 7 becomes [041C] h and DB5 to DB0 become [10101] b in the data bus 8, so that a high level signal is output from the A bus decoder 14 and the D bus key pattern decoder 15. Is output.
[0047]
In this state, a high level signal is output from the AND circuit 13 at the timing when the write signal IWRE is output from the CPU 2 and the clock signal CK1 is output. The bit pattern [1] is output from the output terminal Q.
[0048]
As a result of the above operation, the CE generation circuit 9 outputs a high-level CE signal, so that one level of the input terminal of the AND circuit 24 becomes a low level, and the AND circuit 24 outputs a low-level signal. . Accordingly, the count operation of the down counter 10 stops and the count value of the down counter 10 does not change (see FIGS. 3 and 4).
[0049]
The CPU 2 that has stopped the watchdog timer 6 as described above reads the operation state of the watchdog timer 6 in accordance with the execution of the emulation program.
[0050]
That is, the CPU 2 outputs an address corresponding to the CE generation circuit 9 set in the control circuit 11 in order to read the output state from the CE generation circuit 9.
Then, the control circuit 11 receives the CE read signal from the CPU 2 when the address corresponding to the CE generation circuit 9 among the addresses set to itself is selected and the CPU 2 receives the write signal IWRE. It outputs to the connected buffer circuit 18.
[0051]
As a result, the buffer circuit 18 is enabled, and the output state of the CE signal from the CE generation circuit 9 is output from the buffer circuit 18 to the data bus 8. Therefore, the CPU 2 outputs the output state of the CE signal from the CE generation circuit 9. Can be read.
[0052]
Subsequently, the CPU 2 outputs an address corresponding to the down counter 10 set in the control circuit 11 in order to read the count value of the watchdog timer 6.
Then, the control circuit 11 connects the WDT read signal to the down counter 10 when the write signal IWRE is input from the CPU 2 in a state where the address corresponding to the down counter 10 is selected among the addresses set to itself. Output to the buffer circuit 23.
[0053]
As a result, the buffer circuit 23 is enabled and the count value of the down counter 10 is output from the buffer circuit 23 to the data bus 8, so that the CPU 2 can read the current count value of the down counter 10.
[0054]
Therefore, based on the operation state of the watchdog timer 6 read by the CPU 2, the operation state by the microcomputer 1 can be confirmed at a predetermined timing set in the emulation program.
[0055]
The CPU 2 that has read the operation state of the watchdog timer 6 as described above causes the watchdog timer 6 to operate again. That is, the operation of writing [002A] h to the address [041C] h is executed (see FIG. 3).
[0056]
As a result, the CE generation circuit 9 is selected and [0], which is the level of DB0 of the data bus 8, is written into the latch circuit 12, so that the output of the CE signal from the CE generation circuit 9 is stopped.
As a result, the down counter 10 is enabled and the counting operation is resumed (see FIGS. 3 and 4).
[0057]
According to the configuration described above, the CPU 2 is configured to stop or restart the down counter 10 by accessing the CE generation circuit 9 of the watchdog timer 6 by executing the emulation program. Unlike the conventional configuration which has a dedicated terminal for stopping the watchdog timer and stops the watchdog timer by giving a signal to the dedicated terminal, the watchdog timer 6 can be set in a predetermined manner without troublesome connection. It can be stopped easily at the timing, and debugging of program development becomes easy. Further, even when the emulation is executed by interrupting the program execution, the output of the CE generation circuit 9 is set to the low level only during the period, and the normal operation is performed by setting the output of the CE generation circuit 9 to the high level after the completion of the emulation. It is very easy to use.
[0058]
Since the CPU 2 reads the operation state of the CE generation circuit 9 of the watchdog timer 6 and the count value of the down counter 10 while the watchdog timer 6 is stopped, debugging can be performed more easily. .
[0059]
Furthermore, since the address for stopping the watchdog timer 6 and the address for reading the operation state of the watchdog timer 6 are arranged in the memory space so as not to coincide with the addresses of the ROM 3 and RAM 4, the CPU 2 actually When the above program is executed, the watchdog timer 6 is not inadvertently accessed, and the counting operation of the watchdog timer 6 is not hindered.
[0060]
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
Instead of the down counter 10, an up counter may be provided, and a carry signal may be output as an abnormal signal to the CPU 2 when the counter value of the up counter reaches a limit value.
[0061]
The D bus key pattern decoder is not limited to a bit pattern of [10101] b, and is not limited to a 5-bit key pattern. Further, an address dedicated to the D passkey pattern decoder 15 is set separately from the A bus decoder 14 for the CE generating circuit 9, and the operation of the CE generating circuit 9 is enabled only when the D passkey pattern decoder 15 is enabled. As a result, malfunction can be further prevented.
[0062]
Further, although the addresses of the watchdog timer 6 are arranged in the memory space, they may be arranged in the I / O address space. In this case, access to the watchdog timer 6 is by execution of an I / O instruction by the CPU 2.
[0063]
Further, as a means for reading the operation state with the watchdog timer 6 stopped, the watchdog timer 6 may be disconnected from the CPU 2 and accessed through the data bus 8.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing the overall configuration of a one-chip microcomputer in an embodiment of the present invention. FIG. 2 is a diagram showing a specific configuration of a D passkey pattern decoder. FIG. 3 is a diagram showing various signals indicating the operation of a watchdog timer. [Figure 4] Figure showing the change in the timer count value of the watchdog timer [Explanation of symbols]
1 is a one-chip microcomputer, 2 is a CPU, 6 is a watchdog timer, 9 is a count enable generation circuit (stop command output means), 10 is a down counter (count means), 18 is a buffer circuit (output state output means), Reference numeral 23 denotes a buffer circuit (count value output means).

Claims (2)

Provided from the initial value or any set value every time it is accessed by the CPU (2) during normal operation so as to perform the count operation, when the counting of up to the limit value by runaway of the CPU (2) has been completed Is a counting means (10) for outputting an abnormal signal to the CPU (2) and stopping the counting operation in a state of receiving a stop command;
When the CPU (2) executing the emulation program performs a write operation of specific first data to its own address, a stop command is output and a specific second different from the first data is output. Stop command output means (9) for stopping the output of the stop command when the data writing operation is performed ;
Output state output means (18) for outputting the output state of the stop command by the stop command output means (9) to the CPU (2) in response to a command from the outside;
Count value output means (23) for outputting the count value of the count means (10) to the CPU (2) in response to an external command;
A control circuit (11) for giving a command to the output state output means (18) and the count value output means (23) in response to an access from the CPU (2) during execution of the emulation program ; Features a watchdog timer. A microcomputer comprising the watchdog timer according to claim 1.

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