JP2004021421A - Control method for memory device, its program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a control method for a memory device allowing a control program to be switched into a control program in use for an EEPROM while automatically discriminating the type of access pattern of the EEPROM simply by replacing the serial EEPROM having the same pin position and a different access pattern in the same place without using extra hardware. <P>SOLUTION: Random read processing for a 1-bite address is tried on each slave address of the serial EEPROM. When an acknowledge signal is returned in S3 after specifying the slave address following a start bit, the slave address is determined to be effective. When it is not returned, the slave address is determined to be ineffective. The above read processing is continued for the effective slave address. When the acknowledgement signal is returned in S7 after specifying the slave address following the start bit, a 1-bite address EEPROM is set, and when it is not returned, a 2-bite address EEPROM is set. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to determining the type of access mode of an EEPROM.
[0002]
[Prior art]
There are roughly two types of control methods for the serial EEPROM, and there are a two-wire type and a three-wire type. Hereinafter, a method of controlling a serial EEPROM by a two-wire system will be briefly described.
[0003]
As an interface used for a method of controlling a serial EEPROM by a two-wire system, ² There is a C (Inter IC Communication) bus. Currently I ² Serial EEPROMs compatible with the C bus have the advantages of being small and taking up little space on the board, and having the advantage of being inexpensive, but having eight address bits. ² Even if eight memories, which are the maximum number of connections on the C bus, are mounted, the maximum memory space is only 16 Kbits.
[0004]
In communication with the serial EEPROM, a chip select signal (A) is used as shown in FIG. ₀ , A ₁ , A ₂ ) Is TRUE, the instruction command, address, and data are continuously transmitted in synchronization with the serial synchronization clock (SCL). In a communication mode according to a normal system design, the bit value of each signal is manipulated by operating an I / O register provided corresponding to CS (chip select signal), SDA (data signal), and SCL (serial clock signal). Operate or set operation commands and addresses such as write and read to one register, and write data when writing data to the register, and output data one bit at a time in synchronization with the clock. ing.
In the case of an EEPROM having an address of 8 bits (hereinafter referred to as 1 byte), the transmission format (when writing data to the EEPROM) is as shown in FIG. In transmission, a unit from a start condition bit to a stop condition bit is one transmission operation unit. After the start of transmission, 8-bit data composed of a slave address and a read / write command bit is transmitted from the host to the EEPROM following the start condition. The second byte is an address and the third byte is data.
[0005]
As described above, when the address is one byte, I ² The maximum memory space on the C bus is 16K bits. However, since the capacity becomes insufficient in this case, an EEPROM having a capacity exceeding 16K using an address field of 2 bytes has come to be used.
[0006]
Note that there is a parallel EEPROM having a larger capacity than the serial EEPROM and a different pin arrangement. Japanese Patent Laid-Open No. Hei 10-320267 discloses that in order to cope with a shortage of capacity in the course of development and design, a memory system initially configured with a serial EEPROM is switched to a parallel EEPROM in the middle. In such a case, a memory control device and a memory control method have been proposed which enable control by the same software before and after switching.
[0007]
On the other hand, the pin arrangement of the 1-byte address serial EEPROM is exactly the same as that of the 2-byte address serial EEPROM. Therefore, a 1-byte address serial EEPROM and a 2-byte address serial EEPROM can be replaced with each other with respect to the same mounting location or socket due to the design of the memory system. However, since the communication timing is different between the 1-byte address EEPROM and the 2-byte address EEPROM, if it is desired to replace the same mounting part or socket and perform control switching between them, it is necessary to take measures after system design. It will be difficult. For example, at the design stage, even if a shortage of capacity is found in an EEPROM having a 1-byte address and a change is required to the EEPROM having a 2-byte address, it is necessary to design a 2-byte read / write processing method again.
[0008]
Therefore, when the use of both types of serial EEPROMs is switched from one to the other, the following steps can be conventionally considered as a process for switching the programs that control both of them.
(A) As disclosed in Japanese Patent Application Laid-Open No. Hei 10-320267, both types of serial EEPROMs are connected so that they can be distinguished from hardware differences. ² The C bus is prepared for each of a 1-byte address and a 2-byte address, and it is determined which EEPROM is mounted, and the program is switched according to the determination result.
(B) The person determines that the EEPROM has been replaced, and the person switches or replaces the program according to the type.
[0009]
[Problems to be solved by the invention]
However, in the above method (a), although the EEPROM having the 1-byte address and the EEPROM having the 2-byte address can be used interchangeably with respect to the same mounting location or socket, dedicated EEPROMs for both types are used. I ² It is necessary to provide a C bus. Therefore, there is a problem that extra hardware must be added.
[0010]
In addition, the method (b) has a problem that, when replacing the EEPROM, it is necessary for a person to replace the BIOS program or to provide a DIP switch in advance and to perform the switching, so that the switching cannot be easily performed.
[0011]
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and its purpose is to replace a serial EEPROM having the same pin arrangement and a different access form in the same place without providing extra hardware, and An object of the present invention is to provide a control method of a memory device capable of automatically determining the type of access mode of an EEPROM and switching a control program to a control program for the EEPROM, a program therefor, and a recording medium.
[0012]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, a method of controlling a memory device according to the present invention is directed to a memory device in which serial EEPROMs having the same pin arrangement and different access modes can be replaced and mounted in the same place. A method of controlling a memory device for effectively setting a control program for controlling access to the attached serial EEPROM, wherein the type of the access mode of the serial EEPROM attached to the memory device is A predetermined access to the EEPROM is performed to make a determination based on the response content obtained from the serial EEPROM, and the control program prepared in advance is set to be valid according to the determination result of the type of the access mode.
[0013]
According to the above-described invention, even if serial EEPROMs having the same pin arrangement and different access modes are mounted in the same location, what kind of response content can be obtained by performing predetermined access to the mounted serial EEPROM. Then, the type of the access mode is determined. Then, in accordance with the determination result, a control program prepared in advance for controlling access to the attached serial EEPROM is set to be valid.
[0014]
Therefore, by merely replacing a serial EEPROM having the same pin arrangement and a different access mode in the same location without providing extra hardware, the type of the access mode of the EEPROM is automatically determined, and the control program is stored in the EEPROM. A control method of a memory device that can be switched to the control program of the first embodiment.
[0015]
If the type of access is determined as described above and the access condition is set based on the result of the determination, it is not necessary to fix the access condition when the memory device is shipped from the product. Can be made to have versatile specifications, leading to cost reduction. In addition, there is no danger that a malfunction due to a control program setting error or the like will occur. Further, even if memory expansion of the serial EEPROM is performed in the future, it is not necessary to newly cope with software.
[0016]
Further, in order to solve the above-mentioned problem, in the control method of the memory device according to the present invention, the predetermined access is an access that can determine the type of the access mode by determining a word address size of the serial EEPROM. It is characterized by having.
[0017]
According to the above invention, the type of the access mode is determined by determining the word address size of the serial EEPROM by a predetermined access. Therefore, the type of the access mode can be determined by software without newly adding hardware. Becomes easier.
[0018]
In order to solve the above-mentioned problems, the control method of the memory device according to the present invention may be arranged such that, in the predetermined access, each of the candidate access modes in the order from the smallest word address size to the larger word address size is used. Attempt to read from the serial EEPROM as a slave at an arbitrary word address corresponding to the type, and correct the type of the access mode corresponding to the word address size at which a response content without error is obtained from the serial EEPROM. It is characterized in that the type is determined.
[0019]
According to the above invention, reading from the serial EEPROM which is a slave is attempted in the order of ascending word address size, and the type of access mode corresponding to the word address size when no error occurs is changed to the access type of the attached serial EEPROM. The type of form. An error occurs when only a word address having a size smaller than the original word address size of the serial EEPROM serving as a slave is output.
[0020]
Therefore, in the course of determining the type of the correct access mode, the data already written is overwritten by the access using the type of the access mode corresponding to the word address size larger than the word address size corresponding to the type of the correct access mode. Thus, it is possible to determine the type of access mode in a state where the data in the serial EEPROM is protected.
[0021]
Further, in order to solve the above-mentioned problem, the control method of the memory device according to the present invention is arranged so that the acknowledge signal is output to the read designation slave address output following the start condition output after the word address output to the serial EEPROM as a slave. If the error is not returned within a predetermined time from the serial EEPROM, it is determined that the error has occurred.
[0022]
According to the above invention, the presence / absence of an error is determined based on the presence / absence of the acknowledgment signal within a predetermined time, so that the presence / absence of an error can be easily determined.
[0023]
Further, in order to solve the above problem, the control method of the memory device according to the present invention is characterized in that after determining the type of the correct access mode, the number of valid bits of the word address is confirmed.
[0024]
According to the above invention, since the number of valid bits is checked after determining the type of the correct access mode, the capacity of the serial EEPROM is determined, and correct access can be performed when using the serial EEPROM.
[0025]
Furthermore, in order to solve the above problem, the method of controlling a memory device according to the present invention determines a word address size or the number of effective bits of a word address for all slave addresses, and determines whether a total capacity of all slave addresses is less than a predetermined capacity. In the case where slaves having different word address sizes are mixed, a serial EEPROM mounting error is determined and reported.
[0026]
According to the above invention, if the total capacity of all slave addresses is less than the predetermined capacity or if slaves having different word address sizes coexist, it is a serial EEPROM mounting error. By determining and reporting this mounting error from the determination of the size or the number of valid bits of the word address, it is possible to prompt replacement of a serial EEPROM that is incorrectly mounted.
[0027]
Further, in the memory device control method according to the present invention, in order to solve the above problem, the predetermined access is an access that can determine the type of the access mode by determining whether a slave address is valid or invalid. It is characterized by:
[0028]
According to the above invention, the address space that can be referred to by the word address, that is, the valid slave address changes by replacing the serial EEPROM, so that the type of access mode is determined by determining whether the slave address is valid or invalid by a predetermined access. Determine. That is, the type of access mode is determined by determining whether a device or page corresponding to the specified slave address exists. Therefore, it is easy to determine the type of access mode by software without newly adding hardware.
[0029]
Further, in order to solve the above-mentioned problem, the control method of the memory device according to the present invention, in response to a slave address output following a start condition output performed from a standby state of the serial EEPROM, receives an acknowledge signal from an addressed slave for a predetermined time. If it returns within, the slave address is determined to be valid, and if it does not return within the predetermined time, the slave address is determined to be invalid.
[0030]
According to the above invention, the validity / invalidity of the slave address is determined based on the presence / absence of the acknowledgment signal within a predetermined time, so that the validity / invalidity can be easily determined.
[0031]
Further, in order to solve the above-mentioned problem, the method of controlling a memory device according to the present invention determines the type of the access mode at the time of starting the memory device, stores the determination result, and stores the determination result when using the memory device. The control program is set to be effective according to the following.
[0032]
According to the above invention, the control program is validated according to the determination result of the type of the access mode of the serial EEPROM obtained at the time of starting the memory device. Therefore, each time the serial EEPROM is accessed, the type of the access mode is not determined. I'm done.
[0033]
In order to solve the above-mentioned problems, a program according to the present invention causes a computer to execute any one of the above-described methods for controlling a memory device.
[0034]
According to the above invention, the control method of the memory device can be made highly versatile.
[0035]
In order to solve the above-mentioned problems, a recording medium of the present invention is characterized in that the above-mentioned program is recorded in a computer-readable manner.
[0036]
According to the above invention, it becomes easy to supply a computer with a program for executing a control method of a memory device.
[0037]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below with reference to FIGS.
[0038]
FIG. 2 shows a configuration of a computer system 1 including the memory device according to the present embodiment. The computer system 1 includes a CPU 2, a memory device 3, a flash ROM 4, a RAM 5, and an ASIC 6.
[0039]
The CPU 2 controls the entire computer system 1. The memory device 3 is I ² C bus interface 3a, I ² A C bus 3b and an EEPROM 3c are provided. I ² The C bus interface 3a serves as a master ² It controls communication with the EEPROM 3c as a slave, which is an IC chip connected to the C bus 3b. (Hereafter, I ² The flash ROM 4, RAM 5, and ASIC 6 are appropriately provided as ICs or LSIs required for the operation of the computer system 1. In particular, the RAM 5 stores the result of determining the type of access to the EEPROM 3c when the memory device 3 operates, as described later.
[0040]
FIG. 3 shows an external view of a chip form of the EEPROM 3c. EEPROM3c is I ² This is a serial EEPROM corresponding to a two-wire bus such as the C bus 3b, and has eight pins. Pin A ₀ ・ A ₁ ・ A ₂ Are pins for connection according to each bit value to determine the device address of the EEPROM 3c, pin SDA is a pin for input / output of serial data, pin SCL is a pin for inputting a serial clock, and pin WP is a write pin. Pin to which signal for protection is input, Pin V _CC Is a pin connected to a power supply voltage in the range of 1.8V to 6V, _SS Is a pin connected to GND.
[0041]
FIG. 4 shows the internal configuration of the EEPROM 3c. If the signals input to each pin are represented by the names of the pins, the signal SCL and the signal A ₀ ・ A ₁ ・ A ₂ Is input to the state counter / slave address comparison circuit 31. The state counter / slave address comparison circuit 31 sends clock information to the control circuit 32. Also, the signal A ₀ ・ A ₁ ・ A ₂ Is fixed as described above, and determines whether or not a slave address including a device address and a page address included in the signal SDA sent from the control circuit 32 matches a slave address provided internally, by a signal A. ₀ ・ A ₁ ・ A ₂ Confirm by performing a comparison operation using. The control circuit 32 causes the start / stop circuit 33 to take in the bit information of the start bit, stop bit, slave address, and word address of the signal SDA at the timing of the signal SCL. To control data read and data write.
[0042]
The word address fetched by the start / stop circuit 33 is sent to a word address buffer 34. The word address buffer 34 divides the word address into rows and columns, an X decoder 35 decodes a row, and a column decoder 36 decodes a row. Perform column decoding. The signal WP is input to the control circuit 32. When the write protection is not performed, the data of the signal SDA is stored in the data register 37 in the data write, and the data register 37 stores the data in accordance with the word address. Is written into the EEPROM cell array 39. In the figure, as an example, the EEPROM cell array 39 is illustrated as a 128 × 256 or 256 × 256 cell array. At the time of writing, the high voltage / timing control circuit 38 generates a high voltage under the control of the control circuit 32 and sends it to the data register 37.
[0043]
In a data read, the column decoder 36 serves as a data read buffer, and the column decoder 36 sends the captured data to the sense amplifier / shift register 40. The sense amplifier / shift register 40 performs amplification and serialization of the data. And sends it to the output circuit 41. The output circuit 41 outputs such read data and an acknowledge signal used for a communication response with the master under the control of the control circuit 32. ² Output to C bus 3b. The output of the output circuit 41 is an open-drain output, and is pulled up by a resistor R provided outside.
[0044]
Next, with reference to FIG. 5, a slave address when the EEPROM 3c having a 1-byte address is mounted on the memory device 3 will be described.
[0045]
FIG. 5 shows a case in which two EEPROMs 3c each having a 1-byte address are mounted on the memory device 3, and the EEPROMs 3c and 32c are respectively used. Pin A for EEPROM 31c ₀ ・ A ₁ ・ A ₂ Are connected to GND, and the pin A is connected to the EEPROM 32c. ₀ ・ A ₁ Are connected to GND, and pin A ₂ Is connected to the power supply Vdd. As a result, the device address of the EEPROM 31c becomes "0" and the device address of the EEPROM 32c becomes "4".
[0046]
Each of the EEPROMs 31c and 32c includes four pages each having a capacity of 256 × 8 bits for one page. Each page address is (P ₁ , P ₀ ) = '00', '01', '10', '11'. When the slave address is specified by the signal SDA, A ₂ Bit and A ₁ ・ A ₀ P as a substitute for the bit of ₁ , P ₀ And. That is, A which constitutes the device address on the signal SDA ₁ ・ A ₀ Becomes invalid. As a result, in the memory device 3 in which the EEPROM 3c of the one-byte address is mounted, there are eight slave addresses of 000 to 111. One I ² Since there are up to eight slave addresses on the C bus, it is not possible to add more EEPROMs of the same type on this bus.
[0047]
Next, a slave address in the case where the 2-byte address EEPROM 3c is mounted on the memory device 3 will be described with reference to FIG.
[0048]
FIG. 6 shows a case where the EEPROM having the 1-byte address in FIG. 5 is replaced with an EEPROM having the 2-byte address, and the EEPROMs 33c and 34c are respectively used. That is, the EEPROM 3c having the 1-byte address and the EEPROM 3c having the 2-byte address can be replaced and mounted in the same place. Pin A for EEPROM 33c ₀ ・ A ₁ ・ A ₂ Are connected to GND, and the pin A is connected to the EEPROM 34c. ₀ ・ A ₁ Are connected to GND, and pin A ₂ Is connected to the power supply Vdd. As a result, the device address of the EEPROM 33c becomes "0" and the device address of the EEPROM 34c becomes "4".
[0049]
Each of the EEPROMs 33c and 34c has a capacity of 2k (or 4k, 8k) × 8 bits and does not have a page. Therefore, when the slave address is specified by the signal SDA, A ₂ ・ A ₁ ・ A ₀ Specify each bit of. As a result, in the memory device 3 in which the EEPROM 3c of the 2-byte address is mounted, there are two types of slave addresses, 100 and 000, and the other slave addresses become invalid.
[0050]
Next, FIG. 7 shows a communication procedure in the data read and data write of the memory device 3 described above.
[0051]
FIG. 7A shows a random read procedure for the EEPROM 3c having a 2-byte address. In the signal SDA output from the master 3a, the slave address is set to A after 1.0.1.0 after the start bit. ₂ ・ A ₁ ・ A ₀ , Followed by a write command. When the EEPROM 3c confirms the slave address and returns an acknowledge signal to the master 3a, the EEPROM 3c fetches information (1st word address) of the upper bit side of the word address in the next 1 byte and returns an acknowledge signal to the master 3a. Then, information of the lower bit side of the word address (2nd word address) is fetched by the next 1 byte, and an acknowledge signal is returned to the master 3a. Then, the master 3a outputs a start bit, a slave address following the start bit, and a read command. When the acknowledge signal is returned to the master 3a, the EEPROM 3c outputs the read 8-bit data to the master 3a. After a no-acknowledge, the master 3a outputs a stop bit and the random read ends.
[0052]
FIG. 7B shows a random read procedure for the EEPROM 3c having a 1-byte address. In the signal SDA output from the master 3a, the slave address is set to A after 1.0.1.0 after the start bit. ₂ ・ P ₁ ・ P ₀ , Followed by a write command. When the EEPROM 3c confirms the slave address and returns an acknowledgment signal to the master 3a, the EEPROM 3c fetches the word address information in the next one byte and returns an acknowledgment signal to the master 3a. Then, the master 3a outputs a start bit, a slave address following the start bit, and a read command. When the acknowledge signal is returned to the master 3a, the EEPROM 3c outputs the read 8-bit data to the master 3a, and after a no-acknowledge, the master 3a outputs a stop bit and the random read ends.
[0053]
FIG. 7C shows a procedure of byte write to the EEPROM 3c of one byte address. In the signal SDA output from the master 3a, the slave address is set to A after 1.0.1.0 after the start bit. ₂ ・ P ₁ ・ P ₀ , Followed by a write command. When the EEPROM 3c confirms the slave address and returns an acknowledgment signal to the master 3a, the EEPROM 3c fetches the word address information in the next one byte and returns an acknowledgment signal to the master 3a. Then, when the EEPROM 31c writes the data output from the master 3a and returns an acknowledge signal to the master 3a, the master 3a outputs a stop bit and the byte write ends.
[0054]
If the 2-byte address random read of FIG. 7A is performed on the 1-byte address EEPROM, the same procedure as that of the 1-byte address byte write of FIG. 7C is performed until the transmission of the second word address. Therefore, stored data may be rewritten. When it is determined whether the EEPROM has a one-byte address or a two-byte address, it is necessary to prevent such unintended data writing.
[0055]
Next, with reference to FIG. 1, a method of determining whether the type of access to the EEPROM 3c attached to the memory device 3 is a one-byte address or a two-byte address will be described.
[0056]
First, in a slave address loop, random reading of the EEPROM 3c of one byte address is attempted for all possible slave addresses (eight ways from 000 to 111). In this loop, the master 3a first outputs a start bit in S1, and outputs one of eight slave addresses in S2 with a write command specified. If the acknowledge signal is returned in S3, the process proceeds to S4, and if the acknowledge signal is not returned, the process proceeds to S11. The acknowledgment signal is returned, for example, for all the slave addresses in the case of FIG. 5, and for the slave addresses '0' and '4' in the case of FIG. This makes it possible to determine which slave address corresponds to the EEPROM. If there is no EEPROM that responds to the slave address, the process branches to S11, and the process of determining whether the address is a one-byte address or a two-byte address after S4 is skipped.
[0057]
In S4, a one-byte word address is arbitrarily output, and it is confirmed that an acknowledge signal is returned. A start bit is output in S5, and a slave address is output in S6 with a read command specified. In S7, if the acknowledge signal is returned, the process proceeds to S8. If the acknowledge signal is not returned, the process proceeds to S13. The acknowledge signal is returned in S7 when the EEPROM 3c has a one-byte address. When the EEPROM 3c has a two-byte address, the start address and the slave address correspond to the lower bits of the word address. An acknowledgment signal is not returned because of inappropriate information. Therefore, it can be understood that the slave that returns the acknowledge signal in this step is the EEPROM 3c of the one-byte address, and the slave that does not return the acknowledge signal is not the EEPROM 3c of the one-byte address.
[0058]
In S8, data read is continuously performed, and if no acknowledge is obtained, the process proceeds to S9, where a stop bit is output and a predetermined time is waited. Thus, in S10, it is determined that the EEPROM 3c has a one-byte address, and if it is set in the RAM 5 of FIG. 2 that the EEPROM 3c has a one-byte address, the determination for one slave address is completed.
[0059]
On the other hand, in S11 branched from S3, it is set that the designated slave address is invalid, and after a certain period of time waiting in S12, the determination for one slave address ends.
[0060]
Further, in S13 and subsequent steps branched from S7, random read is attempted for the EEPROM 3c of the 2-byte address. After waiting for a predetermined time in S13, a start bit is output in S14, a slave address is output in a state where a write command is specified in S15, and it is confirmed that an acknowledge signal is returned. In S16, the upper bit side of the word address is output using one byte, and it is confirmed that the acknowledge signal is returned. In S17, the lower bit side of the word address is output using one byte, and the acknowledgment is performed. Check that the signal returns. Then, a start bit is output in S18, and a slave address is output in S19 with a read command specified. In S20, if an acknowledge signal is returned, the process proceeds to S21. If an acknowledge signal is not returned, the process proceeds to S26.
[0061]
In S21, when the data read is performed and no acknowledgment is obtained, a stop bit is output in S22, and depending on the case, a certain time is waited. Thus, in S23, it is determined that the EEPROM 3c has a 2-byte address, and the fact that the EEPROM 3c has a 2-byte address is set in the RAM 5 of FIG. Then, the number of valid bits in the bits representing the word address is confirmed in S24, and the number of valid bits is set in the RAM 5 in S25. S24 will be described later. Thus, the determination for one slave address ends. On the other hand, in S26 branched from S20, it is determined that an EEPROM 3c (for example, a failed EEPROM) which is neither a 1-byte address nor a 2-byte address which is a candidate for the type of access in the memory device 3 is mounted, and the word address is determined. The fact that the size cannot be determined is set in the RAM 5. After S26, the process proceeds to S12. In any case, since this slave address cannot be used, S26 may be integrated with S11.
[0062]
Thus, the above steps are repeated for all eight slave addresses. After this loop, the process proceeds to S27, and it is determined whether or not the total of the slave capacities of the valid slave addresses is insufficient for the capacity determined to be necessary for the memory device 3. If the capacity is not insufficient, the process proceeds to S28, and if the capacity is insufficient, the process proceeds to S30 to determine that the mounting error of the EEPROM 3c has occurred. In S28, it is determined whether the 1-byte address EEPROM 3c and the 2-byte address EEPROM 3c are mixed. If not, the process proceeds to S29, and if there is, the process proceeds to S30 to determine that the mounting error of the EEPROM 3c has occurred. In S29, it is determined that the mounting of the EEPROM 3c is all normal.
[0063]
Such determination of the word address size is performed every time the memory device 3 is started, that is, every time the computer system 1 is started. FIG. 8 shows a flow of determining the word address size when the computer system 1 is started. If activated, a necessary storage capacity for the memory device 3 is specified in S41. In S42, the configuration of the EEPROM 3c is determined by performing the above-described flow of FIG. In S43, it is determined whether or not there is an error in the result of S42 from the setting result in the RAM 5. If there is no error, the process directly proceeds to the normal processing of the memory device 3, and if there is an error, the process proceeds to S44 to display an error. , The use of the memory device 3 is stopped.
[0064]
FIG. 9 shows a flow of a read process in the normal process of FIG.
[0065]
In step S51, a slave address from which data is read is calculated. In step S52, whether the word address size is 1 byte or 2 bytes is determined from the setting of the RAM 5. If it is one byte, the process proceeds to S53, where a control program for the read process for the EEPROM 3c of the one-byte address is set and the read process is performed. If it is 2 bytes, the process proceeds to S54, where a control program for the read process for the EEPROM 3c of the 2-byte address is set and the read process is performed.
[0066]
FIG. 10 shows a flow of the write process in the normal process of FIG.
[0067]
In S61, a slave address for writing data is calculated, and in S62, whether the word address size is 1 byte or 2 bytes is determined from the setting of the RAM 5. If it is one byte, the process proceeds to S63, where a control program for the write process for the EEPROM 3c of the one-byte address is set and the write process is performed. If it is 2 bytes, the process proceeds to S64, where a control program for the write process for the EEPROM 3c of the 2-byte address is set and the write process is performed.
[0068]
Next, the process of confirming the number of effective bits of the word address performed in S24 of the flowchart of FIG. 1 will be described.
[0069]
In order to confirm the number of valid bits of the word address, first, the slave specifies the largest possible word address when using bits that can be used for the word address, and stores predetermined data. This data is stored in the largest word address that is actually used, ignoring upper bits that are not actually used. Therefore, if the word address where the above data is stored in the slave is checked, since the word address is the maximum value of the word address actually used in the slave, it is possible to confirm the number of effective bits of the word address. it can.
[0070]
FIG. 11 shows this example. FIG. 6A shows that the slave has a capacity of 2 k × 8 bits, FIG. 6B shows that the slave has a capacity of 4 k × 8 bits, and FIG. 6C shows that the slave has a capacity of 8 k × 8 bits. This indicates that the device has an 8-bit capacity. At this time, when the predetermined data is written as FFFFH in the 2-byte address in hexadecimal by the write processing, it is set to 07FFH in FIG. 10A, to 0FFFH in FIG. 10B, and to 1FFFH in FIG. Predetermined data is stored. Then, data matching the predetermined data is searched for, and the word address where the data is stored is obtained. In the case of a 2-byte address, the number of effective bits is 11 bits or more.
[0071]
In addition, at the time of write processing of predetermined data, in addition to the maximum possible word address, if the word address is known to be equal to or more than the maximum value of the actually used word address, the predetermined address is stored there. May be used since the data is stored at the maximum value of the word address actually used. For example, in FIG. 11B, data is stored in 0FFFH even if the designated word address is FFFFH, EFFFH,..., 2FFFH, 1FFFFH, or 0FFFH.
[0072]
As described above, in the control method of the memory device 3 according to the present embodiment, the type of the access mode of the EEPROM 3c mounted on the memory device 3 is changed by performing a predetermined access such as a random read for one byte address to the EEPROM 3c. Then, the control program prepared in advance is set to be valid according to the determination result of the type of the access mode.
[0073]
That is, even if the EEPROMs 3c having the same pin arrangement and different access modes are mounted in the same location, the type of access mode depends on what kind of response is obtained by performing predetermined access to the mounted EEPROM 3c. Is determined. Then, in accordance with the determination result, a control program prepared in advance for controlling access to the mounted EEPROM 3c is set to be valid.
[0074]
Therefore, I corresponding to each type of access mode ² By simply replacing an EEPROM 3c having the same pin arrangement and a different access mode in the same place without providing extra hardware such as a C bus, the type of the access mode of the EEPROM 3c is automatically determined, and the control program is stored in the EEPROM. Can be switched to a control program.
[0075]
In addition, if the type of the access mode is determined as described above and the access condition is set based on the determination result, it is necessary to fix the access condition when the memory device 3 or the computer system 1 is shipped from the product. Since there is no control program, the control program of the EEPROM 3c can be made to have versatile specifications, which leads to cost reduction. In addition, there is no danger that a malfunction due to a control program setting error or the like will occur. Further, even if the memory of the EEPROM 3c is expanded in the future, it is not necessary to newly deal with software.
[0076]
Further, in the present embodiment, the predetermined access is an access in which the type of the access mode can be determined by determining the word address size of the EEPROM 3c as performed in S7 of FIG. Therefore, it is easy to determine the type of access mode by software without newly adding hardware.
[0077]
Further, in the present embodiment, in the above-mentioned predetermined access, candidate words are sequentially arranged in the order of increasing word address size from the smallest word address size such as a 1-byte address to the next 2-byte address. An attempt is made to read from the EEPROM 3c as a slave at an arbitrary word address corresponding to the type of access mode. Then, the type of the access mode corresponding to the word address size at which the response content in which no error occurs from the EEPROM 3c, that is, the response content in which the acknowledge signal is returned without the no acknowledge is determined as the correct access mode type. .
[0078]
That is, reading from the EEPROM 3c as a slave is attempted in ascending order of the word address size, and the type of access mode corresponding to the word address size when no error occurs is set as the type of access mode of the mounted EEPROM 3c. An error occurs when only a word address having a size smaller than the original word address size of the EEPROM 3c as a slave is output.
[0079]
Therefore, in the course of determining the type of the correct access mode, the data already written is overwritten by the access using the type of the access mode corresponding to the word address size larger than the word address size corresponding to the type of the correct access mode. Thus, the type of access mode can be determined while the data in the EEPROM 3c is protected.
[0080]
Further, in the present embodiment, an error occurs for the read designation slave address output following the start condition output after the word address output to the EEPROM 3c as a slave unless the acknowledge signal is returned from the EEPROM 3c within a predetermined time. Is determined. As described above, the presence / absence of an error is determined based on the presence / absence of the acknowledgment signal within a predetermined time, so that the presence / absence of an error can be easily determined.
[0081]
Further, in the present embodiment, after determining the type of the correct access mode, the number of valid bits of the word address is confirmed. Therefore, the capacity of the EEPROM 3c is determined, and correct access can be performed when using the EEPROM 3c.
[0082]
Further, in this embodiment, the word address size or the number of effective bits of the word address is determined for all the slave addresses, and the total capacity of all the slave addresses is less than the predetermined capacity, or slaves having different word address sizes are mixed. In this case, it is determined that the mounting error of the EEPROM 3c has occurred, and a notification is issued. Therefore, by determining and notifying the mounting error from the determination of the word address size or the number of effective bits of the word address for all slave addresses, replacement of the erroneously mounted serial EEPROM 3c can be prompted.
[0083]
Further, in the present embodiment, the type of the access mode can be determined by determining whether the slave address is valid or invalid as performed in S3 of FIG. 1 based on the response to the slave address output as a predetermined access. .
[0084]
As described above, the address space that can be referred to by the word address, that is, the valid slave address changes by replacing the EEPROM 3c. Therefore, the type of the access mode is determined by determining whether the slave address is valid or invalid by a predetermined access. That is, the type of access mode is determined by determining whether a device or page corresponding to the specified slave address exists. Therefore, it is easy to determine the type of access mode by software without newly adding hardware.
[0085]
Also, in this case, if the acknowledge signal is returned within a predetermined time from the slave specified by the slave address output following the start condition output performed from the standby state of the EEPROM 3c, it is determined that the slave address is valid. Otherwise, it is determined that the slave address is invalid. Therefore, it is possible to easily determine whether the slave address is valid or invalid.
[0086]
Further, in the present embodiment, as described with reference to FIG. 8, the type of the access mode is determined at the time of activation of the memory device 3 and the determination result is stored in the RAM 5, and the determination result is determined during normal use of the memory device 3. Set the control program valid according to. Therefore, it is not necessary to determine the type of the access mode each time the EEPROM 3c is accessed.
[0087]
In the present embodiment, the control method of the memory device 3 can be realized by a program to be executed by a computer. Thereby, the control method of the memory device 3 can be made highly versatile. Further, this program can be stored in a computer-readable recording medium. This makes it easy to supply a computer with a program for executing the control method of the memory device 3.
[0088]
As the recording medium, since the processing is performed by the microcomputer, the memory itself in the computer system 1 such as the flash ROM shown in FIG. 2 may be a program medium, or not shown. A program reading device may be provided as an external storage device, and may be a program medium readable by inserting a recording medium into the program reading device.
[0089]
In any case, the stored program may be configured to be accessed and executed by a microprocessor, or in any case, the program may be read, and the read program may be stored in a microcomputer. The program may be downloaded to a program storage area that is not stored, and the program may be executed. It is assumed that this download program is stored in the main unit in advance.
[0090]
Here, the program medium is a recording medium configured to be separable from the main body, such as a tape system such as a magnetic tape or a cassette tape, a magnetic disk such as a floppy disk or a hard disk, or a CD-ROM / MO / MD / DVD. Disc system of an optical disc, a card system such as an IC card (including a memory card) / optical card, or a mask ROM, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically Erasable Programmable Read Only Memory, a semiconductor, etc.) It may be a medium including a memory and fixedly holding a program.
[0091]
Further, in the present embodiment, since the system configuration is such that a communication network including the Internet can be connected, a medium that carries the program in a fluid manner so that the program is downloaded from the communication network may be used. When the program is downloaded from the communication network, the download program may be stored in the main device in advance, or may be installed from another recording medium.
[0092]
【The invention's effect】
As described above, the control method of the memory device according to the present invention is applied to a memory device which can be mounted by replacing serial EEPROMs having the same pin arrangement and different access modes with each other at the same location. A method of controlling a memory device for effectively setting a control program for controlling access to the serial EEPROM, wherein a type of the access mode of the serial EEPROM mounted on the memory device is stored in the serial EEPROM in a predetermined manner. And makes a determination based on the response content obtained from the serial EEPROM, and validates the control program prepared in advance according to the determination result of the type of the access mode.
[0093]
Therefore, by merely replacing a serial EEPROM having the same pin arrangement and a different access mode in the same place without providing extra hardware, the type of the access mode of the EEPROM is automatically determined, and the control program is stored in the EEPROM. And a control method of the memory device that can be switched to the control program for the memory device.
[0094]
If the type of access is determined as described above and the access condition is set based on the result of the determination, it is not necessary to fix the access condition when the memory device is shipped from the product. The control program can be made to have versatile specifications, leading to an effect of reducing costs. Furthermore, there is an effect that there is no danger of occurrence of a malfunction due to a setting mistake of the control program or the like. Furthermore, even if memory expansion of the serial EEPROM is performed in the future, there is an effect that it is not necessary to newly cope with software.
[0095]
Furthermore, the control method of the memory device according to the present invention is configured such that the predetermined access is an access that can determine the type of the access mode by determining the word address size of the serial EEPROM. is there.
[0096]
Therefore, there is an effect that it is easy to determine the type of access mode by software without newly adding hardware.
[0097]
Further, as described above, the control method of the memory device according to the present invention, in the above-mentioned predetermined access, corresponds to each of the above-mentioned candidate access modes in the order of the smallest word address size and sequentially increasing the word address size. Attempt to read the serial EEPROM as a slave at an arbitrary word address, and change the type of the access mode corresponding to the word address size at which a response content that does not cause an error from the serial EEPROM to the correct type of the access mode This is the configuration for determination.
[0098]
Therefore, in the course of determining the type of the correct access mode, the data already written is overwritten by the access using the type of the access mode corresponding to the word address size larger than the word address size corresponding to the correct access mode. Thus, the type of access mode can be determined in a state where the data in the serial EEPROM is protected.
[0099]
Further, as described above, the control method of the memory device according to the present invention is such that the acknowledge signal is output from the serial EEPROM to the read designation slave address output following the start condition output after the word address output to the serial EEPROM as a slave. If it does not return within a predetermined time, it is determined that the error has occurred.
[0100]
Therefore, it is possible to easily determine whether or not an error has occurred.
[0101]
Further, the control method of the memory device according to the present invention has a configuration in which the number of valid bits of the word address is confirmed after the type of the correct access mode is determined as described above.
[0102]
Therefore, the capacity of the serial EEPROM can be determined, and an effect can be obtained that the access can be performed correctly when using the serial EEPROM.
[0103]
Further, the control method of the memory device of the present invention, as described above, determines the word address size or the number of effective bits of the word address for all slave addresses, and determines whether the total capacity of all slave addresses is less than a predetermined capacity or a different word. This is a configuration in which if there is a mixture of slaves of the address size, it is determined that there is an error in mounting the serial EEPROM, and a notification is made.
[0104]
Therefore, there is an effect that it is possible to prompt the exchange of the serial EEPROM which is erroneously mounted.
[0105]
Further, the control method of the memory device according to the present invention is configured such that the predetermined access is an access that can determine the type of the access mode by determining whether the slave address is valid or invalid. .
[0106]
Therefore, there is an effect that it is easy to determine the type of access mode by software without newly adding hardware.
[0107]
Further, as described above, according to the memory device control method of the present invention, in response to the slave address output following the start condition output performed from the standby state of the serial EEPROM, the acknowledge signal is returned from the addressed slave within a predetermined time. For example, the slave address is determined to be valid, and if not returned within the predetermined time, the slave address is determined to be invalid.
[0108]
Therefore, it is possible to easily determine whether the slave address is valid or invalid.
[0109]
Further, as described above, the control method of the memory device according to the present invention performs the type determination of the access mode at the time of starting the memory device, stores the determination result, and controls the control according to the determination result when using the memory device. In this configuration, the program is set to be valid.
[0110]
Therefore, there is an effect that it is not necessary to determine the type of the access mode every time the serial EEPROM is accessed.
[0111]
Further, as described above, the program of the present invention is configured to cause a computer to execute any one of the above-described memory device control methods.
[0112]
Therefore, there is an effect that the control method of the memory device can be made highly versatile.
[0113]
Further, the recording medium of the present invention has a configuration in which the above program is recorded in a computer-readable manner as described above.
[0114]
Therefore, it is possible to easily supply a program for executing the control method of the memory device to the computer.
[Brief description of the drawings]
FIG. 1 is a flowchart illustrating a method for controlling a memory device according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a memory device and a computer system including the memory device.
FIG. 3 is a plan view showing the appearance of a serial EEPROM.
FIG. 4 is a block diagram showing an internal configuration of the serial EEPROM of FIG. 3;
FIG. 5 is a block diagram illustrating a slave address of a serial EEPROM having a 1-byte address.
FIG. 6 is a block diagram illustrating a slave address of a 2-byte serial EEPROM.
FIGS. 7A to 7C are signal diagrams illustrating an access state to a serial EEPROM.
FIG. 8 is a flowchart illustrating a process performed when the memory device is activated.
FIG. 9 is a flowchart illustrating a read process of the memory device.
FIG. 10 is a flowchart illustrating a write process of the memory device.
FIGS. 11A to 11C are memory map diagrams for explaining a state in which the number of valid bits of a serial EEPROM is checked.
[Explanation of symbols]
3 Memory device
3c EEPROM (Serial EEPROM)
31c, 32c, 33c, 34c
EEPROM (Serial EEPROM)

Claims (11)

A control program for controlling access to the mounted serial EEPROM is enabled for a memory device in which serial EEPROMs having the same pin arrangement and different access modes can be replaced and mounted in the same location. A method of controlling a memory device to be set to
Determining a type of the access mode of the serial EEPROM mounted on the memory device based on a response content obtained from the serial EEPROM by performing a predetermined access to the serial EEPROM;
A control method for a memory device, wherein the control program prepared in advance is set to be valid according to a result of the determination of the type of the access mode. 2. The method according to claim 1, wherein the predetermined access is an access that can determine a type of the access mode by determining a word address size of the serial EEPROM. In the predetermined access, reading from the serial EEPROM as a slave is performed at an arbitrary word address corresponding to each of the candidate access modes in the order of increasing the word address size from the smallest word address size. 3. The memory device according to claim 2, wherein the type of the access mode corresponding to the word address size at which an error-free response content is obtained from the serial EEPROM is determined as a correct type of the access mode. Control method. In response to a read designation slave address output following a start condition output after a word address output to the serial EEPROM as a slave, if the acknowledge signal is not returned from the serial EEPROM within a predetermined time, it is determined that the error has occurred. The method according to claim 3, wherein 5. The method according to claim 2, wherein the number of effective bits of the word address is confirmed after determining the type of the access mode. The word address size or the number of effective bits of the word address is determined for all the slave addresses, and if the total capacity of all the slave addresses is less than the predetermined capacity or if the slaves having different word address sizes are mixed, the serial EEPROM is determined. 6. The memory control method according to claim 2, wherein a mounting error is determined and notified. 7. The memory device according to claim 1, wherein the predetermined access is an access that can determine the type of the access mode by determining whether the slave address is valid or invalid. Control method. In response to a slave address output following a start condition output from the standby state of the serial EEPROM, if an acknowledge signal is returned from the addressed slave within a predetermined time, it is determined that the slave address is valid, and the slave address is determined to be valid. 8. The method according to claim 7, wherein if not returned, the slave address is determined to be invalid. 9. The method according to claim 1, wherein the type of the access mode is determined at the time of activation of the memory device and the determination result is stored, and the control program is set to be valid according to the determination result when the memory device is used. The method for controlling a memory device according to any one of the above. A program for causing a computer to execute the control method for a memory device according to claim 1. A recording medium characterized by recording the program according to claim 10 in a computer-readable manner.

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