JP3433824B2 - Failure detection device for pulse input / output circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fault detecting apparatus for a pulse input / output circuit, and more particularly to a fault detecting apparatus for a pulse input / output circuit used for controlling various systems for vehicles. It relates to a device for detecting. [0002] A pulse input / output circuit is generally used as a circuit for electronically controlling various devices mounted on an automobile. For example, Japanese Patent Publication No. Sho 62-43070 discloses a pulse input / output circuit for performing pulse control of a fuel injection amount and an ignition timing in an engine. Such a pulse input / output circuit includes a plurality of ports for inputting / outputting a logical pulse signal, and a plurality of registers for holding predetermined data, and reads / writes / writes data to / from the ports and the registers. Processing such as a logical operation is performed. In a pulse input / output circuit of a so-called sequential processing execution type, programs indicating processing contents to be executed are sequentially stored in a storage device, and the programs are sequentially executed while being read out in order. For example, a certain port receives a logical pulse signal from a sensor that detects a specific running state of the vehicle, and another port outputs an instruction given to a specific actuator of the vehicle as a logical pulse signal. The pulse input / output circuit transfers a logical value input to a certain port to a certain register, outputs a held value of a certain register from a certain port, or outputs a predetermined value to the contents of a certain register based on a read program. And performs various processes, such as performing calculations, to control various devices mounted on the vehicle. When such a pulse input / output circuit is used, it is necessary to provide some kind of failure detection means. In particular, since the on-vehicle pulse input / output circuit plays an important role of electronically controlling various devices mounted on the automobile, the failure detection means is indispensable for ensuring safe traveling. However, as described above, the functions of the pulse input / output circuit are as diverse as reading / writing data to / from a port, reading / writing data to / from a register, and performing a logical operation (mainly adding 1) on the read data. It is necessary to diagnose whether or not each of these functions is operating normally.
However, since this pulse input / output circuit does not have a built-in CPU, a failure diagnosis function is conventionally added by adding diagnosis hardware to perform the above-described diagnosis. Was. However, when such diagnostic hardware is added, the circuit scale becomes large, which is a factor that hinders downsizing and cost reduction of the circuit. SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse input / output circuit failure detecting device which can make the hardware configuration as simple as possible. According to the present invention, there is provided an input / output port group having a plurality of ports for inputting / outputting a logical pulse signal, and a register group having a plurality of registers for holding predetermined data. A port / register control device that executes each process of reading data, writing data, and performing logical operation on data for each port and each register;
A storage unit storing the processing contents to be executed by the port / register control device in a predetermined order, and the processing contents stored in the storage unit are sequentially taken out.
A pulse decoding circuit provided with a command decoding circuit for giving this to a port / register control device and executing the command decoding circuit. When the stored value of the first register matches the stored value of the second register, the logic state of a predetermined port is inverted, and the stored value of the first register is returned to the initial value. Processing and
While counting the predetermined clock signal, the count value is stored in the third register, and when the logic state of the predetermined port is inverted, the value held in the second register is changed to the third register.
And the second process of rewriting the held value of the third register to the initial value and storing the first process and the second process by the port / register control device. Upon execution, failure detection is performed by determining whether or not the inversion cycle of the above-described predetermined port logical state matches a predetermined cycle that is set in advance. [0008] In the fault detecting apparatus for a pulse input / output circuit according to the present invention, two processes are executed for fault detection. In the first process, the count value of the clock signal is stored in a first register, and when the value held in the first register matches the value held in the second register, the logic state of a predetermined port is set. Is performed, and the value held in the first register is returned to the initial value. In the second process, the count value of the clock signal is stored in the third register, and when the logic state of the predetermined port is inverted, the value held in the second register is changed to the third register. This is a process of rewriting the stored value of the third register to the initial value. These two processes depend on each other. In other words, the configuration is such that one processing result affects the other processing. Specifically, the value held in the second register used as the target of match detection in the first processing is a value obtained as a result of the second processing. Similarly, the inverted state of the predetermined port used in the second processing is created as a result of the first processing. As described above, since the two processes depend on each other, if both processes are executed normally, a predetermined logic state is always obtained at a predetermined cycle at a predetermined port. Become. Conversely, if a predetermined logical state cannot be obtained in this port at a predetermined cycle, it can be considered that an abnormality has occurred in any of the processes. The two processes described above include all processes of reading / writing data to / from a port, reading / writing data to / from a register, and performing a logical operation (an operation of adding 1 to perform counting) on the read data. Therefore, diagnosis of all these processes becomes possible. Moreover, since it is only necessary to prepare a program for executing the above two processes in the storage device, the diagnosis can be executed by software, and the necessary hardware configuration can be minimized. . BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 1 is a block diagram showing a basic configuration of an automobile system control device including a pulse input / output circuit to which a failure detection device according to the present invention is applied. First, the configuration and operation of the entire vehicle system control device will be described. The pulse input / output circuit 100 is a unit that performs subordinate control in the control device. The main control in this control device is executed by a host unit 200 having a built-in CPU. However, the operation of the host unit 200 itself is not the essence of the present invention, and a detailed description thereof will be omitted. The pulse input / output circuit 100 is connected to a CPU in the host unit 200 by a bus 150. In the pulse input / output circuit 100, CP
Although U is not built-in, the following circuit is built-in. [0008] In the device of this embodiment, the memory 10
M, and the programs are written in a predetermined order. The host unit 200 can write an arbitrary program into the memory 10 via the bus 150. The activation register 11 is a register for storing information of only one bit, and the host unit 2
00 can write either “0” or “1” data into the activation register 11 via the bus 150. The function of the pulse input / output circuit 100 is stopped when data "0" is written in the activation register 11, but the program in the memory 10 is stopped when data "1" is written. Execute sequentially. AND circuit 1
2 functions to supply an externally applied clock to the program counter 13 only when data "1" is written in the activation register 11. The program counter 13 counts the count value P based on this clock.
Count up C. The program stored in the memory 10 receives an address specified by the count value PC and is read out to the instruction decoding circuit 14 in the order of the programs 1, 2, 3,.... When the count value PC reaches the last address value in the memory 10, the program counter 13 returns the count value to the initial value and continues counting. Thus, each program in the memory 10 is read cyclically. The instruction decoding circuit 14 decodes the program read from the memory 10 and transmits the decoded contents to the port / register control device 15. The port / register control device 15 executes a predetermined process based on the decoded program. That is, data read / write processing is executed for a specific register in the register group 16, data read / write processing is executed for a specific port in the input / output port group 17, A predetermined logical operation (an operation of adding 1 in this embodiment) is performed on the read data. The kind of processing to be performed depends entirely on the given program. In this embodiment, the register group 16 is composed of eight registers reg1 to reg8, and can store predetermined data. In this embodiment, the input / output port group 17 includes external ports OP1 and OP
, And internal ports IP1, IP2,. The external port OPn is a terminal connected to an external device, and inputs a logical pulse signal from an external device (various sensors) or outputs a logical pulse signal to an external device (various actuators). It has a function to do. On the other hand, the internal port IPn is an internal terminal that can maintain a predetermined potential state. The pulse input / output circuit 100 having such a configuration performs a subordinate system control on the vehicle based on a group of programs written in the memory 10. That is, the logic state input to a specific external port is stored in a specific register or a specific internal port,
A process of adding 1 to a value held in a specific register and outputting the result to a specific register or a specific port is executed. In this way, a predetermined control value is output to various actuators according to the detection values input from various sensors, and the system is controlled. The present invention relates to such a pulse input / output circuit 1
00 is provided. Conventionally, such a failure detection device is connected to a pulse input / output circuit 1
The present invention is realized by adding dedicated hardware to 00, but in the present invention, this failure detection is executed using software, and the addition of dedicated hardware is minimized. . In order to perform the failure detection according to the present invention, two failure detection programs are prepared. Here, these two programs are called function1 and function2. These two programs each include a process of counting the same clock signal clock1. As the clock signal clock1, for example, an AND circuit 1
A signal obtained by dividing the frequency of one of the two input signals may be used. The function 1 is a program for executing a process as shown in the flowchart of FIG. That is, in step S11, it is determined whether or not clock1 is inverted. If the logical value of clock1 is the same as the previous time (that is, if it has not been inverted yet), the process ends without executing anything. If clock1 is inverted, in step S12, the value held in the first register reg1 in the register group 16 is increased by 1 (the value held in the register is read out, and an operation of adding 1 is performed. Write to the register again). Then, in step S13,
The value held in the first register reg1 and the second register r
It is determined whether or not the stored value of eg2 is equal. If they are not equal, the process ends there. If they are equal, in step S14, the logic state of the first internal port IP1 in the input / output port group 17 is inverted, and the value held in the first register reg1 is returned to the initial value “0” (0 is written). ). FIG. 3 is a diagram showing the above processing.
Each time the rising edge or falling edge of clock1 is detected, the content of the first register reg1 becomes 1
Each time it increases (step S12). Therefore, the value held in the first register reg1 gradually increases from 0. Then, every time this value reaches the value held in the second register reg2 (step S13), the logical value of the internal port IP1 is inverted, and the first register reg2 is inverted.
1 is returned to "0" (step S14). Therefore, if the value of the second register reg2 is constant as shown in FIG. 3, the first register reg1 becomes
The operation of repeatedly counting up to the value of 0 to reg2 is performed, and the logic state of the internal port IP1 repeats inversion in synchronization with this repetition operation. This inversion cycle is always constant if the cycle of clock1 and the held value of reg2 are constant. On the other hand, function2 is a program for executing the processing as shown in the flowchart of FIG. That is, in step S21, it is determined whether or not clock1 is inverted. If the logical value of clock1 is the same as the previous time (that is, if it has not been inverted yet), the process ends without executing anything. If clock1 is inverted, step S
22, the third register re in the register group 16
The held value of g3 is increased by 1 (the held value of the register is read out, an operation of adding 1 is performed, and the result is written into the register again). Then, in step S23, it is determined whether or not the logical state of the internal port IP1 has been inverted. If the logical state is the same as that of the previous time (that is, if the logical state has not been inverted yet), the process ends there. If it has been inverted, in step S24, the value held in the second register reg2 is changed to the third register reg3.
And the value held in the third register reg3 is returned to the initial value “0” (0 is written). FIG. 5 is a diagram showing the above processing. Third register reg
The content of 3 is incremented by 1 each time a rising edge or a falling edge of clock1 is detected (step S22). Therefore, the third register reg3
Is gradually increased from 0. This count-up operation continues until the logical value of the internal port IP1 is inverted. When the logical inversion of the internal port IP1 occurs (step S23), after the value of the third register reg3 at that time is moved to the second register reg2,
The third register reg3 is returned to "0" (step S24). Therefore, if the inversion cycle of the internal port IP1 is constant as shown in FIG. 5, the third register reg3 increases at the timing of clock1 only during this inversion cycle, and the second register reg
2, a value corresponding to this inversion cycle is written every time. After all, clock1 period and internal port IP1
Is constant, the value held in the second register reg2 is always constant. In order to perform failure detection, as described above, fu
The nction1 and the function2 may be written as programs from the host unit 200 into the memory 10 via the bus 150, and these may be repeatedly executed. clock1
Is a clock signal obtained by dividing the driving clock supplied to the pulse input / output circuit 100, and its cycle is always constant unless a failure occurs. By the way, function1 is a process of inverting the internal port IP1 at a cycle corresponding to the value of the second register reg2.
nction2 is a process of writing a value corresponding to the inversion cycle of the internal port IP1 to the second register reg2. In other words, the configuration is such that one processing result affects the other processing. FIG. 6 is a diagram showing the relationship between the two processes. Therefore, as long as there is no abnormality in any of the processes, the value of the second register reg2 is constant, and the inversion cycle of the internal port IP1 is also constant. Therefore, if it is determined whether or not the internal port IP1 is inverted at regular intervals, it is possible to recognize the presence or absence of a failure. The processing of function1 and function2 includes all processing of reading / writing data to / from a port, reading / writing data to / from a register, and performing a logical operation (an operation of adding 1 to perform counting) on the read data. If any one of these processes has an abnormality, the relationship in the diagram shown in FIG. 6 is not satisfied, and the inversion cycle of the internal port IP1 is disturbed. Therefore, failure diagnosis can be performed for the entire process of the pulse input / output circuit 100. In addition, the above-described diagnostic processing is performed by storing two diagnostic programs func in the memory 10.
It is only necessary to write and execute tion1 and function2, so there is no need to add special hardware. However, in order to determine whether or not the internal port IP1 is inverted at regular intervals, some hardware is required. FIG. 7 shows an example of a circuit for making such a determination. This determination circuit is based on the AND circuit 2
1, a flip-flop 22, a counter circuit 23, and an exclusive OR circuit 24. AND circuit 2
1 has one input terminal connected to the internal port IP1;
The bit of the activation register 11 is input to the other input terminal. That is, when the activation register 11 stores the bit “1” indicating the activation state, the AND circuit 2
1 outputs a signal indicating the logical state of the internal port IP1. This signal is supplied to the flip-flop 22
To the D input terminal. On the other hand, the counter circuit 23
The clock input terminal clk of this embodiment (using a watchdog timer) is supplied with clock2 obtained from a clock signal of a different system from clock1. Generally, an in-vehicle system control device includes a standby system unit that performs emergency control in place of a normal control unit in the event of a failure. Is designed to operate with a clock of a different system from the clock used. In such a case, it is preferable to use another system clock for the standby system unit as clock2. Thus, the use of clock2 of a different system from clock1 is c
This is because even if a failure occurs in lock1 itself, it is possible to detect an abnormality. (When the same clock1 is used, a failure such as the clock1 cycle having been extended twice has been considered. If it occurs, it cannot be detected). From the counter circuit 23, output signals of MSB (most significant bit) and MSB-1 (second high order bit) are taken out, and the latter is supplied to the clock input terminal clk of the flip-flop 22, while the former is exclusive. It is provided to one input terminal of the logical OR circuit 24. Also, exclusive OR
The other input terminal of the circuit 24 has a flip-flop 22
Are provided. The operation of such a decision circuit will be described with reference to the timing chart of FIG. Now, it is assumed that the (MSB-1) output signal and the MSB output signal of the counter circuit 23 are periodic signals as shown in the figure. Assuming that the former inversion cycle is L / 2, the latter indicates a count value one digit higher, so that the latter has an inversion cycle L twice as large. On the other hand, the output signal from the internal port IP1 is
As described above, as long as the pulse input / output circuit 100 operates normally, it has a constant inversion cycle. So MS
The inversion cycle of the B output signal and the inversion cycle of the internal port IP1 when the internal port IP1 is normal are set in advance so as to be the same L (this may be done by adjusting the setting of the counter circuit 23 used, 2 may be adjusted when the steady value of the register reg2 is initialized.) Anyway, the inversion cycle of the MSB output signal and the inversion cycle of the internal port IP1 (when normal) are set to the same L. However, as described above, the output signal of the internal port IP1 is clock1
Since the MSB output signal is obtained based on clock 2 of another system, the phases of the two do not match as shown in FIG. The flip-flop 22 functions to adjust the phase difference. That is, when the output signal from the internal port IP1 given to the D input terminal is output from the Q output terminal, (MS
B-1) The signal Q has the same phase as the output signal. If the pulse input / output circuit 100 operates normally, the internal port IP1 repeats logical inversion at the inversion cycle L, so that this signal Q should completely match the MSB output signal. The exclusive OR circuit 24 is a circuit that detects this coincidence.
That is, if they match, a logic “0” is output (the pulse input / output circuit 100 is normal), and if they do not match, a logic “1” is output (the pulse input / output circuit 100 fails). Thus, the output signal of the exclusive OR circuit 24 can be used as a failure detection signal. The hardware shown in FIG. 7 is a relatively simple circuit, and adding such a circuit to the pulse input / output circuit 100 does not impose a significant load. Although the present invention has been described based on the illustrated embodiment, the present invention is not limited to this embodiment, but can be implemented in various other modes. For example, in the circuit shown in FIG.
However, instead of this clock2, the same clo
It is also possible to use ck1. However, as described above, in order to detect the abnormality of the clock itself,
It is preferable to use clock2. Further, the circuit shown in FIG. 7 is shown as an example. In short, any other circuit that can confirm that the logical inversion cycle of the internal port IP1 is the predetermined cycle L is used. A simple circuit may be used. As described above, according to the present invention, in order to detect a failure of the pulse input / output circuit, two processing programs for accessing a port and a register are prepared, and both programs are mutually connected programs. In this embodiment, the failure detection is performed by confirming that a constant execution result is always obtained, so that the hardware configuration can be simplified as much as possible.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a basic configuration of a pulse input / output circuit to which a failure detection device according to the present invention is applied. FIG. 2 is a flowchart showing processing contents of a program function1 used in failure detection according to the present invention. FIG. 3 is a diagram corresponding to the processing contents shown in FIG. 2; FIG. 4 is a flowchart showing processing contents of a program function2 used in failure detection according to the present invention. FIG. 5 is a diagram corresponding to the processing content shown in FIG. 4; FIG. 6 is a diagram showing a mutual relationship between two programs function1 and function2. FIG. 7 is an internal port I in the diagram shown in FIG. 6;
FIG. 4 is a circuit diagram illustrating an example of a circuit that determines whether a logical state of P1 is a fixed cycle. FIG. 8 is a timing chart showing the operation of the circuit of FIG. 7; [Description of Signs] 0 memory 11 start register 12 AND circuit 13 program counter 14 instruction decoding circuit 15 port register controller 16 register group 17 input / output port group 21 AND circuit 22 flip-flop 23 counter circuit 24 exclusive OR circuit 100 pulse input / output circuit 150 bus 200 host units reg1 to reg8 registers OP1, OP2, external ports IP1, IP2, internal ports clock1, clock2 clock signals

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-297226 (JP, A) JP-A-63-307541 (JP, A) JP-A-1-1855741 (JP, A) JP-A 61-307 260336 (JP, A) Japanese Utility Model Hei 4-90252 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/00 G06F 11/30 G06F 1/04

Claims (1)

(57) Claims: 1. An input / output port group having a plurality of ports for inputting / outputting a logical pulse signal, a register group having a plurality of registers for holding predetermined data, A port / register control device that executes each process of reading data, writing data, and performing logical operation on data with respect to a port and the register, and a process content to be executed by the port / register control device, A pulse input / output circuit comprising: a storage unit that stores the processing contents stored in the storage unit in the order described above; and an instruction decoding circuit that sequentially retrieves the processing content stored in the storage unit and supplies the processing content to the port / register control device for execution. , Detecting a failure in the first register while counting a predetermined clock signal and storing the counted value in a first register. A first process for inverting the logic state of a predetermined port and returning the held value of the first register to an initial value when the held value of the data matches the held value of the second register; While counting the signals, the count value is stored in a third register, and when the logic state of the predetermined port is inverted, the value held in the second register is changed to the value held in the third register. Rewrite and the third
A second process for returning the held value of the register to an initial value; and storing the second process in the storage unit, and when the first process and the second process are executed by the port / register control device, A failure detection device for a pulse input / output circuit, wherein failure detection is performed by determining whether the inversion cycle of the logic state of a predetermined port matches a predetermined cycle set in advance.