JPH06250868A - Computer - Google Patents

Abstract

PURPOSE:To remove an error by independently constituting three operation control parts, allowing the operation control parts to simultaneously execute the same operation and finding out the majority of respective operation results by an I/O control part. CONSTITUTION:Three operation control parts 15 each of which consists of a memory 1, a CPU 2, a control circuit 7, and an FIFO 14 for storing output information are independently constituted. The I/O control part 21 is constituted of a reference signal generating circuit 5 for generating a reference signal 6 for simultaneously and periodically starting the three operation control parts 15, a CPU 18 and a selector circuit 17 for successively selecting the FIFOs 14 of the control parts 15. Since the three operation control parts 15 are independently driven by the reference signal 6, this computer has an effect capable of easily synchronizing plural data outputs and easily detecting and separating a generated error.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention eliminates computer errors.
The present invention relates to a computer that requires a fault-tolerant function that automatically eliminates it.

[0002]

2. Description of the Related Art FIG. 10 is a diagram showing a configuration example of a conventional computer according to the present invention. FIG. 11 is a timing chart showing the operating state.

In the figure, 1 is a memory for storing a program, 2a, 2b and 2c are CPUs for executing operations, 3 is a clock generation circuit for supplying operation clocks of the CPUs 2a, 2b and 2c, 4 is a clock signal, and 5 is a clock signal. CPU 2a, 2
Reference signal generating circuit for generating periodic operation timings of b and 2c, 6 is a reference signal serving as a reference for the periodic processing of the CPUs 2a, 2b and 2c, and 7 is a CPU 2 based on the reference signal 6.
a control circuit for deciding whether or not to execute the processing of a, 2b, 2c,
Reference numeral 8 is a ready signal output from the control circuit 7 to the CPUs 2a, 2b and 2c, and 9a, 9b and 9c are CPUs 2a and 2c.
Output buses from b and 2c, 10 are output buses 9a and 9b,
9c is a majority decision circuit for taking a majority decision of information, 11 is an output circuit, and 12 is output data. 13a, 13b, 13c
Is a processing end signal which informs the control circuit 7 that the processing of the CPUs 2a, 2b, 2c has been completed.

In FIG. 11, T1 indicates the period of the reference signal 6 and T2 indicates the period of the ready signal 8. The period of T2 is the processing period of the CPUs 2a, 2b, 2c.

Next, the operation will be described. As shown in FIG. 11, when the reference signal 6 is generated at t1, the ready signal 8 is output to the CPUs 2a, 2b and 2c from t2. CPU
2a, 2b, 2c simultaneously start processing based on the ready signal 8. When the processing is started, the CPU 2a,
2b and 2c execute the same processing while loading the processing program from the memory 1 in synchronization with the clock signal 4.
The output information to the output circuit 11 being processed is output to the output bus 9a,
It is output to the majority circuit 10 via 9b and 9c.

The CPUs 2a, 2b and 2c use the clock signal 4
The output information is output at the timing of the same clock signal 4 because it is synchronized with the same program and is the same program.
b and 9c. In FIG. 11, t3 to t
4 shows the case where the output buses 9a, 9b, 9c output the same information, and the output data 12 at this time outputs the same information as the information of the output buses 9a, 9b, 9c.

From t4 to t5, the case where the CPU 2c generates an error is shown. The majority circuit 10 excludes the information of the output bus 9c in error, and outputs the same output information of the output buses 9a and 9b as the output data 12.

When the processing of the CPUs 2a, 2b, 2c is completed, processing end signals 13a, 13b, 13c are output to the control circuit 7. The control circuit 7 controls the processing end signals 13a, 13
When any two of b and 13c are input, the ready signal 8 is stopped at t6.

Incidentally, when the ready signal 8 is other than T2,
The CPUs 2a, 2b, 2c enter the reset state, and with the next reference signal 6, the processing is executed from the initialized state.

As described above, the CPU 2 for each reference signal 6
a, 2b, 2c are initialized, and when a ready signal 8 is generated, a program is loaded from the same memory 1 in synchronization with the clock and executed, and the processing result is majority-determined by the majority-decision circuit 10. Even if one of them runs out of control, the runaway is suppressed within the cycle so that incorrect output information is not output to the output circuit 11.

[0011]

However, recently CPU2
The processing speeds of a, 2b and 2c are improved, the clock signal 4 is increased in speed, and it has become difficult to synchronize the majority circuit 10 due to variations in the delay time of the circuit, and the program of the memory 1 is shared. Therefore, there is a problem that an error in the memory 1 causes an error in all the processes of the CPUs 2a, 2b, 2c.

The present invention has been made in order to solve the above-mentioned problems, and three operation control units each composed of a memory, a CPU and the like are independently configured, and these are independently operated to output the output information. A method of storing each in a first-in / first-out memory arranged in each arithmetic control unit, calling them sequentially by an input / output control unit having a CPU separately configured, and taking a majority decision by a CPU program of the input / output control unit The CPUs 2a, 2
It is intended to facilitate the synchronization of b and 2c and to prevent the error of the memory 1 from affecting the errors of all the CPUs 2a, 2b and 2c.

The output information of the three sets of independent arithmetic control units can be accessed at random addresses from the input / output control units separately configured, and simultaneously or asynchronously from the CPUs of the arithmetic control unit and the input / output control units. The purpose is to do so.

Further, the CPU of the input / output control unit simultaneously reads the output information of the three sets of arithmetic control units, and before inputting this output information to the CPU of the input / output control unit, a majority decision is taken by the majority decision circuit to cause an error. Is intended to be exclusive.

Further, the output information of the first-in / first-out memories of the three sets of operation control units are simultaneously read by the output control circuit which generates a read signal at constant intervals, and the read three sets of output information are majority circuits. The purpose is to exclude the error and output the result directly to the output circuit 11.

Mutual arithmetic control units read the arithmetic results of the three arithmetic control units, compare them with their own results to check for errors, and output the results as an error signal to the input / output control unit. The purpose is to identify the arithmetic control unit in which an error has occurred and to exclude the error so that the error can be output to the output circuit 11.

[0017]

A computer according to the present invention includes a memory 1 for storing a program and a C for executing an operation.
Control circuits 7 and C for controlling the operations of the PU 2a and the CPU 2a
The first-in / first-out memory for storing the output information from the PU 2a and the clock generating circuit 3 for supplying the operation clock to the CPU 2a are independently configured in three sets as one set of operation control section, and further, these three sets of operation control are provided. A reference signal generation circuit 5 for supplying a reference signal 6 for simultaneously and periodically executing the units, a selection circuit for sequentially selecting a first-in / first-out memory in which output information of each operation control unit is stored, and a selection circuit CP that reads output information from the first-in / first-out memory selected in step 3 and executes the majority decision of the three sets of output information by a program
U, a memory that stores a program that executes this majority processing, a clock generation circuit 3 that supplies a clock for operating the CPU, and an output circuit 11 that outputs data to an external device are configured as a set of input / output control units. From the reference signal generation circuit 5 of this input / output control unit to the three sets of arithmetic control units, the reference signal 6
Is generated and the program processing is executed at the same time, and the three sets of arithmetic control units complete the program processing, and the output information is sequentially input while switching the selection circuit from the first-in / first-out memory of the three sets of arithmetic control units. The CPU of the output control unit reads the output data, outputs the output information to an external device after a majority decision is made by the CPU program.

Further, the 2-port RAM is configured as a memory for storing the output information of each of the three sets of arithmetic control units, and the arithmetic control unit and the input / output control unit are set to arbitrary timings of the respective operation programs. The address is accessed.

Further, the output information from the first-in / first-out memory of the three sets of arithmetic control units is read at the same time according to the instruction of the CPU of the input / output control unit, and this output information is input after the majority decision is made by the majority decision circuit. The data is transferred to the CPU of the output control unit.

Further, an output control circuit comprising a counting circuit and a pulse generation circuit is formed in the input / output control section, and the output information of the first-in / first-out memory of the three sets of arithmetic control sections is continuously supplied at a constant cycle. A read signal to be read is generated, and output information from the three sets of first-in / first-out memories is simultaneously read by this read signal.
After the majority decision is made by the majority decision circuit, it is directly output to the output circuit 11.

The output information of the first-in / first-out memories of the three sets of arithmetic control units 1 to 3 is calculated by the arithmetic control unit 2 for the arithmetic control unit 1 and the arithmetic control unit 3 for the arithmetic control unit 2. Regarding the control unit 3, the arithmetic control unit 1 takes in each of them, compares them with its own output information, and transfers the result to an error discrimination circuit. If the arithmetic control units 1 and 2 indicate an error, the arithmetic control unit 1 However, when the arithmetic control units 2 and 3 indicate an error, the arithmetic control unit 2 causes the arithmetic control unit 3 to
When 1 and 1 indicate an error, the arithmetic control unit 3 determines that there is an error, selects the arithmetic control unit that has output the correct output information, and outputs it to the external device.

[0022]

The three sets of operation control units that operate independently as described above and the input / output control unit that manages the operation results of these three sets are arranged, and output information is mutually provided by using a first-in / first-out memory. By how to transfer
The timing of the high-speed CPU acts not only by the clock signal 4 but by the reference signal 6, and
Since the memory 1 for storing the program is independently arranged in the arithmetic control unit, even if an error occurs in one memory 1, the error output information to the output circuit 11 is prevented from being output.

By using the 2-port RAM as the output control storage memory of the three sets of arithmetic control units, the CPUs of the arithmetic control unit and the input / output control unit output output information to or from arbitrary addresses. Can be read.

Further, the output information of the three sets of arithmetic control units is transferred to the CPU of the input / output control unit after the majority vote is taken by the majority circuit, so that the CPU of the input / output control unit is
No need for majority processing in.

The output information stored in the first-in / first-out memories of the three sets of arithmetic control units is continuously read at a constant cycle by using the read signals generated from the counting circuit and the pulse generating circuit of the output control circuit. The output information after the majority vote is directly output from the majority vote circuit to the output circuit 11 by simultaneously reading out and inputting it to the majority vote circuit.

Further, the output information of the three sets of arithmetic control units are mutually captured, the captured output information is compared with its own output information, and an error signal is generated in the input / output control unit. The input / output control unit identifies the arithmetic control unit in which an error has occurred based on an error signal from the unit, and operates so that the arithmetic control unit can be excluded.

[0027]

【Example】

Embodiment 1 FIG. 1 shows a configuration example of a computer which is an embodiment of the present invention. FIG. 2 is a timing chart showing the operating state.

In the figure, 1 to 12 are exactly the same as the above-mentioned conventional example. 14a, 14b and 14c are CPU2
It is a first-in first-out memory (FIFO) that sequentially stores output information from a, 2b, and 2c.
The FIFOs 14a, 14b, 14c are connected to the output buses 9a, 9
The output information written from b and 9c is stored in order from the head address without addressing, and when there is a read request, the output information written first, that is, the output information stored in order from the head address is output. It has a function to go. Therefore, although output information cannot be read from a random address, there is an advantage that the read time can be shortened because only the read signal is required. 15a, 15b, 15
Reference numeral c is an arithmetic control unit, which has exactly the same circuit configuration. 1
Reference numeral 6 denotes a driver for transferring the reference signal 6 to the control circuit 7 formed in each of the arithmetic control units 15a, 15b, 15c, and 17
Is a selection circuit for selecting which one of the FIFOs 14a, 14b, 14c is to be selected, and 18 is a FIFO 14a, a FIFO 14b, a FIFO 14c while switching the selection circuit 17.
Output information in the order of 1) and majority processing and output circuit 1
1 is a CPU that outputs output information, 19 is a memory that stores a control program for the CPU 18, and 20 is a reference signal for the CPU 18. The reference signal 20 is generated with a certain delay time within each generation cycle of the reference signal 6. This delay time is preset in the reference signal generation circuit 5 in accordance with the end time of the processing time of the CPUs 2a, 2b, 2c. Reference numeral 21 is an input / output control unit.

As described above, according to the configuration of the present invention, the arithmetic processing unit 15 is provided in a portion where an error such as numerical operation cannot be tolerated.
This is a method in which three sets of the same circuits a, 15b, and 15c are configured, and the output information is output as the output data 12 while being controlled by the input / output control unit 21.

Next, the operation will be described. A reference signal 6 is periodically generated from the reference signal generation circuit 5 as t1 and t8. The reference signal 6 is output to each control circuit 7 of the arithmetic control units 15a, 15b, 15c via the driver 16. Each control circuit 7 outputs a ready signal 8 to each of the CPUs 2a, 2b, 2c as in the operation of the conventional computer.
As a result, each of the CPUs 2a, 2b, 2c independently starts the processing while independently reading the program from the memory 1 arranged exclusively for each. CPUs 2a, 2b, 2c
The above processing requires time T3, T4, and T5, respectively. This time difference is caused by the phase difference between the clock signals 4. The CPUs 2a, 2b, 2c store output information in the FIFOs 14a, 14b, 14c in the course of processing. When the processing is completed, the CPUs 2a, 2b, 2c output the processing end signals 13a, 13b, 13c to the control circuits 7 and enter the stopped state.

At t7 after the period of T6, the reference signal 20 is output to the CPU 18. The CPU 18 uses the reference signal 20
As a start signal, this process is performed while reading output information from the memory 19 and reading a program having a majority decision process and an output process function to an external device. Figure 2
At T7, the selection circuit 17 is set in the arithmetic control unit 15a and F
The processing period for reading the output information from the IFO 14a in the written order and storing the result in the memory 19 is shown. T8 indicates a processing period in which the selection circuit 17 is switched to the arithmetic control unit 15b and output information is similarly read from the FIFO 14b. T9 indicates a processing period in which the selection circuit 17 is switched to the arithmetic control unit 15c and output information is similarly read from the FIFO 14c.

As described above, the FIFOs 14a, 14b, 1
After reading the output information of 4c, the CPU operates in the period of T10.
18 determines a majority of the three sets of output information stored in the memory 19. After the majority vote processing, the CPU 18 outputs the output data 12 to the external device via the output circuit 11 during the period T11.

In this way, the completely independent arithmetic control unit 15
a, 15b, 15c are synchronized with the start of processing by the reference signal 6 from the input / output control unit 21, and the output information is F
This is a method of synchronizing by the IFOs 14a, 14b, 14c.

Second Embodiment In the above first embodiment, the independent arithmetic control units 15a, 15b,
Although the problem of the conventional clock synchronization system can be solved by arranging 15c and the input / output control unit 21, the output information of the arithmetic control units 15a, 15b, 15c and the input / output control unit 21 can be solved in this embodiment. CPUs 2a, 2
The output information can be simultaneously written and read from each of b and 2c and the CPU 18. The basic operation is the same as that of the first embodiment.

FIG. 3 is a diagram showing an example of the configuration of a computer according to this embodiment. In the figure, reference numeral 22 indicates the address information output from the CPU 18 in the arithmetic control units 15a, 15b,
A driver for transferring to 15c, 23a, 23b, 23c are address signals, and 24a, 24b, 24c are 2-port RA
It is M. The 2-port RAMs 24a, 24b, 24c are
It is a memory having a function of simultaneously writing and reading from different addresses in the same RAM from the CPU 2a and the CPU 18 and accessing a random address by addressing.

Next, the operation will be described. The operation based on the reference signal 6 is basically the same as that of the first embodiment. Therefore,
The timing chart is similar to that of FIG. The difference is that the output information can be fetched while designating an arbitrary address when reading the output information from the 2-port RAMs 24a, 24b, 24c in the periods T7, T8, T9 of FIG. As a result, the address signals 23a,
Although the address setting times of 23b and 23c are added, there is no need to read output information that is unnecessary depending on the processing program, and the CPUs 2a, 2b, and
The parallel reading by the CPU 18 is possible even before the processing of 2c is completed.

Embodiment 3 FIG. 4 shows an example of the configuration of a computer which is an embodiment of the present invention. FIG. 5 is a timing chart showing the operating state.

In the figure, 25 is a FIFO 14a, 14b, 1
4c is a majority circuit for executing a majority vote of output information from 4c.

The basic operation is the same as that of the first embodiment, but in the first embodiment, the process in which the majority decision processing of the output information of the FIFOs 14a, 14b and 14c is performed by the program of the CPU 18 is a pre-stage to be taken into the CPU 18. Is performed by the majority decision circuit 25, the CPU 18 reads the output information after the majority decision, and outputs it to the output circuit 11.

Next, the operation will be described. The CPU 2a, 2b, 2c starts processing by the reference signal 6. Each processing period is T3, T4, T5 shown in FIG. This time difference regarding the execution of the same processing is caused by the arithmetic circuit units 15a, 15b,
It is generated by the phase difference of the clock signal 4 inside 15c.

When the execution of each of the arithmetic circuit units 15a, 15b, 15c is completed, the reference signal 20 is output to the CPU 18 at t7, and the CPU 18 causes the FIFO 14 to operate during the period of T12.
Output information is read simultaneously from a, 14b, and 14c. F
The information simultaneously output from the IFOs 14a, 14b, and 14c is subjected to majority processing by the majority circuit 25, and the result is read by the CPU 18 and output from the output circuit 11. The period of T13 is the output period by the program. In this way, by causing the majority decision circuit 25 to perform the majority decision process in the CPU 18, the CPU
It is possible to omit the program processing time for the 18 majority votes.

Embodiment 4 FIG. 6 shows an example of the configuration of a computer which is an embodiment of the present invention. FIG. 7 is a timing chart showing the operating state.

In the first to third embodiments, the input / output control unit 21 has a C
Although the PU 18 is arranged, in this embodiment,
A circuit having a direct memory access function is arranged.

In the figure, 26 is a FIFO 14a, 14
This is an output control circuit for simultaneously outputting the output information of b and 14c to the majority circuit 25 in a fixed cycle. 27 is a counting circuit for counting a fixed period, 28 is a pulse generation circuit for outputting a pulse to the FIFOs 14a, 14b, 14c when the counting circuit 27 reaches a specified value, 29 is a read pulse, and 30 is a read pulse 29 for the FIFO 14a, 14b. , 31c, 31b, 31c are FIFOs
It is a read signal to 14a, 14b and 14c.

Next, the operation will be described. When the reference signal 6 is generated, the CPUs 2a, 2b, 2c cause T3, T4, T
The process is executed at 5. When the processing is completed, the reference signal 20 is output to the output control circuit 26 at t7. Output control circuit 2
When the reference signal 20 is received by the counter 6, the counting circuit 27 outputs t9.
The counting is started from, and the generation of the read pulse 29 is instructed to the pulse generation circuit 28 in the cycle of T14 in the order of t9 and t10. The read pulse 29 is passed through the driver 30 as read signals 31a, 31b, 31c to the FIFO 14
It is simultaneously output to a, 14b, and 14c.

Each time the read signals 31a, 31b, 31c are generated, the output information is output from the FIFOs 14a, 14b, 14c simultaneously and sequentially from the head address. This output information is input to the majority decision circuit 25, is subjected to a majority decision, and is then directly output to the output circuit 11. Read signal 31
The number of occurrences of a, 31b and 31c is the same as that of the FIFO 14a and 14
It is set to the quantity of output information of b and 14c.

Embodiment 5 FIG. 8 shows an example of the configuration of a computer which is an embodiment of the present invention. FIG. 9 is a timing chart showing the operating state.

In the embodiment of the present invention, the input / output control unit 21 executes the majority decision of the output information of the operation control units 15a, 15b, 15c in the first to fourth embodiments, whereas the operation control units 15a, 15b, 15b, 15c is a method of discriminating whether or not there is a difference in output information between the other party and itself by comparing the output information of itself with each other in units of two sets.

In the figure, 32a, 32b, and 32c are error signals indicating the result of mutual check, and 33 is any CP.
An error identification circuit for identifying whether U2a, 2b, 2c has generated an error, and 34 is an error identification signal. Reference numeral 35 is a reference signal for instructing the CPU 2a, 2b, 2c to end the mutual diagnostic processing, and 36 is a reference signal generation circuit for generating the reference signals 6, 20, 35.

Next, the operation will be described. When the reference signal 6 is generated from the reference signal generation circuit 36, the CPUs 2a, 2
b and 2c start processing. Each processing period is T3
T4 and T5. When each processing is completed, the reference signal 20 is generated after the period of T6. This reference signal 20 is sent to the CPU 2
When a, 2b, and 2c accept the FIFO during the period of T15.
Mutual diagnosis of 14a, 14b, 14c is performed. That is, the CPU 2a and its output information and the FIFO 14c
The CPU 2b outputs its own output information and the FIFO 14a,
The CPU 2c checks its own output information and the FIFO 14b. The result is the error signals 32a, 32b, 32.
It is output to c and is output to the error identification circuit 33. The error identification circuit 33 confirms the presence or absence of an error, and if there is, identifies which CPU 2a, 2b, 2c, and instructs the selection circuit 17 by the error identification signal 34 to indicate the normal CPU 2a, 2b, 2c. After this, the reference signal generation circuit 3
6 outputs the reference signal 35 at t12, and the output circuit 1 outputs the error-free CPU 2a, 2b, 2c to T16 during the period from T16.
Output information is output to 1.

The error identification and the setting of the selection circuit 17 are as follows.
This is done as follows.

When all the error signals 32a, 32b, 32c of the CPUs 2a, 2b, 2c indicate no error,
The output information of the CPU 2a is selected. CPU 2a, 2b
When the error signals 32a and 32b indicate that there is an error, the CPU 2a is in error and the CPU 2b is selected. C
When the error signals 32b and 32c of the PUs 2b and 2c indicate that there is an error, the CPU 2b is in error and the CPU 2c is selected. Error signals 32c, 3 of CPU 2c, 2a
When 2a indicates that there is an error, the CPU 2c is in error and the CPU 2a is selected and output to the output circuit 11.
FIG. 9 shows an example when the CPU 2a is determined to be correct.

The error signals 32a, 32b, 32c
Of all CPUs 2a, 2
This is because b and 2c simultaneously generate an error and the output to the external device is stopped.

[0054]

Since the present invention is constructed as described above, it has the following effects.

The FIFOs 14a, 14b, and 14c having the first-in / first-out function, which are independently operated as the arithmetic control units 15a, 15b, and 15c, can store the output information obtained in the course of this processing in order from the head address.
CPU of the input / output control unit 21 stored in
By sequentially reading this output information and outputting the result obtained by the majority decision by the program to the output circuit 11, it is possible to easily synchronize the timing of the high-speed CPUs and to control a set of arithmetic operations. Parts 15a, 15
Even if an error occurs in b and 15c, another calculation control unit 15
This has the effect of preventing error propagation to a, 15b, and 15c.

Further, the arithmetic control units 15a, 15b, 15c
The output information storage memory is a 2-port RAM 24a, 24
b and 24c, CPU2a, 2b, 2c and C
The output information can be simultaneously accessed from the PU 18, and the output information is calculated at a random address.
The effect of being able to take in from a, 15b, and 15c is produced.

Further, the arithmetic control units 15a, 15b, 15c
The majority of the output information of the CP via the majority circuit 25
By adopting the method of inputting into U18, it is possible to eliminate the need for the majority processing of the program.

Further, the arithmetic control units 15a, 15b, 15c
The output information from the output to the input / output control unit 21 is read at the same time by the read signal output at a constant cycle,
By adopting a method in which the majority decision circuit 25 of the output control circuit 26 makes a majority decision, there is an effect that the majority decision circuit 25 can directly output to the external device through the output circuit 11.

Further, the arithmetic control units 15a, 15b, 15c
The majority of the output information from the arithmetic control units 15a, 15b,
By using the method of mutually checking two sets of 15c, the error identification circuit 33 of the input / output control circuit 21 can easily determine which of the arithmetic control units 15a, 15b, and 15c has an error, and The effect of being able to exclude is produced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of a computer that is Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a timing chart of the computer that is Embodiment 1 of the present invention.

FIG. 3 is a diagram showing a configuration example of a computer that is Embodiment 2 of the present invention.

FIG. 4 is a diagram showing a configuration example of a computer that is Embodiment 3 of the present invention.

FIG. 5 is a diagram showing a timing chart of a computer that is Embodiment 3 of the present invention.

FIG. 6 is a diagram showing a configuration example of a computer that is Embodiment 4 of the present invention.

FIG. 7 is a diagram showing a timing chart of a computer that is Embodiment 4 of the present invention.

FIG. 8 is a diagram showing a configuration example of a computer that is Embodiment 5 of the present invention.

FIG. 9 is a diagram showing a timing chart of a computer that is Embodiment 5 of the present invention.

FIG. 10 is a diagram showing a configuration example of a conventional computer.

FIG. 11 is a diagram showing a timing chart of a conventional computer.

[Explanation of symbols]

 1 Memory 2a CPU 2b CPU 2c CPU 3 Clock generation circuit 5 Reference signal generation circuit 6 Reference signal 7 Control circuit 8 Ready signal 10 Majority decision circuit 11 Output circuit 14a FIFO 14b FIFO 14c FIFO 15a Operation control section 15b Operation control section 15c Operation control section 17 Selection Circuit 18 CPU 19 Memory 20 Reference Signal 21 Input / Output Control Unit 24a 2 Port RAM 24b 2 Port RAM 24c 2 Port RAM 25 Majority Decision Circuit 26 Output Control Circuit 27 Counting Circuit 28 Pulse Generation Circuit 31a Read Signal 31b Read Signal 31c Read Signal 33 error identification circuit 34 error identification signal 35 reference signal 36 reference signal generation circuit

Claims (5)

[Claims] 1. A memory for storing a program, a CPU for executing an operation, a control circuit for controlling execution and stop of the CPU, a first-in / first-out memory for storing output information from the CPU in order from a head address, C
Three sets of operation control units that operate at independent timings and are composed of a clock generation circuit that supplies an operation clock to the PU, and a reference signal generator that supplies a reference signal that causes the three sets of operation control units to be executed simultaneously and periodically. Circuit, a selection circuit for sequentially selecting the first-in / first-out memory in which the output information of the three sets of arithmetic control units is stored,
A CPU that reads output information from the first-in / first-out memory selected by the selection circuit and executes a majority decision process of three sets of output information by a program, a memory that stores a program that executes the majority decision process, and the CPU
Of the input / output control section comprising a clock generation circuit for supplying the operation clock of the above and an output circuit for outputting the output information after the majority decision to an external device, and three sets of operations are performed in synchronization with the reference signal from the reference signal generation circuit. Let the control units run simultaneously,
After the 3 sets of arithmetic and control units have completed the processing of the program, 3
The output information is read from the first-in / first-out memory of the set of arithmetic control units by the input / output control CPU in order while switching the selection circuit, and after the majority decision is made by the program, it is output from the output circuit of the input / output control unit to the external device. A calculator characterized by: 2. A memory for storing output information from the CPU of the arithmetic control unit can be independently accessed from both the CPU of the arithmetic control unit and the CPU of the input / output control unit at an arbitrary timing and at an arbitrary designated address. The computer according to claim 1, wherein the computer comprises a two-port RAM. 3. A CPU of the input / output control unit, wherein the input / output control unit comprises a majority-decision circuit for majority-determining output information from the first-in / first-out memories of the three sets of arithmetic control units.
According to the instruction, the output information of the three sets of first-in / first-out memories are read at the same time, the majority decision circuit takes the majority decision, and the CPU of the input / output control section reads the result and outputs it to the external device. The computer according to claim 1. 4. A counting circuit and a pulse generating circuit for generating read signals for reading out output information stored in first-in / first-out memories of three sets of arithmetic control units in the input / output control unit simultaneously and continuously at fixed intervals. An output control circuit consisting of a majority decision circuit for taking a majority decision of the read three sets of output information, and the output information from the first-in first-out memory is directly transferred from the majority decision circuit to the output circuit and output to an external device. A computer characterized by being able to do it. 5. The output information of each of the first-in / first-out memories of the three sets of arithmetic control units 1 to 3 is output by the arithmetic control unit 2 for the arithmetic control unit 1 and the arithmetic control unit 3 for the arithmetic control unit 2. As for the arithmetic control unit 3, the arithmetic control unit 1 takes in each, and compares the output information of itself with the output information of the other arithmetic control unit that has been taken in. If there is an error, each arithmetic control unit individually The arithmetic control units 1 to 3 are configured so that a comparison error signal can be output to the input / output control unit. Further, when the arithmetic control units 1 and 2 indicate that there is a comparison error in the input / output control unit, the arithmetic control unit 1 is Error identification for identifying the arithmetic control unit 2 when the arithmetic control units 2 and 3 indicate that there is a comparison error, and for identifying the arithmetic control unit 3 when the arithmetic control units 3 and 1 indicate that there is a comparison processing error Circuit and error discrimination circuit A computer having a selection circuit configured to select correct output information.