JPH03265952A - Picture display controller - Google Patents

Abstract

PURPOSE:To shorten the total starting time of a computer system by ordering a CPU to set only a check start address, an end address, the write data, and a check mode respectively when the system starts. CONSTITUTION:A write data control means 14 outputs the checking write data WD into a picture data storage 18 based on a write control signal Sc and a write grant signal Se. A read data control means 16 inputs the read data RD received from the storage 18 based on a read control signal Sd and a read grant signal Sf. Thus, the storage 18 can be checked in a short time in terms of hardware despite a large capacity is given to the storage device (video RAM) 18. Thus, the control means (CPU) 16 does not need to exclusively check the storage 18 and can process other data. Then the total starting time is shortened for a computer system.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 6) Problems to be solved by the invention! ! (Figure 7) Means for solving the problem (Figure 1) Working examples (Figures 2 to 5) Effects of the invention [Summary] Input of video RAM in an image display control device, especially a computer image processing system Regarding the improvement of the check function of the display control device that controls the output, the check process of the video RAM does not depend solely on the CPU, but is performed in a short time using hardware, thereby reducing the total startup time of the computer system. For the purpose of shortening the time, an address control means, an address generation means, a write data control means, a read data control means, and an input/output control means are connected to a bus line, and a control signal generation means is connected to the address control means. means, the address control means comprising:
outputting a control start signal write permission signal and a read permission signal based on the write/read control signal and the control end signal;
The control signal generation means inputs the control activation signal and outputs an address generation control signal, a write control signal, and a read control signal, and the address generation means generates an image based on the control activation signal and the address generation control signal. The write data control means generates a check address and a control end signal for the data storage device, outputs check write data to the image data storage device based on the write control signal and the write permission signal, and outputs the check write data to the image data storage device. The data control means inputs read data from the image data storage device based on a read control signal and a read permission signal.

[Field of Industrial Application] The present invention relates to an image display control device, and more specifically, to an improvement in the checking function of a display control device that controls input/output of a video RAM in a computer image processing system. .

In recent years, with the demand for higher resolution and multicolor computer image processing systems, the capacity of video RAM (memory that can be read and written at any time exclusively for video data) used for image processing in a single computer system has been increased. ing.

According to this device, despite the increased capacity of the video RAM, the CPU (central processing unit) checks the video RAM based on a check processing program when the computer system is started. For this reason, there is a problem in that it takes a lot of time to check, the total startup time of the computer system becomes long, and image processing cannot be started early.

Therefore, there is a need for a device that can check large-capacity video RAM in a short time using hardware without relying solely on the CPU, thereby shortening the total startup time of the computer system. There is.

[Conventional technology]

FIG. 3 is a configuration diagram of a conventional image display control device.

In the figure, the display control device in the computer image processing system includes CPU1. Arbitration circuit 2 Display control circuit 3.
1st. Second Haspan 2F Circuit 4.5. It controls input/output of write data/read data of the video RAM 6.

The video RAM 6 temporarily stores image data necessary for displaying images on a display device connected to the system, and is checked by the CPU 1 to see if writing/reading operations are normal when the system is started. Ru.

FIG. 7 shows a flowchart of a CPU RAM check process according to a conventional example.

In the figure, for example, in the case of a check processing program that reads memory contents from addresses #1O00 to #2000 and compares the values, first, check request signals Sl and S3 are sent from the CPU 1 and the display control circuit 3 to the arbitration circuit 2.
When the circuit 2 outputs the check permission signal S2,
34 are returned respectively. As a result, step P1
Set the start address with . At this time, circuit 2
to the first and second pass buffer circuits 4.5 and 4.5, respectively. S6 is output. As a result, the check write data WD is written to the video RAM 6.

Next, in step P2, data is read from the video RAM 6. At this time, similarly to the write operation, the first . A buffer control signal 35.36 is output to the second path buffer circuit 4.5. As a result, read data RD is input to both buffer circuits 4 and 5.

Next, in step P3, comparison processing with expected value data is performed. At this time, if the write data WD and read data RD do not match (NO), the process moves to step P4 and error handling is performed.

Further, if both data WD and RD match (YES), the process moves to step P5.

In step P5, a video RAM check process for the next address #1001 and subsequent addresses is performed.

Next, in step P6, it is determined whether the next address is #2000. At this time, the address is #20
If the value does not reach 00 (NO), the process returns to step P5. Also, if the address reaches 12000 (YES)
Then, the process moves to step P7.

In step P7, video RAM check processing is performed for the next address #2001 and onwards.

As a result, all addresses #1000X6 steps 60
The video RAM 6 is checked through the processing flow of step 00.

[Problem to be solved by the invention]

By the way, according to the conventional example of checking the video RAM 6, the CPUI writes check write data WD based on a system check processing program, and then judges whether or not the data WD can be read. .

Therefore, the CPU is solely responsible for checking the video RAM 6. This means that more and more time must be spent on the checking process as the capacity of video RAM increases with the demand for higher resolution and multicolor computer graphics.

As a result, there is a problem that the total startup time of the computer system becomes long and image processing cannot be started early.

The present invention was created in view of the problems of the conventional example, and allows the checking process of the video RAM to be performed in a short time using hardware, without relying solely on the CPU, to completely boot the computer system. Image display control bag that makes it possible to shorten start-up time! The purpose is to provide.

[Means to solve the problem]

FIG. 1 shows a principle diagram of an image display control device according to the present invention.

The device includes address control means 12. connected to bus line If. Address generation means 13. Write data control means 1
4. Read data control means 15 and input/output control means 16
and a control signal generating means 17 connected to the address control means 12, the address control means 12 comprising:
A control activation signal Sa, a write permission signal Se and a read permission signal Sf are output based on the write/read control signal R/-9 control end signal Sg, and the control signal generating means 17 inputs the control activation signal Sa. The address generation means 13 outputs an address generation control signal Sb, a write control signal Sc, and a read control signal Sd, and the address generation means 13 generates a check address of the image data storage device 18 based on the control start signal Sa and the address generation control signal sb. ADD and control end signal Sg are generated, and the write data control means 14 outputs check write data WD to the image data storage device 18 based on the write control signal Sc and write permission signal Se, and outputs the check write data WD to the image data storage device 18, The control means 16 inputs the read data RD from the image data storage device 18 based on the read control signal Sd and the read permission signal S', thereby achieving the above object.

[For production]

According to the invention, address control means 12.7 address generation means 13. Write data control means 14.Read data control means 15. Input/output control means 16 and control signal generation means 17 are provided.

For example, when the input/output control means 16 gives the write/read control signal R/- to the address control means 12, the control activation signal Sa is output from the address control means 12 to the address ordering means]3 and the control signal generation means 17. , a write permission signal Se is output to the write data control means 14, and a read permission signal Sf is output to the read data control means 15.

As a result, the control signal generation means 17 generates an address generation control signal Sb, a write control signal Sc, and a read control signal Sd based on the control activation signal Sa, and the address generation control signal sb is outputted to the address generation means 13. ,
The write control signal Sc is output to the write data control means 14, and the read control signal Sd is output to the read data control means 15.
is output to.

Further, in the address generation means 13, the input/output control means 16
The check address ADD is output to the image data storage device 18 by activating the address specified by , the control activation signal Sa, the address generation control signal Sb, and the write control signal Sc.

Furthermore, in the write data control means 14, by activating the write control signal Sc and the write permission signal Se,
Check write data WD is image data storage device 1
8 is output. This completes the write operation.

Next, in the read data control means 16, the read control signal Sd and the read permission signal Sf are activated, so that the read data RD is read from the image data storage device 18, and the check write data WD and the data RD are Comparison and verification processing is performed. At the end of these check processes, a control end signal Sg is output from the address generation means 13 to the address control means 12.

For this reason, image data storage devices (video RA
M) Even if the capacity of the image data storage device 13 is increased, it is possible to check the image data storage device 18 in a shorter time using hardware compared to the software check processing performed by the CPU as in the conventional example. can.

As a result, the input/output control means (CPU) 16 is no longer exclusively responsible for checking the image data storage device 18 as in the conventional example, and can perform other data processing. As a result, the total startup time of the computer system can be shortened, and image processing can be started at an early stage.

[Example] Next, an example of the present invention will be described with reference to the drawings.

2 to 5 are explanatory diagrams of an image display control device according to an embodiment of the present invention, and FIG. 2 shows a configuration diagram thereof.

In the figure, reference numeral 22 denotes an address control circuit which is an embodiment of the address control means 12, and which sets the check mode, controls the read/write setting register 22a, the control end signal Sg, and the write/read control signal RNO. A logical operation circuit 22b performs a logical operation to determine the end of the check process or the continuation of the check process, a check end bit generation circuit 22c generates a bit indicating the end of the write process or read process, and a check start bit generation circuit 22d that generates a bit indicating a start;
A bus request control circuit 22e that outputs a startup control signal Sa and a bus request signal S7 based on the system clock, a bus management circuit 22f that manages the bus line 21, and a video RAM.
The refresh request circuit 22g requests 28 refresh operations.

Note that the check mode will be explained with reference to FIG.

Reference numeral 23 denotes an address generation circuit which is an embodiment of the address generation means 13, and an end address register 23 that sets a check end address based on the activation control signal Sa.
a, a start address register 23b for setting a check start address, an address counter 23C for sequentially counting up the address for chinick ADD, and a first register for comparing the address counter value with the check end address and outputting a control end signal Sg. A temporary address register 23e temporarily stores the check address ADD, and a first output buffer circuit 23f outputs the check address ADD to the video RAM 28 based on the address generation control signal sb.

24 is a write data control circuit which is an embodiment of the write data control means 14, and is a write data control circuit for checking write data WD.
AND of the write data register 24a that sets the write data register 24a, the selector bit generation circuit 24b that generates the selection bit, the selector circuit 24c that selects the address counter value or check write data WD, the write control signal Sc and the write permission signal Se. It consists of an AND logic circuit 24d that performs logical operation processing, and a 20th output buffer circuit 24e that outputs check write data WD and the like based on a match signal from the circuit 24d.

Reference numeral 25 denotes a read data control circuit which is an embodiment of the read data control means 15, and includes an input buffer circuit 25a that takes in the read data RD based on the read permission signal Sr.
, a latch circuit 25b that latches the data RD based on the read control signal Sd, a second comparison circuit 25c that compares data WD during writing with data RD during read, and a read circuit 25c that temporarily registers the read data RD. It consists of a read register 25d, an error bit generation circuit 25e that generates an error bit, and an expected value register 25f that temporarily registers data WD during writing.

26 is a CPU (central processing unit) which is an embodiment of the input/output control means 16, and the address control circuit 22. Address generation circuit 23, write data #
It is connected to the control circuit 24 and the read data control circuit 25.

Reference numeral 27 denotes a control signal generation circuit which is an embodiment of the control signal generation means 17, which includes a first timing generation circuit 27a that generates an address generation control signal sb based on the activation control signal Sa, and a first timing generation circuit 27a that generates a write control signal SC. The second timing generation circuit 27b generates the read control signal Sc, and the third timing generation port 1lI27c generates the read control signal Sc.

Reference numeral 28 denotes a video RAM (memory that can be written/read at any time exclusively for video data), which is an example of the image data storage device 18, and temporarily stores image data necessary for displaying images on a display device in a computer image processing system. It is something.

Note that in order to optimize the image display processing, it is necessary to check whether the write/read operations are normal when the system is started.

3rd [1J(a) to (c) are time charts for explaining the check mode according to the embodiment of the present invention, and FIG.
a) shows the case where the read mode is set in the read/write setting register 22a.

In the figure, in the read mode, data RD is read out after the read permission signal Sf is activated, and the signal Sf
For example, when the control end signal Sg is inactivated, the control end signal Sg is activated in synchronization with the falling edge of the control end signal Sg, and a check end bit is generated.

In addition, (b) in the same figure shows the read/write setting register 22.
The case where the light mode is set to a is shown.

In the figure, in the write mode, data WD is written after the write enable signal Se is activated, and the signal Se
For example, when the control end signal Sg is inactivated, the control end signal Sg is activated in synchronization with the falling edge of the control end signal Sg, and a check end bit is generated.

Furthermore, the same figure (C) shows the read/write setting register 2.
The case where the read/write mode is set to 2a is shown.

In the figure, in the read/write mode, during the period when the write/read control signal R/W is activated, the write permission signal Se is activated, thereby writing data WD, and the read permission signal Sf is activated. When the signal R/- is inactivated, the control end signal Sg is activated and the check end bit is generated in synchronization with the falling edge of the signal R/-. .

These constitute an image display control device according to an embodiment of the present invention.

Next, the video RAM check processing operation in the read/write mode of the device will be explained.

First, the CPU 26 sets a check start bit, for example #1000, in the start address register 23b, and sets a check end bit #2 in the end address register 23b.
Set 000. Also, the write/read control signal R/
-activate. Next, read/write setting register 2
The read/write mode is set as the check mode in 2a.

Next, the selector pit generation port B24b selects either the address counter value or the value of the write data register 24a for the write data WD to the video RAM 2B.

Here, if we choose the address counter value,
Different write data WD is written to the video RAM 2B for each check address ADI), and each address ADI is written to the video RAM 2B.
It is possible to check whether DD is interfering.

Furthermore, if the value of the write data register 24a is selected, different write data WD is written to the video RAM 28 for each check address ADD,
It is possible to check whether the focus points of the same address ADD are interfering with each other.

The processing operations up to this point are related to the start of checking the video RAM 28 by the CPU 26, and subsequent processing operations are performed by hardware.

That is, when the check start bit generation time B22d of the address counter 22 is activated, the address generation circuit 2
The value set in the start address register 23d of No. 3 is loaded into the address counter 23c. The address counter 23c sequentially counts up the check address ADD based on the activation control signal Sa.

At this time, in the bus request control circuit 22e, the bus management circuit 2
2f, a request signal S7 indicating a request to use the bus line 21 is started to be generated.

The bus management circuit 22f determines whether there is an interrupt request for refresh processing in order to continue checking the video RAM 2B. This determination is made by arbitration processing between the request signal S7 and the request signal 310 from the refresh request circuit 22g.

Here, if there are both requests at the same time, refresh processing takes priority. This is to prevent the memory contents from being destroyed due to a delay in the refresh operation since a Guinami RAM is normally used as the video RAM 2B.

As a result, the bus request control circuit 22e receives the bus request control circuit 22e based on the permission signal S8 and the clock signal CLK from the bus management circuit 22f.
An activation control signal Sa is output from the control signal generation circuit 27 to the control signal generation circuit 27.

This activation control signal Sa is transmitted to the first timing generation circuit 27.
It is delayed in step a and output to the first output sofa circuit 23f as an address generation control signal sb. Furthermore, when the address generation control signal sb is activated, the check address ADD is input to the RAM 28 via the first output buffer circuit 23f.

Similarly, the second timing generation circuit 27b delays the signal Sa and outputs it to the AND logic circuit 24d as a write control signal Sc. Furthermore, the signal Sa is delayed by the third timing generation circuit 27c and the latch circuit 25
b as a read control signal Sd.

Along with the input processing of the check address ADD, the check write data WD is output to the RAM 2B.

That is, in the write data control circuit 24, the write enable signal Se from the read/write setting register 22a is
The write data WD selected by the selector circuit 24c from the second output buffer circuit 24e is outputted to the RAM 2B based on the AND logical operation result of the write control signal Sca from the second timing generation circuit 27b.

At this time, each time the address counter 23c counts up, the value of the counter and the value of the register 23d are compared by the first comparison circuit 23d. If there is a match,
The write process is completed, and a control end signal Sg is output to the logical operation circuit 22b.

As a result, the logic operation circuit 22b performs logic operation processing on the write/read control signal R/- and the control end signal Sg, and since the read/write mode is set, the logic operation circuit 22b automatically shifts to read processing (third (See figure (c)). Note that if they do not match, the write process continues.

Next, the read processing will be continued.

First, Lee! ''/The write permission signal Se output from the write setting register 22a is inactivated, and the read permission signal Sfga is activated.Furthermore, at the end of the write process, the check start bit of the check start bit generation circuit 22d is generated, and the bit is Starts the read processing operation.

Note that the address control circuit 22 and the address generation circuit 23
Since the operation is similar to the write processing operation, the explanation will be omitted.

Therefore, in the read data control circuit 25, the read data RD is taken in by the input buffer circuit 25a when the read permission signal Sf is activated. Then, based on the read control signal Sd, the data RD is launched @N
25b, and is temporarily registered by the read register 25d.

Furthermore, the value 1 of the address counter 23c, that is, the write data WD and the read data RD are compared by the second comparison circuit 25c. At this time, if both data match, the storage operation of the RAM 28 is normal, and the check operation is ended. Further, if the two data do not match, an error bit is generated in the error bit generating circuit 25e to make the CPU 26 recognize the abnormal termination.

At this time, the CPU 26 checks the defective bits in the RAM 2B by comparing the data in the read expected value register 25f and the read reading register 25d based on the error bit. Furthermore, address failure is confirmed by referring to the temporary address register 23e.

Note that the counter value of the address counter 23c and the value of the register 23d are compared by the first comparison circuit 23d,
When they match, the read process ends.

As a result, the control end signal Sg is output to the logic operation circuit 22b. The logic operation circuit 22b performs logic operation processing on the write/read control signal R/- and the control end signal Sg, and the check end bit is generated! A check end bit is generated at 22c.

Thereby, the CPU 26 can recognize the completion of the processing related to the check operation of the RAM 2B.

FIG. 4 shows a configuration diagram of a computer image processing system according to an embodiment of the present invention.

In the figure, the computer image processing system includes an image display control device according to the present invention surrounded by a dashed line, 110 various circuits 29 that support input/output of each data processing device, and a circuit 29 for image processing and data calculation processing. Main RAM 30 for temporarily storing program data and C for displaying images.
It consists of an RT device 31 and a keyboard 32 through which an operator inputs control data. In addition, each processing device has a bus line 2
Connected to 1.

5(a) and 5(b) are comparative explanatory diagrams of the start-up time according to the embodiment of the present invention and the conventional example, and FIG. 5(a) is a time table at the time of system start-up of the conventional example. It shows.

In the figure, the video RAM check in the conventional example first involves the following steps:
The main RAM was checked, followed by a check of each of the 110 circuits, followed by a check.

FIG. 4B shows a timetable at the time of system startup according to the embodiment of the present invention.

In the figure, the video RAM 2B according to the present invention is checked in parallel with the main RAM 30 checked.

Note that each of the 110 circuits 29 is checked using the main RAM 3.
This is done following the 0 check.

Further, T is a shortened start-up time, which indicates the difference between the system start-up time of the conventional example and the system start-up time of the present invention.

In this way, according to the image display control device according to the embodiment of the present invention, the address control circuit 22. Address generation circuit 23
．． Write data control circuit 24. Read data control circuit 2
5. A CPU 26 and a control signal generation circuit 27 are provided.

Therefore, when the CPU 26 gives the write/read control signal RNO to the address control circuit 22, the address control circuit 22 sends the address generation circuit 23 and the control signal generation circuit 27.
A control start signal Sa is output to each of the write data control circuits 824 and 25, and a write permission signal Se and a read permission signal Sf are output to the write data control circuit 824 and the read data control circuit 25, respectively.

As a result, the control signal generation circuit 27 generates an address generation control signal Sb, a write control signal Sc, and a read control signal Sd based on the control activation signal Sa, and the address generation control signal sb is output to the address generation circuit 23. ,
The write control signal Sc is output to the write data control circuit 24, and the read! The lf control signal Sd is output to the read data control means 5.

In addition, in the address generation circuit 23, the check start address designated by the CPU 26, the control activation signal Sa, the address generation control signal Sb, and the write control signal Sc are activated, so that the check address ADD is output to the video RAM 2B. be done.

At the same time, in the write data control circuit 24, the write control signal Sc and the write permission signal Se are activated, so that the check write data WD is output to the video RAM 2B. This completes the write operation.

Next, in the read data control circuit 26, the read control signal Sd and the read permission signal S' are activated, so that the read data RD is read from the video RAM 28, and a comparison process is performed between the check write data WD and the data RD. At the end of these check processes, a control end signal Sg is output from the address generation circuit 23 to the address control circuit 22.

As a result, even if the capacity of the video RAM 28 is increased due to the demand for higher resolution and multicolor computer graphics, the hardware check process is much easier than the software checking process using the CPU as in the conventional example. The video RAM 2B can be checked in a short time.

As a result, the CPU 26 performs video RA as in the conventional example.
It is no longer necessary to exclusively perform M2B check processing, and it becomes possible to perform other data processing.

(Effects of the Invention) As described above, according to the present invention, an address control circuit, an address generation circuit, a write data control circuit 1, a read data control circuit, a CPU, and a control signal generation circuit are provided.

Therefore, by having the CPU perform only the setting process of the check start address, end address, write data, and check mode at system startup, the video RAM check process is then performed by hardware without the intervention of the CPU. be able to. This makes it possible to process other data such as the main RAM using the video RAM check processing time that was performed by the CPU in software as in the conventional example.

As a result, the total startup time of the computer system can be shortened, and image processing can be started at an early stage.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of an image display control device according to the present invention, FIG. 2 is a configuration diagram of an image display control device according to an embodiment of the present invention, and FIG. 3 is a check diagram according to an embodiment of the present invention. A time chart explaining the modes. FIG. 4 is a configuration diagram of a computer image processing system according to an embodiment of the present invention. FIG. 5 is a comparison explanation of the start-up time according to an embodiment of the present invention and a conventional example. Figure 6 is a configuration diagram of an image display control device according to a conventional example, and FIG. 7 is a RAM chain of a CPU according to a conventional example. 2 is a processing flowchart. RD...Read data. (Explanation of symbols) 11... Bus line, 12... Address control means, 13... Address generation means, 14... Write data control means, 15... Read data control means, 16... Input/output means, R/W...Write/read control signal, Sa...Control start signal, sb...Address generation control signal, Sc...Write control signal, Sd...Read control signal, Se ...Write permission signal, Sf...Read control signal, Sg...Control end signal, ADD...Address for check, WD...Write data for check,

Claims (1)

[Claims] Address control means (12) connected to the bus line (11)
, address generation means (13), write data control means (
14), comprising read data control means (15), input/output control means (16), and control signal generation means (17) connected to the address control means (12), the address control means (12) is the write/read control signal (R
/W), a control activation signal (Sa), a write permission signal (Se) and a read permission signal (Sf) are output based on the control end signal (Sg), and the control signal generating means (17) outputs the control activation signal (Sg). (Sa) and outputs an address generation control signal (Sb), a write control signal (Sc), and a read control signal (Sd), and the address generation means (13) outputs the control activation signal (
Sa), the check address (AD) of the image data storage device (18) based on the address generation control signal (Sb)
D) and a control end signal (Sg), and the write data control means (14) checks the image data storage device (18) based on the write control signal (Sc) and the write permission signal (Se). Write data for (
WD), and the read data control means (16) inputs read data (RD) from the image data storage device (18) based on a read control signal (Sd) and a read permission signal (Sf). An image display control device characterized by: