JP2003058522A - Method and device for monitoring internal ram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for monitoring a RAM, which accurately monitor an internal RAM with a small amount of hardware and improve the convenience for debugging. SOLUTION: A memory (101) for data copy is provided which always latches the same data as data written in a prescribed address of the internal RAM of a microcomputer. An access address comparator (106) generates a first event occurrence signal in the case of coincidence between the internal address value of an internal address bus and a set address value, and a program counter comparator (105) generates a second event occurrence signal in the case of coincidence between the count value of a program counter and a set program counter value. One of the first and second event occurrence signals is selected, and the selected event occurrence signal is outputted to the memory for data copy as a data latch inhibition signal and is outputted to a program counter latch (110) as a latch timing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for monitoring a built-in RAM of a microcomputer, and more particularly to an internal RAM (Random Ac) of a single chip microcomputer.
The present invention relates to a RAM monitor device and method for improving convenience of debugging by monitoring data written in a cess memory).

[0002]

2. Description of the Related Art Generally, an internal RAM incorporated in a single-chip microcomputer has a structure in which an address is controlled by a CPU and a user cannot access it from the outside. However, in an application field that requires a high degree of real-time control such as electronic control of an automobile engine or robot control, it is extremely important to debug the program by accurately monitoring the internal RAM that changes from moment to moment. Therefore, the internal RA
Various techniques for monitoring M in real time have been proposed.

The single-chip microcomputer disclosed in Japanese Patent Laid-Open No. 6-52333 is provided with an address register and a data latch circuit which can be accessed from the outside, and an internal RA to be monitored in the address register.
Set the address of M. The set address and the address value on the internal address bus are compared by the address comparator, and when the set address and the address value on the address bus match, the address comparator outputs a trigger signal to the data latch circuit. The data latch circuit latches the data on the data bus at the time when the trigger signal is input.
The data latched by the data latch circuit and the set address value of the address register are taken out according to a trigger signal from the outside. The data latched by the data latch circuit is held until the next trigger signal is input from the address comparator.

In the RAM monitor device disclosed in Japanese Patent Publication No. 4-47857, a copy RAM having the same contents as the internal RAM and a monitor RAM connected in parallel with the copy RAM are provided. Normally, the copy RAM and the monitor RAM are constantly rewritten to have the same contents as the internal RAM, and the data is followed. However, when an event signal that gives the timing to be monitored is input, the monitor RAM is disconnected from the computer system and the data input is disabled, and the contents of the monitor RAM at that time (the same data as the internal RAM at that time) Is read. When reading is completed, monitor RAM
Again follows the data in the internal RAM.

[0005]

However, in the single-chip microcomputer disclosed in Japanese Patent Laid-Open No. 6-52333, the latched data is always updatable. Therefore, illegal data is
Even if the data is written in the AM and a malfunction occurs, if the normal data is overwritten, the invalid data cannot be found. Even if the illegal data can be read to the outside, it takes a long time to perform the external communication, which makes it difficult to determine when the data is.

Further, in the RAM monitor device disclosed in Japanese Patent Publication No. 4-47857, illegal data is not updated by disconnecting the monitor RAM from the system at the time of monitoring, but for copying and monitoring. Same RA
Since it is necessary to install two Ms, there is a drawback that the amount of hardware increases.

It is an object of the present invention to provide a RAM monitor device and method capable of accurately monitoring the internal RAM with a small amount of hardware.

Another object of the present invention is to provide a RAM monitor device and method that further improve the convenience of debugging.

[0009]

According to the present invention, there is provided a RAM monitor device for monitoring data written in an internal RAM (Random Access Memory) of a microcomputer.
A data copying memory which is connected to the internal data bus of the microcomputer and stores the same data as the data written in a desired address of the internal RAM, and an event occurrence for detecting an event occurrence due to a plurality of predetermined event occurrence factors Detecting means, data copy prohibiting means for prohibiting a data copying operation of the data copying memory when an event occurrence due to a preselected event occurrence factor is detected, and the data copying And an external interface for reading the data stored in the memory for external use.

Further, according to the present invention, a RAM monitor device for monitoring data written in an internal RAM (Random Access Memory) of a microcomputer is connected to an internal data bus of the microcomputer and is provided at a desired address of the internal RAM. A data copying memory that always stores the same data as the data to be written is connected to the internal address bus of the microcomputer, and its address value is compared with a preset address value. When they match, a first event occurs. An access address comparison means for generating a signal and a program counter comparison for generating a second event generation signal when the counter of the program counter in the program executed by the microcomputer is compared with a preset program counter value and they match. Means and said Event selecting means for selecting one of the first and second event occurrence signals and outputting the selected event occurrence signal to the data copying memory as a data latch inhibit signal; and data latched in the data copying memory. And an external interface for reading out to the outside.

A program counter memory for latching the count value of the program counter at the timing of the event occurrence signal selected by the event selection means is further provided, and the counter value of the program counter latched in the program counter memory is the external value. It is characterized in that it can be read to the outside by an interface.

The system further comprises a timer counter memory for latching the timer counter value of the microcomputer at the timing of the event occurrence signal selected by the event selecting means, and the timer counter value latched in the timer counter memory is the external interface. It is characterized by being readable to the outside by.

According to another aspect of the present invention, a RAM monitor device for monitoring data written in an internal RAM (Random Access Memory) of a microcomputer is connected to an internal data bus of the microcomputer to store data in the internal RAM. A data copying memory that always stores the same data as the data written to the desired address is connected to the internal address bus of the microcomputer, and its address value is compared with a preset address value. A second event generation signal is generated when the access address comparison means for generating one event generation signal and the count value of the program counter in the program executed by the microcomputer and the preset program counter value are compared and coincide with each other. Program counter comparing means for The third event is connected to the internal data bus, compares the data on the internal data bus with a data range that allows writing to the internal RAM, and when the write data has a value outside the preset range, A data comparison means for generating a generation signal and one of the first, second and third event generation signals are selected and the selected event generation signal is output to the data copying memory as a data latch inhibit signal. It is characterized by comprising an event selection means and an external interface for reading the data latched in the data copying memory to the outside.

Further, the RAM monitoring method according to the present invention is
In the data copying memory connected to the internal data bus of the microcomputer, the same data as the data to be written at the desired address of the internal RAM is stored, and event occurrence due to a plurality of predetermined event occurrence factors is detected, When an event occurrence due to a preselected event occurrence factor among the plurality of event occurrence factors is detected, the data copying operation of the data copying memory is prohibited, and the data stored in the data copying memory is externally stored. It is characterized by reading out to the outside through an interface.

As described above, according to the present invention, the same data as the data to be written in the desired internal RAM address is always latched in the data copying latch and selected from a plurality of predetermined event occurrence factors. The data update of the data copying latch is prohibited at the timing of the occurrence of one event. Therefore, by reading the data from the data copying latch in the update prohibited state, the data in the internal RAM can be accurately grasped even when the operation of the external interface is slow, and the simultaneity of the data and the reliability of the data can be obtained. Can be achieved together.

By latching the program counter value being executed at the timing of the occurrence of one selected event, it is possible to easily determine at which address the program code has written the illegal data.

Further, by latching the timer counter value when an event occurs, it is possible to know at what time the event occurred even if the CPU runs out of control.

Further, if the data writing range to the internal RAM is set in advance, an event is generated when illegal data outside the expected range is written, and the data update of the data copying latch is prohibited as described above. In addition, the program counter value being executed can be latched.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION (Structure of First Embodiment) FIG.
1 is a functional block diagram showing a first embodiment of a RAM monitor device according to the present invention. The RAM monitor device according to the present embodiment is provided with the data copying latch 101, and as described later, maintains the synchronism with the data written in the internal RAM of the single-chip microcomputer and prevents the operation of the CPU. It is possible to access from the outside without.

The timing at which the data copying latch 101 latches the data from the internal data bus is determined by the copy permission signal S _CPY output from the copy address comparator 102. In the copy address setting register 103, the address of the internal RAM to be monitored is set by the user. The copy address comparator 102 compares the address value of the internal address bus with the desired copy address value set in the copy address setting register 103 when the RAM write enable signal indicates writing to the internal RAM, and if they match, The copy permission signal S _CPY is output to the data copy latch 101. Therefore, every time data is written to the internal RAM address to be monitored, the copy permission signal S _CPY is output, the same data as the internal RAM is written from the internal data bus to the data copying latch 101, and the data is updated in real time. It

In the program counter setting register 104, a program counter value at a desired instruction execution location in the CPU execution program is set. The program counter comparator 105 constantly compares the program counter of the CPU with the setting register value of the program counter setting register 104, and outputs a match signal S _PC as an event generation signal when they match.

The access address comparator 106 includes an address value of the internal address bus and an address setting register 107.
The register value set to is always compared, and when they match, a match signal S _ADR is output as an event generation signal.
Unlike the copy address comparator 102, the access address comparator 106 uses not only an address in the RAM area but also an address for accessing a circuit in the single-chip microcomputer in order to observe the address of the access destination of the CPU. Must be entered from.
However, when the address detection range is limited to the RAM area, the same address as the address connected to the RAM data copy latch 11 may be connected. Here, the internal address bus is connected to the access address comparator 106 and the copy address comparator 102,
The detection range of the copy address comparator 102 is limited by using the RAM write enable signal.

The event generation signal (S _PC ) from the program counter comparator 105 and the event generation signal (S _ADR ) from the access address comparator 106 are input to the event selector 108, and the event generation signal on the preselected side is A data write inhibit (data copy inhibit) signal is output to the data copy latch 101, and a latch timing signal is output to the program counter latch 110.

The event selection register 109 holds an event occurrence signal selected by the event selector 108, that is, a set value for determining an event factor.
For example, if “00” is set in the event selection register 109, the event selector 108 causes the event generation signal (S _ADR ) from the access address comparator 106.
Are selected and output to the data copying latch 101 and the program counter latch 110, respectively. When the event occurrence signal selected by the event selector 108 is input, the program counter latch 110 latches the program counter value at that time.

The external interface 111 is connected to the copy address setting register 103, the program counter setting register 104, the address setting register 107, the event selection register 109, the data copying latch 101, and the program counter latch 110, respectively. The user can enter C through the external interface 111.
Register settings and data reading can be performed without disturbing the operation of the PU.

The capacity of the data copying latch 101 is equal to the internal RA of the single-chip microcomputer.
It does not have to have the same capacity as M. This is because there is almost no use for copying all the data in the internal RAM, and if a data copying latch 101 of the same capacity is provided, it becomes a single chip.
This is because the circuit scale of the microcomputer increases. Therefore, it suffices if the data copying latch 101 having a capacity capable of copying a part of data is provided.

Which address data is to be copied is determined by the register value set in the copy address setting register 103. As described above, every time data is written to the internal RAM address for monitoring, the same data as the internal RAM is written to the data copying latch 101 from the internal data bus. In a normal state, this updating operation is repeated.

If the data to be output to the outside spans a plurality of addresses, a plurality of data copying latches 101, copy address comparators 102, and copy address setting registers 103 may be provided.

(Data Copy Inhibit Control) In the first embodiment, the data copy of the data copy latch 101 is prohibited because it matches the set value of the program counter (event generation signal S _PC ) and the access address setting. This is the case where the one selected by the event selector 108 among the coincidence with the value (event generation signal S _ADR ) is input to the data copying latch 101. As described above, the coincidence with the set value of the program counter means a case where the program counter when the instruction is executed coincides with the set value of the program counter setting register 104. The matching with the set value of the access address means a case where the access address when the circuit in the computer accesses a memory space in which the circuit is present and the set value of the address setting register 107 match.

The event selector 108 is an event selection record.
Event factor is selected in advance according to the setting value of register 109
The selected event occurrence signal is prohibited from data copying.
It is output to the data copying latch 101 as a stop signal and
Data write inhibition control of the data copying latch 101
U When the data copy latch 101 is in the data copy prohibited state
If it becomes, the data copy latch 101 is added after that.
On the other hand, a copy permission signal S _CPYEven if you enter, for data copying
The data in the latch 101 is not updated, just before the event occurs
Data is retained. In this way,
Data stored in the switch 101 is an external interface.
It is possible to read from 111.

The event generation signal selected by the event selector 108 is output to the program counter latch 110 as a latch timing signal. When the selected event occurrence signal is input, the program counter latch 110 latches the program counter value at that time. The value of the program counter at the time of this event can be similarly read from the external interface 111. Therefore, when an event occurs, the user can easily know which program code is used to store the data written in the RAM in the data copying latch 101.

In addition, the copy address setting register 10
3, program counter setting register 104, address setting register 107, and event selection register 10
Also for 9, the external interface 111 can read / write data from the outside. Since the external interface 111 operates independently of the single-chip microcomputer, it does not affect the operation of the single-chip microcomputer (CPU operation).

Data copy latch 101 in copy prohibited state
When the data is read via the external interface 111, the state shifts to the copy permitted state. In the RAM data copy latch 101 in the copy permitted state, the data update is repeated at the timing when the copy permission signal S _CPY is input again, as described above.

As a method of switching the data copying latch 101 between the copy prohibited state and the copy permitted state, a separately provided flag setting register can be used.
Specifically, when an event occurs, the flag setting register is automatically set on the circuit side and the data copy latch 1
01 is set to the copy prohibited state, and the flag setting register is reset to shift to the copy permitted state under the control of the external interface by the user.

(Second Embodiment) FIG. 2 shows an R according to the present invention.
It is a functional block diagram which shows 2nd Embodiment of AM monitor apparatus. In the configuration of the second embodiment, the same functional blocks as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 2, the data comparator 201 and the data range setting register 202 are added, and the number of inputs of the event selector 203 is increased to three.
This is a difference from the embodiment. In the second embodiment, the internal R
A data range at the time of writing to the AM is specified, and the inside or outside of the range is added as a condition for event occurrence. By setting such a data range, in a certain program routine, it is possible to detect a case where undesired data is written to the RAM due to a malfunction of the execution program, or a case where the extra data is overwritten on the important RAM data. You can

The data range setting register 202 is set through the external interface 111, for example, in a certain program to a data range that is not writable in the internal RAM. The data comparator 201 constantly compares the unwritable data range set in the data range setting register 202 with the data value on the internal data bus, and if they match, outputs a match signal (event occurrence signal) to the event selector 203. Is output.

The event selector 203 is as described above.
According to the setting value of the event selection register 109,
Event occurrence signal from program counter comparator 105
(S _PC), The event from the access address comparator 106
Generation signal (S_ADR), And from the data comparator 201
Select one of the event occurrence signals of
Signal is a data write inhibit (data copy inhibit) signal.
No. to the data copying latch 101 as the number
To the program counter latch 110 as a signal
Output. Data copy latch 101, program
Counter latch 110 The operation of that circuit block is the first
The description is omitted because it is the same as the embodiment.

(Third Embodiment) FIG. 3 shows an R according to the present invention.
It is a functional block diagram which shows 3rd Embodiment of AM monitor apparatus. The third embodiment has a configuration in which a timer counter latch 301 is added to the configuration of the second embodiment shown in FIG. The third embodiment may have a configuration in which a timer counter latch 301 is added to the configuration of the first embodiment shown in FIG. In the configuration of the third embodiment, the same functional blocks as those of the embodiment shown in FIGS. 1 and 2 are designated by the same reference numerals and description thereof will be omitted.

In FIG. 3, the event generation signal selected by the event selector 203 is used as a data write prohibition (data copy prohibition) signal as the data copying latch 10.
1 to the program counter latch 110 as a latch timing signal, and similarly to the timer counter latch 301 as a latch timing signal. The timer counter latch 301 is connected to a timer counter (not shown) in the single-chip microcomputer, and latches the timer value according to the latch timing signal from the event selector 203. The timer value latched by the timer counter latch 301 can be read through the external interface 111.

By providing the timer counter latch 301, even when the CPU runs out of control and the program counter becomes an indefinite value, the latched timer value is read to cause the RAM data to be stored at the time when the event occurs. You can know if it was held.

Since the operations in the above-described first to third embodiments are completely independent of the operation of the single chip computer, they do not affect the real-time property of the single chip computer at all.

[0043]

As described in detail above, according to the present invention, the same data as the data to be written to a desired internal RAM address is always latched in the data copying latch, and a plurality of predetermined event occurrence factors are generated. At the timing of occurrence of one event selected from the above, the data update of the data copying latch is prohibited and the program counter value being executed is latched.

Therefore, by reading the data from the data copy latch in the update prohibited state, the data in the internal RAM can be accurately grasped even when the operation of the external interface is slow, and the simultaneity of the data and the data can be obtained. Can be achieved together. Further, since the program counter value at the time of event occurrence can be read, it is possible to easily determine at which address the program code has written the illegal data.

Further, if the data writing range to the internal RAM is set in advance, an event is generated when illegal data outside the assumed range is written, and the data update of the data copying latch is prohibited as described above. In addition, the program counter value being executed can be latched.

Further, by latching the timer counter value when an event occurs, even when the CPU runs out of control, it is possible to know at what time the event occurred.

[Brief description of drawings]

FIG. 1 is a functional block diagram showing a first embodiment of a RAM monitor device according to the present invention.

FIG. 2 is a functional block diagram showing a second embodiment of a RAM monitor device according to the present invention.

FIG. 3 is a functional block diagram showing a third embodiment of a RAM monitor device according to the present invention.

[Explanation of symbols]

101 Data copy latch 102 Copy address comparator 103 Copy address setting register 104 Program counter setting register 105 Program counter comparator 106 access address comparator 107 address setting register 108 Event Selector 109 event selection register 110 program counter latch 111 External interface 201 data comparator 202 Data range setting register 203 Event selection register 301 timer counter latch

Claims (7)

[Claims] 1. An internal RAM (Ran of a microcomputer
dom access memory) for monitoring data written to a RAM monitor device, which is connected to an internal data bus of the microcomputer and stores the same data as the data written to a desired address of the internal RAM, Event occurrence detection means for detecting an event occurrence due to a plurality of predetermined event occurrence factors, and at the time when an event occurrence due to a preselected event occurrence factor among the plurality of event occurrence factors is detected,
A RAM monitor device, comprising: a data copy prohibiting unit for prohibiting a data copy operation of the data copy memory; and an external interface for reading the data stored in the data copy memory to the outside. 2. The event occurrence detection means is connected to an internal address bus of the microcomputer, compares the address value with a preset address value, and generates a first event occurrence signal when they match. Access address comparing means, and program counter comparing means for generating a second event occurrence signal when the counter value of the program counter in the program executed by the microcomputer is compared with a preset program counter value and they match. The RAM monitor device according to claim 1, further comprising: 3. The event occurrence detecting means is further connected to a data bus inside the microcomputer, and compares the data on the data bus inside the microcomputer with a data range in which writing to the internal RAM is permitted. 4. The R according to claim 2, further comprising a data comparison means for generating the third event occurrence signal when the write data has a value outside the preset range.
AM monitor device. 4. The data copy prohibiting means selects an event selection means selected in advance from the plurality of event occurrence factors; and an event occurrence due to the selected event occurrence cause, the data copying memory. 2. The RAM monitor device according to claim 1, further comprising a selector that outputs a data copy prohibition command to the RAM monitor. 5. A program counter memory for holding a program counter value at the same point in time when the data copying memory becomes a data copying prohibited state due to an event occurrence due to the selected event occurrence factor. 5. The RAM monitor device according to any one of 1 to 4. 6. A timer counter memory for holding a timer counter value at the same time when the data copying memory is in a data copying prohibited state due to the occurrence of an event due to the selected event occurrence factor. 6. The RAM monitor device according to any one of 1 to 5. 7. An internal RAM (Ran) of a microcomputer
dom access memory), in the data copying memory connected to the internal data bus of the microcomputer, the same data as the data written at the desired address of the internal RAM is stored, Event occurrence due to a plurality of event occurrence factors that have been detected, when the event occurrence due to a preselected event occurrence factor among the plurality of event occurrence factors is detected,
A RAM monitoring method, wherein the data copying operation of the data copying memory is prohibited, and the data stored in the data copying memory is read out to the outside through an external interface.