KR0150161B1 - Device for displaying register and ram data - Google Patents

Abstract

The technical field to which the invention pertains to the scope of the claims: A device that enables visual confirmation of data in registers and RAM.

2. Problems to be solved by the invention: Provides an improved device that allows the program to visually check the data of the internal registers and RAM of the microcomputer without stopping the actual execution.

3. Summary of Solution of the Invention: According to an improved apparatus, an evolution chip outputting a system clock, bank data, read and write signals, a control signal, and inputting and outputting data through an internal data bus, and responding to the system clock. The first latch for latching the bank data, the second latch for latching the confirmation bank data applied through the data bus in response to the control signal, and the output of the first and second latches are compared. A bank comparator comprising a comparator for outputting a chip enable signal for selecting a memory specific to the data; data provided from the system data bus for interfacing the data on the memory to be read or written by the host side of the system; A buffer for storing a data and a latch for latching data in a memory in response to the system clock; And a gate interface unit for generating a write enable control signal of the memory by combining and gating the read and write signals and the output of the second latch; and latching data of the data bus in response to the system clock. A latch element providing an address of the memory, a buffer element commonly connected to an output terminal of the latch element, storing data provided to the bank data bus and providing the address as the memory address, and a read connected to the data output terminal of the memory. And a memory unit including the first and second buffer elements for writing, and the memory having a data bus connected to the first and second buffer elements.

4. Significant use of the invention: It is used in the field to visually check the data of the internal registers and RAM of the microcomputer.

Description

Device for displaying data of MICOM internal register and RAM

1 is an operation timing diagram applied when a device according to the present invention performs a read operation on an internal register.

2 is an operation timing diagram applied when a device according to the present invention performs a write operation to an internal register.

3 is a diagram showing an expiration date of bank data for storing RAM data.

4 is a bitmap of a system data bus to which the present invention is applied.

5 is a detailed circuit diagram of a device according to the invention.

TECHNICAL FIELD The present invention relates to the field of microcomputer applications, and more particularly, to an apparatus for displaying data of internal registers and RAM of a microcomputer while executing a program.

In general, in-circuit emulators (hereinafter referred to as ICEs) are necessary to develop applications for microcontroller units (MICOMs) and microprocessor units (MPUs). In this ICE, there is an evaluation chip that excludes only the ROM part of the internal block of MICOM.

Therefore, when the developer of the MICOM application program the ROM part of the evolution chip to control the system he wants to develop, the ICE is helped to develop the program more effectively. At this time, it is necessary for the developer to check and display the data of the internal registers and the RAM of MICOM by utilizing various functions of the ICE.

In such a place, when checking the internal registers and RAM data of the MICOM, conventionally, the actual execution of the program is stopped and the values of the internal registers and the RAM are read and confirmed through the screen or the display device of the personal computer. This conventional method has a disadvantage in that the operation of the microcomputer operated by the program of the ROM is interrupted and thus the execution of the program cannot be performed during the display operation.

Therefore, even if there is a desire for display, it is burdensome to stop program execution, so that the developer cannot use the function of the ICE properly.

Accordingly, an object of the present invention is to provide an apparatus for visually confirming the internal registers and RAM data of the microcomputer without stopping the actual execution of the program in view of the above-described conventional problems.

According to the present invention for achieving the above object, an evolution chip for outputting a system clock, bank data, read and write signals, a control signal and input and output data through an internal data bus in a microprocessor, and the system clock A first latch for latching the bank data in response to the second latch; a second latch for latching confirmation bank data applied through the system data bus in response to a system control signal at a host side of the system; A bank comparator comprising a comparator for comparing the outputs of the two latches and outputting a chip enable signal for selecting a specific memory upon matching;

A host interface including a buffer for storing data provided from a system data bus and an latch for latching data in memory in response to the system clock for interfacing the host side of the system to read or write data in the memory. Wealth; A signal generator for combining the read and write signals with the output of the second latch to generate a Lart enable control signal of the memory; latching data of a data bus in response to the system clock to address an address of the memory; Even a latch providing a buffer device includes: a buffer device connected to an output terminal of the latch element and storing data provided to the system data bus and providing the data as an address of the memory; and a first read and write device connected to the data output terminal of the memory. And a memory unit including a second buffer and the memory having a data bus connected to the first and second buffer elements.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. First, the principle of the method for real-time display of the contents of the internal register and RAM in accordance with the present invention will be described for convenience of understanding. Typically, microcomputers have registers and RAM (herein collectively referred to as registers and RAM). These registers are largely divided into control registers and data memory, all of which are very important for application developers. Therefore, it is necessary to check the contents of registers while developing an application program, and to correct the errors easily to prevent normal operation of the program. By the way, one of the methods to find the contents of this internal register is to find the program at a certain point while stopping. This may cause damage to the target system, and if the actual time is required, this method is essential in real time. It is not effective because it is not made. Therefore, the present invention uses the hardware of FIG. 5 to implement a method for displaying the contents of internal registers without manipulation in real time.

Referring to FIG. 5, a bank comparison block A having a comparator connected to one EVE chip 53, two latches 54 and 55, and output terminals 11 and 13 of the two latches to perform a comparison: buffer 51 and a latch Host interface block B, which has 52, forcibly writes to or reads from the host in memory 58: Block 59 for controlling the write permission signal WE of memory 58: Controls the memory address, including memory 58, latch 57, and buffer 60 The output 17 of the latch 57 and the output of the buffer 60 are connected to the address bus of the memory, and the outputs of the buffer 61 and the buffer 62 which control the directionality for writing and reading data are connected to the data bus of the memory 58, respectively. Able to know.

Here, when the evolution chip is abbreviated as an EVA chip, the EVA chip 53 provides the system clock S3 to line 6 and S2 to line 10. Bank data is also applied to line 5, and internal data is transmitted and received via bus 7. The read signal is output through the line 8, and the write signal is output through the line 9.

Accordingly, in FIG. 1, the internal data bus DB [0: 7] has an address of an internal register in a section where the system clock S3 is a logic '1', and the internal register read signal IOR 8 is logical'1. When the internal data bus is on, the data read from the register indicated by the address in the interval where the system clock S3 is logic '1' is loaded.

In FIG. 2, the internal data bus DB [0: 7] has an address of an internal register and the internal register write signal IOW 9 is a logic '1' in a period where the system clock S3 is a logic '1'. When the internal data bus is in the interval when the system clock S3 is a logic '1'; The data to be written in the register indicated by the address is loaded.

In FIG. 3, designated RAM bank data is latched in a section in which the system clock S3 is logic '1'. Therefore, the bank data change at every system clock S3. Banks can have two or more, so you need to know what banks are currently in use. If the program designer can specify the bank of register to check in advance, the value of the internal register can be checked in the following way.

As shown in Fig. 5, the bank to be checked is loaded on the BDB [0: 7] (12), stored in the latch 55 by the control signal W1 (14), and its output 13 is one side of the comparator 56. Allows input to be set up. In addition, the chip 53 stores the bank data SMB [0: 3] (5) in the latch 54 in the section in which the system clock S3 (6) is logic '1', and its output 11 is the other input of the comparator 56. To bank data. At this time, if the comparator 56 compares the two input conditions and is the same, the output CE 15 is sent out to select the memory 58.

The SRAM memory 58 stores DB [0: 7] (7) from which the internal data corresponding to the same address as the internal register of the selected bank comes from the EVA chip. The storage condition may be stored while the LOW (9) output from the EVA chip is logic '1' and while the IOR (8) is logic '1'.

The method of selecting the write mode may be implemented by a combination of the inputs BDB7 and BDB6 of the latch 55. Therefore, if BDB7, BDB6 is 1, it is read, if BDB7, BDB6 is 10, it is write, and if BDB7, BDB6 is 11, it is read and write mode.

Addressing of the memory 58 stores the DB [0: 7] (7) output from the EVA chip 53 in the latch 57 in the section where the system clock S3 (6) is logic '1'. RA [0: 7] is the address of the memory. In this way, the same value as the value written to the internal register of the EVA chip is stored in the memory 58 through the buffer 61.

How to read the contents stored in the memory 58 is as follows. The output start signal 21 of the memory 58 is a logic '0' in a period where both MWE0 and MWE1 are logic '0' and the system clock S2 is logic '1'. At this time, the contents stored in the memory are loaded on the DATA [0: 7] (23) bus and the latch 52 stores RA [0: 7] and DATA [0: 7] at the time when the system clock S2 is logic '1'. Then, the host can read the address and data of the internal register when R1 is logic '1', so the contents of the internal register of the microcomputer are read in real time.

The method of initializing and reading memory directly from the host is described as follows. The system data bus SD [8:15] is applied to the input of buffer 60 through buffer 51 when RWB is logic '0' and the address of memory as RA [0: 7] when W2 is logic '1'. do. At the same time, SD [0: 7] is applied to the data input / output terminal of the memory 58 through the buffer 62 when the RWB is the logic '0', and the initial values are stored in the memory when the signals MWE0 and MWE1 are the logic '0', respectively.

The method of directly accessing and reading the memory is the same as the method of designating and storing the address of memory 58, and the output start signal 21 of memory 58 is valid when MWE0 and MEW1 are logic '0', respectively. The contents will be published. At this time, when the RWB is a logic '1' through the buffer 62 and the buffer 51, it is loaded on the SD [0:15], and thus the contents of the memory 58 are transmitted to the host.

As described above, according to the present invention, it is possible to visually check the data of the internal register and RAM of the microcomputer without stopping the actual execution of the program.

Claims (2)

A device for writing and reading data of internal registers and RAM of a microcomputer or microprocessor in real time during program execution: A system clock, bank data, read and write signals, control signals are output, and data are transmitted through an internal data bus. An evolution chip for outputting a signal, a first latch for latching the bank data in response to the system clock, and a second latch for latching confirmation bank data applied through a host system data bus in response to a host system control signal And a bank comparator including a comparator for comparing the outputs of the first and second latches and outputting a chip enable signal for selecting a specific memory at a match; forcibly reading data of the memory from the host side of the system. Interface from the system data bus A host interface unit including a buffer for storing data, and a latch for latching data of the memory in response to the system clock: a combination of gating the read and write signals and an output of the second latch to enable write of the memory; A signal generator for generating a control signal; a latch element for latching data of the data bus in response to the system clock to provide an address of the memory, and being commonly connected to an output terminal of the latch element and provided to a host system data bus; A buffer device for providing data as an address of the memory, and first and second buffer devices for read and write connected to a data output terminal of the memory, the memory having a data bus connected to the first and second buffer devices. Apparatus characterized by having a memory unit provided. The apparatus of claim 1, wherein the memory element is a static memory.