JPH07182199A - Information processor - Google Patents

Abstract

PURPOSE:To provide an information processor of a microcontrol system which can perform a test without increasing the number of test-only external terminals. CONSTITUTION:An information processor is provided with a micro-ROM address selector circuit 19 which performs the switching between the output of an instruction register 12 and the micro-ROM address inputted through an external terminal 21, and a micro-ROM address switching circuit 22 which performs the switching between the microaddress that is designated by the output of the micro-ROM with the instruction start timing and the output of the circuit 19. Then an address is inputted through the terminal 21 with the start timing of a microstep set in a test mode, and the microstep is carried out based on the microflow written in the micro-ROM. Therefore the test is facilitated by a fact that the address of the micro-ROM is inputted through the terminal 21. Furthermore the terminal 21 can be applied to the purposes other than input of the address. Therefore the test can be carried out with a small number of terminals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus, and more particularly to improvement of a test circuit in a microprogram type information processing apparatus.

[0002]

2. Description of the Related Art An example of a test circuit for an information processing apparatus of this type is disclosed in Japanese Patent Laid-Open No. 62-278645. Referring to FIG. 5, which shows a block diagram of a main part of the information processing apparatus described in the publication, the information processing apparatus includes an instruction ROM 11, an instruction register 12, and a microprogram R.
An OM (hereinafter referred to as a micro ROM) address register 13, a micro ROM section 14 including a decoder and a micro ROM, a latch circuit 15, a control signal generation circuit 1
7. Micro ROM address selection circuit, latch circuit 20
And an external input terminal group (hereinafter referred to as an external terminal) 21. The output of the instruction ROM 11 is set in the instruction register 12, the output of the instruction register 12 is stored in the micro ROM address register 13, and in response to the clock inversion φ. It is supplied to the micro ROM address selection circuit 19.

On the other hand, after the address signal at the time of the test supplied from the external terminal 21 is also latched by the latch circuit 20,
It is supplied to the micro ROM address selection circuit 19. The outputs of the micro ROM address register 13 and the latch circuit 20 are output in response to the test signal TEST1 supplied from the test terminal in the input external terminal group 21 when the output of the latch circuit 20 is high (H) level. , At the low (L) level, the address values set in the micro ROM address register 12 are selected and supplied to the micro ROM section 14.

Of the output of the micro ROM unit 14, a signal of several bits is stored in the micro ROM address register 13 as the value of the next address, and the remaining bits are supplied to the control signal generation circuit 17 to generate a control signal. It is configured.

To explain the operation again with reference to FIG. 5, the TEST1 signal is fixed at the L level during normal instruction execution. The instruction code read from the instruction ROM 11 is set in the instruction register 12,
Since one signal is at the L level, the contents of the instruction register 12 are transferred to the micro ROM address register 13.

The micro ROM address selection circuit 19 selects the address value set in the micro ROM address register 13, and execution of a series of micro steps specific to the instruction is started.

The contents of the head address are read from the micro ROM 14 and latched in the latch circuit 15. The control signal generation circuit 17 outputs a control signal 18 based on the information latched by the latch circuit 15.

On the other hand, the next micro ROM address is determined by the output signal 16 for several bits of the latch circuit 15, and the micro step is continuously executed.

In the test mode, the TEST1 signal is set to H level. Since the TEST1 signal is at the H level, the micro ROM address selection circuit 19 has the external terminal 2
The test address value supplied from 1 and latched in the latch circuit 20 is selected, and the operation is performed regardless of the instruction execution flow specific to the instruction execution, and the microsteps specified by the input address are sequentially executed. To be done.

[0010]

In recent years, microcomputers have come to include complicated instructions, and microsteps have become complicated, so that the number of bits of microinstruction addresses has also increased. For example, if there is a 2K step micro instruction, the address of the micro instruction becomes 11 bits. Further, in spite of the complexity of the functional blocks including the timer and the serial interface, the miniaturization of the package has become necessary to meet the demand for miniaturization of the device.

However, the conventional information processing apparatus requires a terminal for inputting an address of a micro instruction, which has a drawback of increasing the number of terminals.

An object of the present invention was made in view of the above-mentioned conventional drawbacks, and it is an object of the present invention to enable a test to be executed without increasing the number of external terminals dedicated to the test of the information processing apparatus.

[0013]

According to the information processing apparatus of the present invention, the contents of the instruction register are set in the microprogram ROM address register during normal operation, and the value is selected by the microprogram ROM address selection circuit to make it unique to the instruction. When the execution of a series of micro steps is started, the contents of the head address are latched in the first latch circuit from the micro program ROM section storing the micro program, and the micro program ROM is output by a predetermined bit of this latch circuit. The next address of the unit is set in the microprogram ROM register, and the address value of a predetermined microstep supplied from the external terminal is latched in the second latch circuit during the test, and then the output signal thereof responds to the test signal. Select the micro program ROM In a microprogram type information processing device selected by a path, at the time of the test, only an execution start address of a predetermined microprogram process is designated based on an address value supplied from the external terminal, and the microprogram following the execution start address is specified. The program processing is provided with means for selecting and executing the next microstep based on the data read from the microprogram ROM section.

The means are the microprogram ROM address selection circuit and the microprogram R.
A micro program ROM address switching circuit and the micro program ROM register are inserted between the OM section and the micro program ROM address switching circuit in response to an instruction start signal at an instruction start timing, and the micro program ROM address switching circuit outputs the first latch circuit and At least one of the outputs of the microprogram ROM address selection circuit is selected and supplied to the microROM register.

Furthermore, after the execution start address given from the external terminal is latched by the second latch circuit, the external terminal is used as either an input terminal or an output terminal of a predetermined signal. Characterize.

[0016]

Embodiments of the present invention will now be described with reference to the drawings. Referring to FIG. 1, which is a block diagram of a first embodiment of the present invention, a part different from the conventional example is a micro RO.
The M address switching circuit 22 and the switching circuit 23 are newly added so that one of the outputs of the control signal generating circuit 17 and at least one of the output signals of the internal circuit 24 are selected by the switching circuit 23 and output to the external terminal 21. That is what I did.

That is, a micro ROM is provided between the micro ROM address selection circuit 19 and the micro ROM section 14.
The address switching circuit 22 and the micro ROM address register are inserted, and in response to the instruction start signal MSTART supplied from the execution unit (not shown) at the instruction start timing, the micro ROM address switching circuit 22 outputs the output of the latch circuit 15 and the micro ROM. At least one of the outputs of the ROM address selection circuit 19 is selected and the micro RO is selected.
It is supplied to the M register 13. In response to the second test signal TEST2 supplied from the outside, at least one of the predetermined control signal 18 provided by the control signal generating circuit 17 and the predetermined signal output from the internal circuit 24 so that the result can be monitored. The configuration is selected by the switching circuit 23 and output to the external terminal 21.

The other structure is the same as that of the conventional example, and the same constituent elements are designated by the same reference numerals and the description of the structure is omitted.

The operation will be described with reference to FIG. 2 which is a timing chart for explaining the operation during the normal operation and FIG. 3 which is a timing chart for explaining the operation during the test in addition to FIG. The TEST1 signal is fixed at L level.

The instruction code read from the instruction ROM 11 is supplied to the instruction register 12, but the TEST1 signal is at the L level, so the content a1 of the instruction register 12 is R.
It is supplied to the OM address switching circuit 22. The command start signal MSTART goes high at the command start timing,
The contents a1 of the instruction register 12 are transferred to the micro ROM address register 13, and execution of a series of micro steps specific to the instruction is started.

The content a1 of the head address is read from the micro ROM section 14 and latched in the latch circuit 15. The control signal generation circuit 17 outputs the control signal 18 based on the information (a1) latched by the latch circuit 15.

After the start of execution of the microstep, the instruction start signal MSTART goes low and the latch circuit 15
The output 16 for a few bits of ## EQU1 ## determines the next micro ROM address a2, and microstep execution is subsequently performed.

At the time of test, the TEST1 signal is set to H level. Referring to FIG. 3, in response to the H level of the TEST1 signal, the micro ROM address selection circuit 19 selects the address value A1 input from the external terminal 21 and latched by the latch circuit 20.

An instruction start signal MST at the instruction start timing
The ART becomes H level, the contents of the latch circuit 20 are transferred to the micro ROM address register 13, and the execution of micro steps with the micro address A1 supplied from the external terminal 21 as the head address is started.

Starting address A from the micro ROM section 14
The content of 1 (A1) is read and latched in the latch circuit 15. The control signal generation circuit 17 outputs a control signal 18 based on the information (A1), (A2), ... Latched by the latch circuit 15.

After the start of execution of the microstep, the instruction start signal MSTART goes low and the latch circuit 15
The output 16 for a few bits determines the next micro ROM address A2, and microstep execution is subsequently performed.

After the instruction start timing, the control signal 18
Is output from the external terminal 21, and the control signal 18 or the output signal of the internal circuit 24 can be monitored from outside the information processing apparatus.

Referring to FIG. 4 which is a block diagram of the second embodiment of the present invention, the control signal 18 is not output to the external terminal 21 and only signals from other blocks are connected.

Therefore, in the test mode, except for the instruction start timing, the external terminal 21 is used as a terminal for inputting a test signal of another block or for monitoring an output signal. In the case of this example, since the switching circuit 23 is unnecessary, the input terminal for the control signal (TEST2) and its wiring are also unnecessary.

[0030]

As described above, in the conventional information processing apparatus, at the time of testing, only the execution start address of a predetermined microprogram process is designated based on the address value supplied from the external terminal, and the next execution start address is specified. The micro program process of (1) includes means for selecting and executing a micro step based on the data read from the micro ROM section. Therefore, in the past, the external terminal could be used only for the address input of the micro ROM at the time of the test, but by using the circuit of the present invention, the external terminal can be used for the input of the micro ROM address and the monitor of the control signal. Therefore, the number of terminals required for testing the micro ROM section can be reduced.

Further, if it is also used as an input / output terminal for a test signal of another functional block, two blocks can be tested at the same time, and the test time can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation during the normal operation in the first embodiment.

FIG. 3 is a timing chart for explaining an operation during a test in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional information processing apparatus.

[Explanation of symbols]

 11 instruction ROM 12 instruction register 13 micro ROM address register 14 micro ROM section 15, 20 latch circuit 16 number of bits of output of micro ROM section 17 control signal generation circuit 18 control signal 19 micro ROM address switching circuit 21 external terminal 22 ROM address Switching circuit 23 Test signal (TEST1) 24 Switching circuit 25 Internal circuit

Claims (3)

[Claims] 1. The contents of the instruction register are set in the microprogram ROM address register during normal operation,
The value is selected by the microprogram ROM address selection circuit to start execution of a series of microsteps peculiar to the instruction, and the contents of the start address are latched in the first latch circuit from the microprogram ROM section storing the microprogram. Then, the next address of the micro program ROM section is set in the micro program ROM register by the output of a predetermined bit of the latch circuit, and the address value of the predetermined micro step supplied from the external terminal at the time of the test is the second latch. In a microprogram type information processing device whose output signal is latched by a circuit and is selected by the microprogram ROM selection circuit in response to a test signal; in the test, based on an address value supplied from the external terminal Predetermined micro A means for designating only an execution start address of the gram processing, and for executing the microprogram processing following the execution start address, selecting and executing the next microstep based on the data read from the microprogram ROM section. An information processing device characterized by: 2. The means is the microprogram R
OM address selection circuit and the microprogram ROM
A micro program ROM address switching circuit and the micro program ROM register, and the micro program ROM address switching circuit responds to an instruction start signal at an instruction start timing.
Output of the latch circuit and the microprogram RO
2. The information processing apparatus according to claim 1, wherein at least one of the outputs of the M address selection circuit is selected and supplied to the micro ROM register. 3. After the execution start address given from the external terminal is latched by the second latch circuit,
The information processing apparatus according to claim 1, wherein the external terminal is used as either an input terminal or an output terminal of a predetermined signal.