JPS62278645A - Microcomputer - Google Patents

Abstract

PURPOSE:To ensure a test of a microcomputer with high efficiency by using a means which designates a micro-ROM address based on the address value supplied to an external input terminal in a test mode and executes selectively a microstep regardless of an execution flow of a series of microsteps proper to instructions through execution of instructions. CONSTITUTION:In a test mode the test signal is set at a high level and therefore a micro-ROM address selection switch circuit 19 selects the address value supplied from an external input terminal 20. Then the circuit 19 works regardless of the execution flow of a series of microsteps proper to instructions through execution of instructions and executes successively the microsteps designated by the input addresses. Therefore the addresses are successively supplied through the terminal 20 to execute repetitively only each microstep where each arithmetic action of an ALU is carried out in case a certain hardware, e.g., the ALU is checked. As a result, the ALU can be checked without executing all arithmetic instructions and therefore a test pattern is reduced.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a microprogram type microcomputer.

[Conventional technology]

FIG. 2 shows a block diagram of a conventional microprogram type micro combinator.

1 is instruction ROM, 2 is instruction register, 3 is micro EL
OM address register 4 is a micro ROM section which is composed of a decoder and a micro ROM. 5 is a latch circuit,
6 is a part (several bits) of the output of the latch circuit 5, which becomes the micro ROM address information of the primary micro step. 7
is a control signal generation circuit, and 8 is a control signal.

The operation of the prior art will be explained. The instruction code read from the instruction ROMx enters the instruction register 2, the contents of the instruction register 2 are transferred to the micro ROM address register 31C, and execution of a series of instruction-specific microsteps is started. The output of the micro) LOM address register 3 is input to the decoder of the micro ROM section 4, and when the micro ROM of the address is selected, the latch circuit 5 latches the output of the micro ROM section 4. Micro FLOM
4 stores control signal information to be output at each microstep, and a control signal generating circuit 7 outputs a control signal 8 based on the output of the latch circuit 5. On the other hand, the output 6 of several bits from the latch circuit 5 is input to the micro ROM address register 4, which determines the address of the micro ROM to be selected for the next micro step, and the micro step is subsequently executed. .

By repeating the above operations, a series of instruction-specific microprograms is executed.

The micro combinator test described above checks the hardware by executing instructions. For example, A
When checking the LU, the ALU should be checked by executing a series of microstep flows for all arithmetic instructions in the ALU and checking each arithmetic function.

[Problem that the invention seeks to solve]

In the above-mentioned microprogram-based microcombinator, when checking certain hardware during a test, it executes an instruction to operate the hardware, operates the hardware in a series of instruction-specific microstep flows, and then checks each piece of hardware. Checked the hardware by verifying functionality.

For example, in order to check hardware that executes multiple arithmetic instructions, it is necessary to perform the above operation for all arithmetic instructions. However, the flow of a series of microsteps for executing these instructions differs only in the microsteps that determine an arithmetic operation such as addition or subtraction, and the microsteps in the series are often the same.

Therefore.

This method had the disadvantage that the microstep flow was duplicated, resulting in a huge number of test clicks, which resulted in poor test efficiency.

[Failure to solve the problem]

The microprogram type microcomputer of the present invention specifies the micro ROM address based on the address value input to the external input terminal during testing, and the micro ROM address is specified based on the address value input to the external input terminal during testing, and the micro ROM address is specified based on the address value input to the external input terminal. It has means for selecting and executing steps.

〔Example〕

An embodiment of the present invention is shown in FIG. 1, and 11-18 have the same functions as the prior art components 1-8 shown in FIG. 1
9 is a micro ROM address selection switching circuit;
This circuit switches the address value set in the micro ROM address register 13 when the T signal is high level, and selects the address value input from 20 when the T signal is low level. Reference numeral 20 denotes an external input terminal, which is a terminal for inputting address values from the outside during testing.

The operation of this embodiment will be explained. During normal instruction execution, Tg
The ST signal is set to low level.

The instruction code read from instruction R, OMI 1 enters the instruction register 12, but since the TENT signal is low level, the contents of the instruction register 12 where the instruction is stored are transferred to the micro ROM address register 13, and the contents of the instruction register 12 are transferred to the micro ROM address register 13. The address selection switching circuit 19 is a micro ROM.
The address value set in the address register 13 is selected and execution of a series of instruction-specific microsteps is started.

Micro RO of the first address from the micro ROM section 14
M is read out, the latch circuit 15 reads out the micro ROM, and the latch circuit 15 latches the output of the micro 80M section 14, so the control signal generation circuit 17 outputs the micro ROM.
A control signal 18 is output based on the information stored in M. On the other hand, the output 16 of several pits of the latch circuit 15 is input to the micro ROM address register 13, the micro ROM address of the first micro step is determined, and the micro step is subsequently executed.

'rgs'r sets the TgST signal to high level ('rE8T signal is at high level, so the micro ROM address selection switching circuit 19 selects the address value input from the external input terminal 20. , is unrelated to the execution flow of a series of instruction-specific microsteps due to instruction execution (operation), and the microsteps specified by the input address are sequentially executed.

Therefore, when checking a piece of hardware such as an ALU, addresses can be input sequentially from the external input terminal so as to repeatedly execute only each microstep in which each arithmetic operation of the human LU is executed.

The test pattern is shortened because the ALU can be checked without executing all operation instructions.

〔Effect of the invention〕

As explained above, the present invention switches the address value selected by the micro ROM address selection switching circuit using the TB8T signal, and sequentially inputs the address values from the external input terminal. Since the microsteps can be operated independently of the flow, it is possible to check the microinstruction level directly related to the operation of the hardware, which has the advantage of shortening the number of test clicks and enabling efficient testing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprogrammed microcomviator according to the present invention. 11...Instruction ROM, 12...Instruction register, 13...Micro ROM address register, 14...Micro 8,0M section, 15...-
...... Latch circuit, 16... Several bits of the output of 15, 17... Control signal generation circuit, 18.
...-Control signal, 19...Micro ROM
Address selection switching circuit, 2o...external input terminal. FIG. 2 is a block diagram of a conventional microprogram type microcomputer. 1...Instruction ROM, 2...Instruction register, 3...Micro ROM address register,
4...Micro ROM section, 5...--Latch circuit, 6...Several bits of the output of 5, 7...
. . . Control signal generation circuit, 8 . . . Control signal. Agent: Susumu Uchihara, patent attorney, Figure 1

Claims (1)

[Claims] In microprogram-based microcomputers, during testing, the micromemory address is specified based on the address value input to the external input terminal, and a microstep is selected and executed regardless of the execution flow of a series of microsteps by executing instructions. A microcomputer characterized by having means for.