JPS5935245A - Pseudo fault generator - Google Patents

Abstract

PURPOSE:To generate a pseudo fault even under microinstruction execution, by generating the pseudo fault when the instruction code of a microprogram being executed coincides with a preset instruction code for the generation of the pseudo fault. CONSTITUTION:A desired pseudo fault switch SW among switches SW11 and a desired pseudo fault generation microinstruction code setting swith SW1 among switches SW4 are set. The setting of those SWs is possible regardless of whether a data processor 1 is in operation or not, and set values are changed during the operation. A microinstruction register output 2 from the processor 1 is stored in a microinstruction buffer register 3. The output of a pseudo fault generation microinstruction code register 5 having the SW4 set is compared with the output of the register 3 by a comparing circuit 8; when they coincide with each other, a pseudo signal generating circuit 10 is driven by a coincidence signal 9 to output a pseudo fault signal 12 set by the SW11 to the pseudo fault application point in the processor 1. The signal of ''1'' or ''0'' depending upon the circuit characteristic of the application point is generated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a pseudo-failure generation device, and particularly to a device for generating a pseudo-fault on a data processing device.

[Prior art]

Conventionally, methods for generating pseudo failures in data processing and storage include methods in which pseudo failures are obtained from the input/output terminals of backboards, packages, ICs, etc. within the data processing equipment or are injected using external circuits; The second method is to build in an error generation circuit in advance in the data processing device, and after setting it to test mode, generate an error with a pseudo-failure generation command.However, in the first method, there are no conditions for generating a pseudo-fault. Occurs at invalid timing because it cannot be selected 1. Or,
It had drawbacks such as not being able to target arbitrary microinstructions.

In addition, in the second method, a set of test modes and a pseudo failure instruction must be embedded in the program.
There was a drawback that required changes to the program.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a device that generates a pseudo failure during execution of any microinstruction without changing the program.

[Structure of the invention]

According to the first aspect of the present invention, the microinstruction register output indicating the instruction code of the microprogram being executed on the data processing device and the output of the pseudo failure microinstruction code register indicating the preset trigger point of the pseudo failure occurrence are output. a comparison circuit that compares microinstruction code information;
A pseudo-failure generation device is obtained, which includes a pseudo-fault generation circuit that generates a pseudo-fault in various circuits in the data processing device when the comparison circuit detects a match between microinstruction codes.

According to the second aspect of the present invention, the output of the macro instruction register indicating the instruction code of the macro instruction being executed on the data processing device and the pseudo-failure occurrence macro instruction code register indicating the trigger point of the preset pseudo-failure occurrence are output. a comparison circuit that compares macro instruction code information;
A pseudo-fault generating device is obtained, which includes a pseudo-fault generating circuit that generates a pseudo-fault in various circuits in the data processing device when the comparison circuit detects a match between macro instruction codes.

[Explanation of Examples]

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the first invention. Referring to FIG. 1, a microinstruction buffer register 3 for storing a microinstruction register output 2 from a data processing device 1, and a pseudo fault A pseudo failure micro instruction code register 5 that stores the output of the micro instruction code setting switch 4, a comparison circuit 8 that compares the outputs 6 and 7 of these two registers 3 and 5, and the comparison circuit 85- Under the control of the output 9 of the switch 11, the value of the switch for which a pseudo failure is to be generated is set to v'1'' in order to send the output of the pseudo failure setting switch 11 to the data processing device 1.The outputs of these switches 11 are The output 12 of the fault generation circuit 10 is connected to an arbitrary pseudo-fault injection point of the data processing device 1, and when the output 12 becomes 11 "or 0", it is arbitrarily connected to the pseudo-fault injection point according to the circuit characteristics of the pseudo-1 pseudo-fault injection point. You can choose.

Further, a microinstruction code for causing a pseudo failure is set in the pseudo failure microinstruction code setting switch 4. The switches 4 and 11 can be set while the data processing device 1 is in operation or stopped, and the set values can also be changed during operation.

Also, the outputs of switches 4 and 11 are set to 6- to prevent chatter. are temporarily stored in registers 5 and 10.

On the other hand, the microinstruction register output 2 from the data processing interposer 1 is stored in the microinstruction buffer register 3. Outputs 6 and 7 of registers 3 and 5 are compared in comparator circuit 8, and if they match, output 9 of comparator circuit 8 becomes '
1'', and the pseudo fault generation circuit 10 sends the output of the pseudo fault setting switch 11 to the data processing interposer 1.

The output of the pseudo fault generating circuit 10 is connected to a pseudo fault injection point in the data processing interposer 1, and a pseudo fault is generated when the output 12 becomes 11" or 0". Output 1
Whether a pseudo fault occurs when 2 is 11" or 0" depends on the circuit characteristics of the pseudo fault injection point of the data processing interposer 1.

In the above embodiment, the pseudo-fault generation microinstruction code and the pseudo-fault settings are obtained by using a switch. However, by providing a special interface between the data processing interposer 1 and this device, It is also possible to perform this according to the instructions in Section 1.

Further, in the first invention, a microprogram instruction code is used, but in the second invention, a macro instruction macro instruction code of one step higher is used in place of the microprogram address.

Furthermore, it is possible to have both the comparison circuit of the first invention and the comparison circuit of the second invention. If a match is detected only with

〔Effect of the invention〕

As explained above, the present invention also has the effect of generating a pseudo-failure during execution of any micro-instruction or macro-instruction without making any changes to the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the first invention. 1...Data processing interposition, 2...Micro instruction letter, 6...Output of register 3, 7...
...Register 5-9 = 6 / mouth

Claims (3)

[Claims] (1) Microinstruction code information output from the microinstruction register output indicating the instruction code of the microprogram being executed on the data processing device and the pseudo failure microinstruction code register indicating the trigger point for the preset pseudo failure occurrence and a pseudo fault generation circuit that generates a pseudo fault in various circuits in the data processing device when the comparison circuit detects a match between the microinstruction codes. A simulated failure generating device. (2) Macro instruction code information of the output of the macro instruction register output indicating the instruction code of the macro instruction being executed on the data processing device and the pseudo-failure occurrence macro instruction code register indicating the trigger point of the preset pseudo-failure occurrence. and a comparison circuit that compares the data, and when this comparison circuit detects a match between the macro instruction codes, the data
A pseudo-failure generation device comprising: a pseudo-fault generation circuit that generates pseudo-faults in various circuits within a processing device. (3) The microinstruction code of the output of the microinstruction register indicating the instruction code of the microprogram being executed on the data processing device and the pseudo failure microinstruction code register indicating the trigger point of the preset pseudo failure occurrence. a first comparison circuit that compares information; a macro instruction register indicating the instruction code of the macro instruction being executed on the data processing device; and a pseudo-failure occurrence macro instruction indicating a preset trigger point for the occurrence of a pseudo-failure. and a fourth and second comparison circuit that compares output macro instruction code information with the code register, and generates a pseudo failure only when a match is detected in the first and second comparison circuits. The pseudo-failure generating device according to claim 1, wherein the pseudo-failure generation device does not generate a pseudo-failure when only one comparison circuit detects a match.