JPH02187834A - Microprocessor - Google Patents

Abstract

PURPOSE:To efficiently and easily perform a life test for a high temperature accelerated operation by providing an address counter, a branch conditional register, and a test terminal. CONSTITUTION:A test pre-processing is performed by resetting the address counter 24 and setting the address 0 or a ROM 9 as a start address in a state where an MPU 1 is reset. An instruction is executed one after another by updating the counter 24 at every completion of an instruction 1. When the execution of the final instruction (m) is completed, a test post-processing is executed. In the post-processing, the counter 24 is changed to the address of the instruction 1. Thus, all the instructions of the MPU 1 can be executed sequentially only by activating a test mode signal ST at the test terminal 22, and the life test for the high temperature accelerated operation can easily be performed without adding an out-fitted pattern generator by performing such operation in a high temperature state.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to microprocessors.

[Conventional technology]

As microprocessors become more sophisticated and become more widespread, there is an increasing demand for improved reliability.

To ensure the reliability of microprocessors, accelerated life tests (so-called aging) are generally performed during the manufacturing process.
is being carried out.

Traditionally, this type of test has been performed with the power supply terminals of the microprocessor energized and heated.

In this case, the input terminal of the microprocessor was fixed at the power supply potential or the installation potential.

In addition, an accelerated operation life test @(
Operational aging) provided operational instructions to the microprocessor's terminals from an external pattern generator.

[Problem to be solved by the invention]

In the conventional microprocessor described above, the potential of the input terminal is fixed during the high temperature operation life test, so the internal circuit of the microprocessor hardly operates.

For this reason, the current flowing through the internal elements differs from the actual operating state, resulting in a disadvantage that the acceleration effect of the life test is reduced.

Furthermore, in order to perform an accelerated life test with internal elements in operation, an expensive external test device such as a pattern generator is required, which is economically disadvantageous.

Furthermore, even when this pattern generator is used, it is difficult to generate all the states of the microprocessor.

SUMMARY OF THE INVENTION An object of the present invention is to provide a microprocessor that can be easily subjected to high-temperature accelerated operation life tests.

[Means to solve the problem]

The microprocessor of the present invention includes a microcode ROM that inputs an address signal and outputs a microinstruction;
An arithmetic logic circuit controlled by the microinstruction, an address counter initialized by inputting a reset signal, and a counter signal of the address counter input by the test mode signal as a start address signal of the microcode ROM. a branch condition register initialized by a reset signal; means for making an output signal of the branch condition register input by a test mode signal a branch condition of the microcode ROM; and a branch condition register initialized by a reset signal; The branch condition register includes means for updating the address counter when the microinstruction at the highest address is completed, and means for updating the branch condition register when the microinstruction at the highest address is completed.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention.

The microprocessor 1 includes a microcode ROM 9 that inputs an address signal selected by an address selector 7 and outputs a microinstruction, an ALU 14 that is controlled by the microinstruction, and an address that is initialized by inputting a reset signal.・An address switching circuit 23 which switches the address switching circuit 23 according to the test mode signal ST inputted from the counter 24 and the test terminal 22 and uses the counter signal of the address counter 24 as the start address signal of the micro code ROM 9, and a reset signal. The branch condition register 28 is initialized and the branch condition switch circuit 27 is switched by the test mode signal ST.
a branch determination circuit 21 that uses the output signal of the micro-code ROM 9 as a branch condition; means for updating the address counter 24 at the time when the micro-instruction is completed; and a means for updating the address counter 24 at the time when the micro-instruction at the highest address is completed. and means for updating the branch condition register 28.

Here, the instruction decoder 3 receives the macro instruction signal S2 and generates and outputs a start address signal S6 for operating the micro code ROM 9.

First, when the test mode signal ST is made inactive, the address switching circuit 23 selects the start address signal S6 and specifies the start address of the microcode ROM 9.

Here, the microcode ROM 9 stores processing means for each instruction.

For example, in the case of an addition instruction, data in the register 13 is given to AL and U14 via the data bus 12, and an operation signal S15 representing the operation result is returned to the register 13 via the data bus 12.

At this time, the state of the calculation result, such as carry overflow, is stored in the flag 16 of the ALU from the calculation signal 815 of the ALU 14.

At this time, when the subsequent processing is selected depending on the state of the flag 16, the branch condition switching circuit 27 is configured to output flag information 31g to the branch condition signal S26.

Furthermore, a branch control signal S2 is sent from the microcode instruction S port.
0 is generated and judged by the branch judgment circuit 21, and when this predetermined condition is satisfied, a branch signal S25 is outputted to branch the control.

Next, when the test mode signal S is activated, the output of the address switching circuit 23 is switched to the address counter 2.
The branch condition signal 326 becomes the output information of the branch condition register 28.

FIG. 2 is a block diagram of the contents stored in the microcode ROM shown in FIG.

Here, while the microprocessor 1 is in the reset state, the address counter 24 is reset.

As a result, the test preprocessing is executed by setting address O of the microcode ROM 9 as the start address.

FIG. 3 is a flowchart for explaining the operation of the circuit shown in FIG.

By updating the address counter each time instruction i is completed, instructions can be executed one after another.

When the last instruction m is executed, post-test processing is executed next.

In post-processing, address counter 24 is updated to the address of instruction 1.

At the same time, the branch condition register 28 is updated to the next condition.

In this way, the test terminal 22 is connected to the test mode signal ST.
Just by activating it, all the instructions of the microprocessor can be executed sequentially, and if this operation is performed under high temperature conditions,
High-temperature accelerated operation life tests can be easily performed without adding an external pattern generator.

Note that if the microprocessor of this embodiment is mounted on a plurality of printed circuit boards and each light emitting diode is caused to emit light using the signal that updates the address counter 24 shown in FIG. 1, each microprocessor will execute an instruction. You can visually confirm that it is.

〔Effect of the invention〕

As described above, the present invention has the effect of realizing a microprocessor that can efficiently and easily perform a high-temperature accelerated operation life test by providing an address counter, a branch condition register, and a test terminal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a configuration diagram of the memory contents of the microcode ROM shown in FIG. 1, and FIG. 3 is a flowchart for explaining the operation of the circuit shown in FIG. 1. It is. l...Microprocessor, 3...Instruction decoder,
7... Address selector, 8... Address latch, 9... Micro code ROM, 10... Latch, 12... Data bus, 13... Register, 14
...ALU, 17...Arithmetic control circuit, one...
- Branch control circuit, 21... Branch judgment circuit, 23...
Address switching circuit, 24...Address counter, 2
7... Branch condition switching circuit, 28... Branch condition register, S2... Macro instruction signal, S4... Address signal, S6... Start address signal, Sll... Micro code instruction , S20...branch control signal, S25
... Branch signal, S26... Branch condition signal.

Claims (1)

[Claims] A microcode ROM that inputs an address signal and outputs a microinstruction, an arithmetic logic circuit controlled by the microinstruction, an address counter initialized by a reset signal, and the address inputted by a test mode signal.・The counter signal of the counter is
means for making the start address signal of the code ROM; a branch condition register initialized by a reset signal; and means for making the output signal of the branch condition register input by the test mode signal the branch condition of the micro code ROM. and means for updating the address counter at the time when the microinstruction at the highest address is completed; and means for updating the branch condition register at the time when the microinstruction at the highest address is completed. .