JPH05158853A - Channel connecting mechanism - Google Patents

Abstract

PURPOSE:To improve a reliability by carrying out the pseudo evaluation of a processing from a control processor which is not actually connected with a channel connecting mechanism. CONSTITUTION:At the time of receiving the number information of a control processor 40 for the pseudo evaluation which is not actually connected, an interface control part 70 sets a corresponding flag from a flag group 72, and communicates it to an analysis processing part 60. In the analysis processing part 60, the content of the communicated flag is copied to a copy register 62, and the number information of the control processor 40 for the pseudo evaluation is stored in a pseudo number register 63, so that the start of a diagnosis can be prepared. When a diagnosis instruction signal is set at the analysis processing part 60, a diagnosis processing part sets the flag of the control processor indicated in the pseudo number register 63 as a copy flag, and operates the data processing of the control processor 40 for the pseudo evaluation. Thus, the diagnosis of the control processor 40 which is not actually connected can be attained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a channel connection mechanism capable of connecting a plurality of control processors, and more particularly to a method of diagnosing processing from a control processor not actually connected to the channel connection mechanism.

[0002]

2. Description of the Related Art Conventionally, in this type of channel connection mechanism,
It was possible to evaluate whether the instruction from the control processor actually connected was processed correctly, but it was impossible to evaluate whether the instruction from the control processor not actually connected was processed correctly. . for that reason,
Either the currently connected control processor is connected to another to be evaluated, or another control processor is connected to be evaluated, or an alternative device that looks like a control processor is created and connected to it for evaluation. It was

[0003]

However, according to such a conventional method, when the currently connected control processor is connected to another for evaluation, one by one in every connectable case. Since evaluation is required, there are problems that it takes man-hours for connection and that competition evaluation cannot be performed sufficiently. Further, if another control processor is prepared or a pseudo control processor is created, there is a problem that the cost is increased and a great number of man-hours are required for the creation process.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a channel connection mechanism which does not require a connection processor of a control processor or a pseudo control processor and a manufacturing process.

[0005]

The channel connection mechanism of the present invention is connected between a host system, a control processor that performs processing based on data from the host system, and the host system and the control processor. In a data processing system including a channel connection mechanism for controlling data transfer between the host system and the control processor and enabling a plurality of connections of the control processor, data with the host system is stored in the channel connection mechanism. A host interface control unit for controlling transfer, an analysis processing unit for analyzing data from the host system and data from the control processor, an interface control unit for controlling data transfer with the control processor, and each of the control processors It is set when receiving data from the control processor A flag group, a means for notifying the analysis processing unit when an arbitrary flag of the flag group is set, a copy register for reading the contents of the flag group and copying the contents, and the control processor When receiving the number information of the connected control processor, it stores the information, and when receiving the number information of the control processor which is not actually connected and which is to be evaluated in a pseudo manner, it stores the information. A pseudo number register, a diagnostic instruction signal that is set when a diagnostic instruction is received from the control processor, the flag is arbitrarily set when the diagnostic instruction signal is set, the contents of the flag group are read, and the copy register is read. When resetting, the control processor flag indicated in the configuration number register is reset. And a diagnosis processor which sets the copy flag and sets the flag of the pseudo number control processor shown in the register.

Further, in the channel connection mechanism, a host interface control unit for controlling data transfer with the host system, an analysis processing unit for analyzing data of the host system and data from the control processor, and the control processor. An interface control unit for controlling data transfer between the control processor, a flag group which is provided for each control processor and is respectively set when data is received from the control processor, and when any flag of the flag group is set, When a means for notifying the analysis processing unit, a copy register for reading the contents of the flag group and copying the contents, and the number information of the control processor to be pseudo-evaluated that is not actually connected from the control processor are received. A pseudo number register that stores that information and a diagnostic number from the control processor. Buffer for storing a diagnostic command for receiving a diagnostic command for use, a diagnostic instruction signal that is set when a diagnostic instruction is received from the control processor, and the flag is arbitrarily set when the diagnostic instruction signal is set. When the contents of the flag group are read and copied to the copy register, a diagnostic processing unit that sets the flag of the control processor indicated in the pseudo number register and sets the copy flag, and the diagnostic instruction signal are set. In addition, when the analysis processing unit is decoding the flag of the control processor indicated in the pseudo number register, it has means for fetching the contents of the diagnostic buffer into the analysis processing unit.

In the channel connection mechanism, there are provided a host interface control unit for controlling data transfer with the host system, an analysis processing unit for analyzing data of the host system and data from the control processor, and the control processor. An interface control unit that controls data transfer, a flag group that is provided for each control processor and is set when receiving data from the control processor, and notifies the analysis processing unit when an arbitrary flag is set. Means, a copy register for reading the contents of the flag group and copying the contents, and a pseudo register for storing the number information of a control processor which is not actually connected and which is to be evaluated in a pseudo manner from the control processor. Number register and diagnostic command for diagnostics from the control processor When receiving a diagnostic buffer that stores the diagnostic command when received, a diagnostic instruction signal that is set when a diagnostic instruction is received from the control processor, and timing information that determines when the diagnostic instruction signal becomes valid from the control processor. A timer register in which the information is stored, a means for decrementing the timer register, a valid signal indicating the validity of the diagnostic instruction signal set when the content of the timer register becomes zero, the diagnostic instruction signal and the When a valid signal is set, the flags are arbitrarily set, and when the contents of the flags are read and copied to the copy register, the flag of the control processor indicated in the pseudo number register is set to the copy flag. Set the diagnostic processing unit to be copied and the diagnostic instruction signal It has been, and a means for capturing the contents of the diagnostic buffer to the analysis processing unit when the analysis processing unit is decoding a flag of the control processor shown in the pseudo number register.

[0008]

According to the above configuration, when the interface control unit for controlling the data transfer from the control processor receives from the control processor the number information of the control processor which is not actually connected and is to be evaluated in a pseudo manner, it is detected from the flag group. The corresponding flag is set and notified to the analysis processing unit.The analysis processing unit copies the content of the notified flag to the copy register and stores the number information of the control processor to be pseudo evaluated in the pseudo number register. Prepare to start diagnosis. When the diagnostic instruction is issued from the control processor and the diagnostic instruction signal is set in the analysis processing unit based on the diagnostic instruction, the diagnostic processing unit sets the flag of the control processor indicated in the pseudo number register to be pseudo as a copy flag. Since the data processing of the control processor to be evaluated is performed, it is possible to diagnose the control processor which is not actually connected but is to be evaluated in a pseudo manner.

Alternatively, when the interface control unit issues a diagnostic command of the control processor to be pseudo-evaluated from the control processor, the issued diagnostic command is stored in the diagnostic buffer, and the diagnostic buffer is used during the diagnostic process in the analysis processing unit. Since the data stored in is processed as received data, it is possible to diagnose a control processor which is not actually connected and which is to be pseudo-diagnosed from the content of the diagnostic command from the control processor.

Alternatively, in the analysis processing section, timing information for determining when the diagnostic instruction signal from the control processor becomes valid is stored in the timer register, and the timer register is decremented. Since the valid signal to be valid is set, it is possible to diagnose the control processor which is not actually connected and which is to be pseudo-diagnosed, based on the timing preset input from the control processor.

[0011]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a channel connection mechanism which is an embodiment of the present invention.

In FIG. 1, 10 is a host system and 3
Reference numeral 0 represents a control processor A that is actually connected, reference numeral 40 represents a control processor B that is pseudo-diagnosed and is not actually connected, and reference numeral 20 is a channel that connects the host system 10 and the control processor A30 to control data transfer. The channel connection mechanism 20 is composed of an interface control unit such as a host interface control unit 50, an analysis processing unit 60, and a control processor A30 70.
The interface control unit 70 has a transmission / reception buffer 71 and a flag group 72 corresponding to a control processor, and the analysis processing unit 60 analyzes the contents of the microprocessor 61 and the flag group 72 that analyze various data and perform analysis control such as diagnostic processing. A copy flag 62 to be copied in accordance with an instruction from the microprocessor 61, and a pseudo number register 6 for storing a pseudo configuration number and an alternative configuration number of each control processor in the case of diagnostic processing.
3 and an alternative number register 64 are included in the entire structure.

Next, the operation will be described.

In order to make the explanation more concrete, the channel connection mechanism 20 is connectable to four control processors (four control processors are respectively assigned configuration numbers for convenience, and the control numbers are 1, from the left of the figure. 2, 3, and 4, that is, the control processor A has a configuration number 1 and the control processor B has a configuration number 2). Actually, only one of the control processors A30 is connected as shown in FIG.

It is attempted to diagnose whether the channel connection arrangement 20 can correctly process the data from the control processor B40 which is not actually connected.

First, the configuration number that the control processor A30 wants to diagnose in a pseudo manner (configuration number 2 because it is the control processor B40 this time) and the configuration number that is actually connected to substitute for it (configuration number 1 because it is the control processor A30). The data is transmitted to the channel connection mechanism 20.
When the above data is transmitted from the control processor A30,
The data is stored in the transmission / reception buffer 71 for the control processor A30 in the interface control unit 70, and at the same time, the flag for the control processor A30 in the flag group 72 is set. When this flag is set, the microprocessor 61 in the analysis processing unit 60 is notified and the content of the flag group 72 is copied to the copy flag 62.
Based on the contents of the copy flag 62, the microprocessor 61 identifies from which control number of the control processor the data was received. When it is recognized that the data is received from the control processor A30, the configuration number of the control processor is stored, the data is read from the transmission / reception buffer 71 for the control processor A30, and the received data is analyzed. As a result of the analysis, when it is recognized that the data is to the host system 10, the data is transferred to the host system 10 via the host interface control unit 50. When the pseudo configuration number for the pseudo diagnosis and the alternative configuration number are recognized, "2" is stored in the pseudo number register 63, and the alternative configuration number is stored in the alternative number register 64, "1".

Next, the control processor A30 issues a pseudo diagnosis start command to the channel connection mechanism 20 in order to start the pseudo diagnosis. The microprocessor 61 confirms whether there is any other flag set in the copy register, and if there is another flag set, it identifies which configuration number of the control processor flag. If no other flag is set, the contents of the flag group 72 are copied again to the copy flag. Based on the copy flag, data is read from the transmission / reception buffer 71 for the control processor A30, and when the microprocessor 61 recognizes it as a pseudo diagnosis start instruction, the microprocessor 61 sets a pseudo diagnosis signal (diagnosis instruction signal) 65.

After that, when an instruction is received from the control processor A30 and the microprocessor 61 copies the contents of the flag group to the copy register 62, the flag of the corresponding control processor B40 of the pseudo number register 63 is set to substitute. The flag of the corresponding control processor A30 of the number register 64 is reset and then copied to the copy flag 62.

The microprocessor 61 decodes the flag of the control processor B40, and the control processor B40
When the data is read from the transmission / reception buffer 71 for control, the number of the decoded control processor matches the pseudo number register 63. Therefore, the control processor B40
Control processor A3 instead of the transmission / reception buffer 71 for
Data is read from the 0 transmission / reception buffer 71.
The microprocessor 61 analyzes the data and processes it as received data from the control processor B40 that is pseudo connected.

Next, a second embodiment of the present invention will be described.

FIG. 2 is a block diagram of a channel connection mechanism according to the second embodiment of the present invention.

In the figure, numeral 73 is a diagnostic buffer for storing issued diagnostic commands.

In the second embodiment, in the embodiment shown in FIG.
The control processor A30 substitutes for the configuration number to be pseudo-diagnosed, and instead of transmitting the actually connected configuration number as data to the channel connection mechanism 20,
Channel connection mechanism 2 is used to issue diagnostic commands that you want to simulate.
Issue to 0. When the microprocessor 61 analyzes the data and recognizes that the data is a diagnostic command for diagnosis, the microprocessor 61 stores the diagnostic command in the diagnostic buffer 73 in the interface control unit 70.

Further, the microprocessor 61 receives a command from the control processor A30 after setting the pseudo diagnosis signal (diagnosis instruction signal) 65, and the microprocessor 6
When 1 copies the content of the flag group to the copy register 62, the flag for the corresponding control processor B40 of the pseudo number register 63 is set and then copied to the copy flag 62. When the microprocessor 61 decodes the flag of the control processor B40 and tries to read the data from the transmission / reception buffer 71, the decoded control processor number matches the pseudo configuration number register. Data is read from the buffer 73. The microprocessor 61 analyzes the data and processes it as received data from the control processor B40 that is pseudo connected.

Next, a third embodiment of the present invention will be described.

FIG. 3 is a block diagram of a channel connection mechanism according to the third embodiment of the present invention.

In the figure, 66 is a timer register for storing timing data, and 67 is a valid signal for validating the pseudo diagnostic signal.

In the third embodiment, even if the microprocessor 61 sets the pseudo diagnosis signal (diagnosis instruction signal) 65 in the second embodiment of FIG. 2, that signal is not effective. To enable it, the control processor A30
Issues timing information for the pseudo diagnostic number to the channel connection mechanism 20. When the microprocessor 61 analyzes the data and recognizes that the data is timing data, the microprocessor 61 sets the data in the timer register 66.

The value of the timer register 66 is decremented.

When the content of the timer register becomes zero,
The valid signal 67 is set and the pseudo diagnostic signal 65 becomes valid. After that, similarly, when the microprocessor 61 decodes the flag of the control processor B40 and tries to read the data from the transmission / reception buffer 71, the decoded control processor number matches the pseudo configuration number register. Data is read from the diagnostic buffer 73 instead of. The microprocessor 61 analyzes the data and processes it as received data from the control processor B40 that is pseudo connected.

[0032]

As described above, according to the present invention, it is possible to evaluate whether or not an instruction from a control processor that is not actually connected to the channel connection mechanism has been correctly processed, so that the reliability is improved. is there. Further, since a control processor is not separately created or a pseudo control processor is not created, there is an effect that the number of preparation steps is not required.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a channel connection mechanism according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a channel connection mechanism according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a channel connection mechanism according to a third embodiment of the present invention.

[Explanation of Codes] 10 host system 20 channel connection mechanism 30 control processor A 40 control processor B 50 host interface control unit 60 analysis processing unit 61 microprocessor 62 copy register 63 pseudo number register 64 alternation number register 65 pseudo diagnostic signal 66 timer register 70 interface control unit 71 transmission / reception buffer 72 flag group 73 diagnostic buffer 67 valid signal

Claims (3)

[Claims] 1. A host system, a control processor that performs processing based on data from the host system, and a data transfer between the host system and the control processor, which is connected between the host system and the control processor. In a data processing system provided with a channel connection mechanism capable of connecting a plurality of control processors, in the channel connection mechanism, a host interface control unit for controlling data transfer with a host system, data from the host system, An analysis processing unit that analyzes data from the control processor, an interface control unit that controls data transfer with the control processor, and a flag group that is provided for each control processor and is set when data is received from the control processor. , Any flag of the flag group is set And a means for notifying the analysis processing unit, a copy register for reading the contents of the flag group and copying the contents, and the information when the configuration number information of the control processor actually connected is received from the control processor. A configuration number register for storing, a pseudo number register for storing the number information of the control processor which is not actually connected from the control processor but is desired to be evaluated, and a pseudo number register for storing the information when the diagnostic instruction is received from the control processor. And a flag of the control processor indicated in the configuration number register when the flag is arbitrarily set and the contents of the flag group are read and copied to the copy register when the diagnostic instruction signal is set. To reset the control processor flag shown in the pseudo number register. The sets by providing a diagnostic unit to be set in the copy flag, actually connected to the control processor does not process the channel connecting mechanism, wherein a diagnosis that can be of. 2. A host interface control unit for controlling data transfer with a host system, an analysis processing unit for analyzing data from the host system and data from the control processor, and the control in the channel connection mechanism. An interface control unit for controlling data transfer with a processor, a flag group which is provided for each control processor and is set when data is received from the control processor, and an analysis process when an arbitrary flag of the flag group is set And a copy register for reading the contents of the flag group and copying the contents, and receiving the number information of the control processor which is not actually connected but is desired to be evaluated from the control processor. A pseudo number register to store and a diagnostic code for diagnostics from the control processor. Buffer for storing a diagnostic command when the diagnostic command is received, a diagnostic instruction signal that is set when a diagnostic instruction is received from the control processor, and the flag is arbitrarily set when the diagnostic instruction signal is set. When the contents of the group are read and copied to the copy register, a diagnostic processing unit that sets the flag of the control processor indicated in the pseudo number register and sets the copy flag; and the diagnostic instruction signal is set, When the analysis processing unit is decoding the flag of the control processor indicated in the pseudo number register, the control unit that is not actually connected is provided by providing a unit for fetching the contents of the diagnostic buffer into the analysis processing unit. Channel connection according to claim 1, characterized in that the processing of the processor can be diagnosed. Structure. 3. A host interface control unit for controlling data transfer with a host system, an analysis processing unit for analyzing data of the host system and data from the control processor, and the control processor in the channel connection mechanism. An interface control unit for controlling data transfer between the control processor, a flag group provided for each control processor and set when data is received from the control processor, and means for notifying the analysis processing unit when an arbitrary flag is set A copy register into which the contents of the flag group are read and whose contents are copied; and a pseudo number register which stores the information when the number information of the control processor which is not actually connected but is desired to be evaluated is received from the control processor. When a diagnostic command for diagnosis is received from the control processor, A diagnostic buffer for storing a diagnostic command of the information, a diagnostic instruction signal that is set when a diagnostic instruction is received from the control processor, and timing information that determines when the diagnostic instruction signal becomes valid from the control processor. Is stored, a means for decrementing the timer register, a valid signal indicating the validity of the diagnostic instruction signal which is set when the content of the timer register becomes zero, the diagnostic instruction signal and the valid signal When is set, the flag is arbitrarily set, and when the contents of the flag group are read and copied to the copy register, the flag of the control processor indicated in the pseudo number register is set and copied to the copy flag. The diagnostic processing unit and the diagnostic instruction signal are set. When the analysis processing unit is decoding the flag of the control processor indicated in the pseudo number register, the means for fetching the contents of the diagnostic buffer into the analysis processing unit is not provided so that the connection is not actually made. 3. The channel connection mechanism according to claim 2, wherein the processing of the control processor can be diagnosed.