JP2972190B1 - CPU high-speed processing circuit - Google Patents

Abstract

Abstract: [PROBLEMS] To create a program extremely easily while using a method of achieving high-speed processing using a plurality of CPUs. The CPU has the same processing speed as the CPU 0, CPU 1,...
Improve using n. The software such as CPU0 and the circuit blocks 1, 2, and 3 sequentially start each CPU with a time difference, thereby reducing the waiting time of each CPU and sequentially putting the outputs obtained with the time difference on the data bus. By doing so, the processing cycle is speeded up as compared with the CPU alone.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention]

The present invention provides a C for improving the processing speed of the CPU.
The present invention relates to a high-speed processing circuit of a PU.

[0002]

2. Description of the Related Art Parallel processing such as parallel arithmetic and pipeline processing is well known as a technique for increasing the processing speed of a CPU. There is also a method of distributing a plurality of CPUs in a parallel configuration.

[0003]

However, in the case of the parallel algorithm, a special algorithm for reducing the number of calculations is required, and the number of instructions for executing the algorithm is enormous. Also, multiple CPUs
For the distributed processing with the parallel configuration of
Not only does the processing content of the PUs differ, but depending on how the calculation / processing is divided, some CPUs have a waiting time,
To eliminate the waiting time, a special program is required for each CPU. This is the same in the case of pipeline processing. In short, in order to achieve high-speed processing of the CPU, the cost of program development becomes large, which is a major problem.

The present invention has been made in view of the above background, and has as its object to create a program extremely easily, while using a method for achieving high-speed processing using a plurality of CPUs. An object of the present invention is to provide a high-speed processing circuit of a CPU.

[0005]

According to the high-speed processing circuit of the CPU of the present invention, the processing speed of the CPU is controlled by the same n (n.gtoreq.2) CPUs 1 _and CP having the same program installed.
U2... A circuit to be improved using CPUn,
CPU1 _, CPU2... Authorization codes 1 and 2 for CPUn
.., N for providing n as initialization data, and processing / processing in CPU1 _, CPU2,.
Means for inputting a start axis permission code before inputting data necessary for performing an operation, determining whether or not the code matches the initialized own permission code, and performing data input only when the match is obtained; CPU1 _, CPU2 ... CP
When data input is completed at Un, and means for outputting the input operation check signal from said CPU, a means for sequentially outputting the input operation starting shaft authorization code 1, 2 · · · n receives the input operation check signal, CPU _1, CPU2 ... CPU
n, when the processing / computation is completed, means for outputting an output start signal from _the CPU, CPU1 _, CPU2,.
.. Receiving output start signals from CPUn and sequentially outputting output axis permission codes 1, 2,.
When the processing / calculation is completed in PU1 _, CPU2,... CPUn, a means for outputting an output start signal from the CPU _, and an output axis permission code 1, in response to the output start signal output from CPU1 _, CPU2,. 2 ...
. Means for sequentially outputting n, CPU1 _, CPU2,...
Before outputting data indicating the result of the processing / calculation in the CPUn, the starting axis permission codes are input, and it is determined whether or not the initialized own permission codes match,
Means for outputting data only when they match, and a CPU
1 _, CPU2... Means for placing data output from each of the CPUs on a data bus.

The operation of the CPU generally has a flow of fetch, decode, processing / operation, and output. A series of programs are executed by repeating this operation cycle. Since the fetch operation does not start until the output operation is completed, this cycle can be said to be the minimum unit of the processing speed of the CPU.

Looking at these operations at the level of hardware or machine language, the fetch operation is in a waiting state when, for example, the decoding operation is started. The circuit of the present invention is, so to speak, constructed so as not to make such a waiting time. That is, by sequentially starting the n CPUs with a time difference, the waiting time of each CPU is reduced, and
By sequentially putting outputs obtained by the processing / calculation of U on the data bus, the processing cycle can be sped up as compared with the case of using only the CPU.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a configuration diagram of a high-speed processing circuit of the CPU, FIG. 2 is a flowchart showing a flow of a program processed by each CPU of the circuit, and FIG. 3 is a timing chart of main signals of the circuit.

[0009] In this circuit, the processing speed of the CPU is controlled by the same (n + 1) CPs with the same program installed.
U0, CPU1,... Are circuits that are improved using CPUn, and are mounted on a CPU board or the like.

The circuit includes CPU0, CPU1,.
.., N as initialization data, and CPU0, CPU1,.
-Before starting data input necessary for performing processing / calculation to CPUn, input the start axis permission code, and determine whether or not it matches the initialized own permission code. Means B for performing the operation and the CPU
0, CPU1,..., CPUn, when data input is completed, means C for outputting input operation confirmation signals from CPU0, CPU1,. 2 ...
n for sequentially outputting n, CPU0 _, CPU1,...
When the processing / operation is completed in the CPUn, the CPU
Means for outputting an output start signal from the CPU 0 _, C
PU1,... Means F for sequentially outputting output axis permission codes 1, 2,... N in response to the output start signal output from CPUn, and data indicating the results of processing / calculation in CPU0 _, CPU2,. Means for inputting the start axis permission codes before outputting the data, determining whether or not the initialized own permission codes match, and outputting data only when the codes match, and CPU0 _, CPU1,...
A means H for placing the data output from the CPUn on the data bus;

Means B, C, E and G are:
CPU0, CPU1,... Are realized by programs installed in CPUn, and the means D, F, and H are realized by newly added hardware. Means A is realized by both a program and hardware.

CPU0 _, CPU1,..., CPUn are connected in parallel, and sequentially process programs shown in FIG. 2 recorded in a memory (not shown). CPU0
_, CPU1 ... Part of each I / O port of CPUn
INISIG input terminal, STR-CODE input terminal, I
END output terminal, OUT-CODE input terminal, and / WR terminal are respectively assigned.

CPU0 _, CPU1,... Each I of CPUn
The NISIG input terminals include DIP0, DIP1,.
DIPn are connected to each other. Here, DIP0, D
Numerical data of 0, 1,... N is output from IP1. As a result, CPU0 _, CPU1
.. Permission codes 0, 1,... N are assigned to CPUn, respectively.

The reason why the permission code needs to be assigned to each CPU is that since the programs installed in each CPU are the same, it is not possible to recognize the axis of the CPU itself. .

Circuit blocks 1, 2, and 3 are also added as peripheral circuits of CPU0 _, CPU1,..., CPUn.

The circuit block 1 selects and outputs each input operation completion signal output from the IEND output terminal of the CPU according to the start axis permission code, and receives the output signal of the selector 12 as a clock. The counting result is output as a start axis permission code (n + 1)
It comprises a bit counter 11.

The processing cycle of the CPU can be divided into three stages: input, operation / processing, and output, but the minimum processing speed unit t is not uniquely determined by the contents of the program and the operation / processing. Therefore, a command for sequentially starting the operation of each CPU cannot be unilaterally issued from other than the CPU. For this reason, a circuit block 1 is needed to keep pace with the input operation of each CPU. In other words, the circuit block 1 functions as a distribution circuit.

The circuit block 2 selects the output start signal (WR signal) output from the / WR terminal of the CPU according to the output axis permission code and outputs the selected signal. The output signal of the selector 12 is input as a clock. And the counting result is output as an output axis permission code (n + 1).
It comprises a bit counter 21.

The circuit block 3 includes an OR circuit 31 to which each data output from the data terminal of the CPU is input,
Latch circuit 3 for synchronizing data output from R circuit 31 with an output signal of selector 12 and outputting the data to a data bus
3 is comprised.

As described above, since the minimum processing speed t of the CPU is not uniquely determined, the timing of latching the data output from each CPU on the data bus is not uniquely determined. Therefore, circuit blocks 2 and 3 are required to keep pace with the output operation of each CPU and to put the data output from each CPU on one data bus. In other words, the circuit blocks 2 and 3 function as a synthesis circuit.

The programs processed in each CPU are as shown in FIG. The contents of this program will be described, and the operation of this circuit will be described.

First, when the power is turned on, initialization is performed. This initialization includes input of data of permission codes 0, 1,..., N (S1). Thereafter, a start axis permission code is input (S2), and it is determined whether or not the input code matches the permission code assigned to the self (S3).

If the input start axis permission code does not match the permission code assigned to itself, step 2 is processed again, and steps 2 and 3 are repeated until a match is found, and the apparatus enters a standby state. On the other hand, if they match, data as a prerequisite for processing / calculation is input (S4).
When the input is completed, an input operation completion signal is output (S
5).

When the input operation completion signal is output,
The start axis permission code output from the circuit block 1 is counted up. That is, the start axis permission code is output to the next CPU, and the input operation is started for the CPU.

Thereafter, processing / calculation is performed based on the input data (S6). When this is completed, an output start signal is output as soon as data output becomes possible (S7), and an output axis permission code is input. (S8) It is determined whether or not the input code matches the permission code assigned to itself (S9).

When the output start signal is output, the output axis permission code output from the circuit block 2 is counted up. That is, the output axis start code is output to the next CPU, the start axis permission code is output, and the output operation is started for the CPU as described below.

If the input output shaft permission code does not match the permission code assigned to itself, step 8 is processed again, and steps 8 and 9 are repeatedly processed until the output shaft permission code matches, and the apparatus enters a standby state. On the other hand, if they match, data as a result of the processing / calculation is output (S10).

When data is output, the data is output via the data bus by the function of the circuit block 3.

When the data output is completed, the flow returns to step 2 again, and thereafter, the same processing as described above is repeatedly performed.

Since such a program is processed by each CPU, each CPU operates as shown in FIG. 3, and the processing is performed at a period exceeding the minimum processing speed unit t obtained by the CPU alone.

The high-speed processing circuit of the CPU according to the present invention is not limited to the above-described embodiment. For example, the circuit blocks 1, 2, and 3 may have any circuit configuration as long as they have the same function.

[0032]

As described above, in the case of the high-speed processing circuit of the CPU according to the present invention, although a method for achieving high-speed processing using a plurality of CPUs, it is only necessary to add simple instructions to a basic program. Moreover, since each CPU is configured to process the same program,
It is extremely easy to create a program as compared with the conventional method, and the cost of program development can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram for describing an embodiment of the present invention, and is a configuration diagram of a high-speed processing circuit of a CPU.

FIG. 2 is a flowchart showing a flow of a program processed by each CPU of the circuit.

FIG. 3 is a timing chart of main signals of the circuit.

[Explanation of symbols]

 CPU0 to CPUn 1,2,3 circuit block

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-9-204215 (JP, A) JP-A-9-6425 (JP, A) JP-A-8-106312 (JP, A) JP-A-8-204 76823 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G06F 15/177 670 G05B 19/414 JICST file (JOIS)

Claims (1)

(57) [Claims] 1. The processing speed of a CPU is set to the same n (n ≧ 2) CPUs 1 _and 2 with the same program installed _.
CPU2, a high-speed processing circuit of the CPU which is improved by using CPUn, CPU1 _, CPU2, CPU
means for providing each of n in the authorization code 1, 2 · · · n as Nisha rise _{data, CPU1,} CPU2 ··· CP
Before inputting data necessary for performing processing / operation at Un, a start axis permission code is input, and it is determined whether or not the start axis permission code coincides with the initialized self permission code. Means for causing CPU1 _,
CPU2... CPUn, when data input is completed, means for outputting an input operation confirmation signal from the CPU, and means for receiving the input operation confirmation signal and sequentially outputting input operation start axis permission codes 1, 2,. And CPU1 _, C
PU2... Means for outputting an output start signal from the CPU when the processing / calculation is completed in the CPUn;
CPU1 _, CPU2... CPUn receiving output start signals output from CPUn, and sequentially outputting output axis permission codes 1, 2,... N, and CPU1 _, CPU2.
Means for inputting a starting axis permission code before outputting data indicating a result of processing / operation, determining whether or not the initialized own permission code matches, and outputting data only when it matches. And CPU1 _and CP
U2... CPU comprising means for placing data output from each of CPUn on a data bus
High-speed processing circuit.