KR940006818B1 - Gate array internal logic scan system - Google Patents

Abstract

The system improves the test accuracy of the logic scanner system to add the gate array test circuit. The system comprises; multiple register loops (17-19) set for the internal loop back test; a first multiplexer (16) outputting the multiple register signals; decoding units (15,20) providing the selection control signal of the multiplexer; a test logic (1) set in the gate array; a logic control unit (14) connected with a microprocessor (3); and a counter unit outputting the counter results to the logic control unit.

Description

Gate Array Internal Logic Scan System

1 is a block diagram of a gate array internal logic scan system according to the present invention.

2 is a configuration diagram of the scan control circuit of FIG.

3 is a diagram illustrating the test logic of FIG.

4 is a detailed configuration diagram of the register loop of FIG.

* Explanation of symbols for main parts of the drawings

1: test logic 2: scan control circuit

3: microprocessor 4: memory

10: address register 11: multiplexer

12: data register 13: counter

14: logic control circuit 15: address decoder

16: multiplexer 17,18,19: register loop

20: sub address decoder 21,22,23; register.

The present invention relates to a gate array internal logic scan system for detecting abnormalities of internal structures of a custom chip and a gate array.

Conventionally, a gate array is applied by applying an address, data, and control signal to an input side of a gate array to obtain a desired result value on the output side, or by writing data to a memory element area such as an internal register and reading it back to find whether the result value is the same. Judging whether there was an abnormality.

However, in the conventional test method, the accuracy of fault check of internal logic is determined according to a diagnostic program, and the search method according to the front end program is limited as the density of a custom chip such as a gate array is increased. There was this.

An object of the present invention is to provide a gate array internal logic scan system that improves test accuracy by adding circuits for testing to custom chips and gate arrays.

In order to achieve the above object, the present invention provides a gate array internal logic scan system that includes a microprocessor, and detects the abnormality of the internal logic of the custom chip and the gate array; A plurality of register loops installed inside the custom chip and gate array for loopback testing, a first multiplexer for selecting and outputting output signals of the plurality of register loops, and receiving and decoding an address from the microprocessor And a decoding means provided as a selection control signal of a multiplexer, wherein the test logic is provided in a plurality of test chips and inside the custom chip and the gate array, a logic control means connected to the microprocessor, and the test logic according to the control of the logic control means. Multiplexing means for selecting one of the loop test signal output from a plurality, Counter means for down counting the count value received from the microprocessor under the control of the logic control means to output a counting result to the logic control means, The microA data register which receives a test data pattern from a processor, receives the output of the multiplexing means, shifts it serially according to a control signal of the logic control circuit, and transfers it to a register loop in the test logic; And an address register for outputting the address signal to the decoding means in the test logic in accordance with the control signal of the logic control means.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

1 is a block diagram of a gate array internal logic scan system according to the present invention, where 1 is test logic, 2 is a scan control circuit, 3 is a microprocessor, and 4 is a memory.

The gate array internal logic scan system according to the present invention includes a test logic 1, a scan control circuit 2, a microprocessor 3, and a memory 4, as shown in FIG.

The scan control circuit 2 is connected to the microprocessor 3 and the test logic 1 to control a loopback operation for the scan of the test logic 1 under the control of the microprocessor 3, and the micro The processor 3 is connected to the scan control circuit 2 to control the scan control circuit 2 for scanning the custom chip and gate array to be tested.

2 is a configuration diagram of the scan control circuit 2 of FIG. 1, 10 is an address register, 11 is a multiplexer, 12 is a data register, 13 is a counter, and 14 is a logic control circuit.

The scan control circuit 2 connects the address register 10 to the microprocessor 3 and the test logic 1 as shown in FIG. 2, and the output of the test logic 1 is connected to the scan logic. It is connected via a multiplexer. The data register 11 is connected to the multiplexer 11, the counter 13 is connected to the microprocessor 3, and the multiplexer 11, the microprocessor 3, and the counter are connected. The logic control circuit 14 is connected to the data register 12 and the address register 10.

The multiplexer 11 selects a test output signal Tout from the test logic 1 under the control of the logic control circuit 14 and outputs the test output signal Tout to the data register 12. At the start of the test, the data register 12 inputs test input data Tin to the test logic 1 under the control of the logic control circuit 14 and the microprocessor 3. The address register 10 receives an address signal from the microprocessor 3 and outputs the address signal to the test logic 1 under the control of the logic control signal 14.

The counter 13 consists of a down counter decremented by one per clock, and consists of the test logic 1 and the scan control circuit 2 until the counter 13 indicates " 0 ". Shifts in the loop are synchronized by the clock from the microprocessor 3. When the counter 13 reaches " 0 ", the logic control circuit 14 detects this, generates an interrupt and informs the microprocessor 3 of the end of the test.

3 is a configuration diagram of the test logic 1 of FIG. 1, 15 is an address decoder, 16 is a multiplexer, 17, 18 and 19 are D flip-flop register loops, and 20 is a sub address decode.

The test logic 1 receives an address from the scan control circuit 2 and selects one chip (D / A) of n custom chips from the address decoder, and applies the multiplexer l6 to the address decoder 15. And n register loops 17 to 19 connected to the scan control circuit 2 and the multiplexer 16, and a selected one of the n custom chips to the scan control circuit 2 and the multiplexer 16. The sub-address decoder 20 which selects one register loop from the n register loops 17 to 19 in the custom chip is connected to each other. The multiplexer 16 performs AND on the address decoder 15 and the subaddress decoder output to use the control signal.

When the test input signal Tin input from the scan control circuit 2 is inputted to the n register loops 7 to 19 and shifted, and then input to the multiplexer 16, the multiplexer 16 receives the sub. The test output signal Tout1 is output to the scan control circuit 2 under the control of the address decoder 20.

4 is a detailed configuration diagram of the D flip-flop register loops 17, 18, and 19 of FIG. 3, and 21, 22, and 23 represent registers, respectively.

The register loops 17, 18, and 19 are composed of a plurality of registers 21, 22, and 23 connected in series as shown in FIG. 4. In the normal mode, each register 21, 22, and 23 is used. Outputs normal output data Yout1 to Yout3 by inputting each data Di1 to Di3, and in test mode, the test input data Tin input from the scan control circuit 2 is clocked. It shifts through adjacent registers 21, 22, and 23 according to CLK, and outputs it to the scan control circuit 2.

In addition, the registers 21, 22, and 23 each include a clock CLK, an output enable signal OE, a normal mode decision signal NE, and a test mode decision signal TE input from the scan control circuit 2. It works according to).

Looking at the detailed operation of the present invention configured as described above are as follows.

First, in order to proceed with the test, the microprocessor 3 issues an address to the scan control circuit 2 shown in FIG. 2, writes an address in the address register after chip selection, and writes a test data pattern in the data register. It also writes (1oad) the value to the down counter.

When the above processing is completed, the scan control circuit 2 analyzes and decodes the data of the address to use the address decoder 15 as the first step, and selects one of n custom chips and the sub address decoder 20. Finally, one of the n register loops (see FIG. 4) is finally selected in the selected custom chip (gate array).

Then, the dada pattern of the data register 12 is shifted in series through the selected data path. At this time, the counter 13 operates as a down counter according to a clock, and an initial value is determined according to the number of D flip-flops of a register loop to be scanned.

The shifted data continues through the selected path of the selected custom chip, and the shift is continued until the counter value becomes zero (zero). The data is touted through the multiplexer 16 and through the multiplexer 11, the data register ( Is fed back to 12)

When the counter value reaches zero, the logic control circuit 14 interrupts the microprocessor 3 to indicate that the test is completed, and the register 3 reads the data register 12 to match the value and the initial data pattern. Check to see if the good / bad of the custom chip. Here, the outputs of the two decoders 15 and 20 are treated with AND to enable the multiplexer during the test so that the shift operation can be made via the selected path.

In addition, in the register root shown in FIG. 4, each register represents a D flip-flop, and each flip-flop outputs the input Di to the data output Yout by the clock CLK in the normal operation. In the operation mode, NE (normal enable) is used.

During the scan test, the operation mode is activated from the logic control circuit 14 to test enable (TE). At this time, the data input Di and the output Yout are disabled, and the input data Tin is clocked. It outputs to Tout and inputs to Tin of adjacent D flip-flop, and eventually forms a series loop between D flip-flops and makes a finite register group to serve as a data path when scanning.

The preprocess above is repeated for all register loops.

Therefore, the present invention configured and operated as described above adds a circuit for a test to the custom chip and the gate array, thereby improving the accuracy of the test.

Claims (2)

10. A gate array internal logic scan system comprising a microprocessor (3) for detecting abnormalities of internal logic of a custom chip and gate array; A plurality of register loops 17 to 19 installed inside the custom chip and gate array for loopback testing, a first multiplexer 16 for selecting and outputting output signals of the plurality of register loops 17 to 19, Decoding means (15,20) for receiving the input from the microprocessor to decode and provide as a selection control signal of the multiplexer 16, the test logic to be installed in a large number of the custom chip and the gate array to be tested ( 1), the logic control means 14 connected to the microprocessor 3, and the loop test signals Tout1 to Tout3 output from the plurality of test logics 1 under the control of the logic control means 14. Multiplexing means (11) for selecting one of the counts and the count value received from the microprocessor (3) down counting under the control of the logic control means (14) A counter means 13 for outputting a result to the logic control means 14, a test data pattern from the microprocessor 3, and an output of the multiplexing means 11, The logic control means (1) shifts serially according to a control signal and transfers the data register (12) to the register loops (17 to 19) in the test logic (1) and the address signal input from the microprocessor (3). And an address register (10) for outputting to the decoding means (15, 20) in the test logic (1) in accordance with the control signal of (14). 3. The logic scan system of a gate array according to claim 2, wherein the register loop (17 to 19) is formed by connecting a plurality of registers (21 to 23) in series.