JPH08115994A - Semiconductor device - Google Patents

Abstract

PURPOSE: To provide a noise-resistant package structure which realizes lower cost and easy arrangement of wiring by providing a wiring board and a high degree of freedom with respect to wiring layout by connecting a wire in the package with low inductance and high capacitance, and can be adapted to a high-speed semiconductor device. CONSTITUTION: A semiconductor device has a semiconductor chip 18 having an electrode, a substrate 17 on which the semiconductor chip 18 is mounted and which has a first wiring film 13a, lead terminals 12a, 12b electrically connected with the semiconductor chip 18, and a wire 14 for connecting the lead terminals 12a, 12b with the electrode, The semiconductor device also has a cap 16 for hermetically sealing the semiconductor chip 18 in cooperation with the substrate 17, and a wiring board 61 having wiring films 13b, 13c and provided between the substrate 17 and the cap 16. For instance, the first wiring film 13a on the surface of the substrate 17 is connected in predetermined portions with the second wiring films 13b, 13c on the lower and upper sides of the wiring board 16 by means of a conductive pin 20 and a through-hole 20a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device using a squad type package. There are various requirements for packaging semiconductor chips, and in addition to high reliability in strength, heat resistance, and moisture absorption resistance, connecting the semiconductor chip electrodes to lead terminals with low inductance and high capacitance, package cost Is also an important issue.

Reliability in terms of strength can be solved by making the package ceramic. Furthermore, the number of electrodes in semiconductor chips, which are becoming more highly integrated year by year, and the number of corresponding lead terminals tend to increase year by year, and the wiring layout is becoming more complicated. The packaging structure that does this also increases the need.

There is a multilayer ceramic package as a semiconductor device in which the package is made of ceramic, the degree of freedom of wiring is large, and the semiconductor chip can be connected with low inductance and high capacity. The multilayer ceramic package has an advantage that a wiring film can be sufficiently secured by providing a wiring film on each one of the ceramic substrates in a multi-layered manner. In addition to the complicated brazing process of the lead terminals, the use of gold for the surface treatment of the lead terminals has a drawback that the package cost is high.

[0004]

2. Description of the Related Art A squad type package has been developed to solve the problem that the cost of a multilayer ceramic package is high. However, although the problem of high package cost was solved with the sirquad type package, the degree of freedom in routing the wiring is reduced.

Therefore, a so-called two-layer quad-type package has been developed as a package structure which uses a ceramic package, is inexpensive, and has relatively free wiring. FIG. 7 shows a schematic structure of a two-layer quad-type package viewed from the side. In the figure,
Reference numeral 1 indicates a two-layer quad-type package. In the two-layer quad-type package 1, a semiconductor chip 8 is fixed on a ceramic substrate 7 with an adhesive 9, and lead terminals 2a and 2b are sandwiched by a glass material 5 (for example, low melting point glass). The semiconductor chip 8 is sealed by covering the cap 6 from above.

There are two types of lead terminals 2a and 2b in the figure. Of these, the lead terminal 2a is connected to the ground electrode or the power supply electrode formed on the semiconductor chip 8 through the wire 4, and has a wider width and a shorter length than the lead terminal 2b. ing. On the other hand, the lead terminal 2b
Is a signal line that is connected to the signal electrode 8a formed on the semiconductor chip 8 via the wire 4, and has a one-to-one correspondence with each electrode.

A method of connecting the leads 2a, 2b to the electrodes will be described with reference to FIG. 8, which is a view taken along the line BB 'shown by the broken line in FIG. The lead terminal 2b shown in FIG. 8 is arranged so that its tip approaches the electrode 8a up to the position of the glass material 5, and is directly connected to the electrode 8a by the wire 4. On the other hand, as described above, the lead terminal 2a is wider than the lead terminal 2b, and a plurality of wires (three wires in FIG. 8) are simultaneously connected to connect the wiring film 3 to the wiring film 3 in the vicinity of the outer peripheral portion of the substrate 7. Connected. Further, the wiring film 3 is connected again to the electrode 8a using the wire 4 at a position close to the semiconductor chip 8a.

The reason why wiring is relatively free in the two-layer quad-type package 1 is as follows. That is, the wire 4 connected to the lead terminal 2a is
The lead terminal 2a and the electrode 8a of the semiconductor chip 8 are connected via the wiring film 3 for wiring provided on the substrate 7. That is, the wiring film 3 is a metal film formed and patterned on the substrate 7, and the wire 4 does not directly connect the lead terminal 2a of the semiconductor chip 8 and the electrode 8a, if necessary.
After the wire 4 is once connected to the wiring film 3 for wiring, the wire 4 can be extended from the wiring film and connected to the lead terminal 2a, so that there are more choices in the wiring routing method.

The merit of the above construction is that the wire length can be shortened and the wiring area can be increased. Therefore, in the two-layer quad-type package, the wiring layout is simple, and the ground electrode and the electrode 8a for the power supply electrode are connected to the wiring film 3 via the wire 4, and a plurality of wiring films 3 are formed from the wiring film 3. Since it is connected to the lead terminal 2a via the wire 4, the ground line and the power supply line are superior in inductance and capacitance as compared with the signal line in which the signal electrode 8a and the lead terminal 2b are directly connected by the wire 4. This is advantageous in that the ground and the power supply can be stabilized.

[0010]

However, the two-layer sir quad type package solves the problem of lowering the manufacturing cost, but on the other hand, in the future, the semiconductor chip mounted in the semiconductor device will be further improved. It seems that it is impossible to deal with the increase in the number of terminals due to higher density and higher speed, and higher density of wiring.

In other words, with the increase in the number of lead terminals and the increase in wiring density, the conventional two-layer quad type becomes complicated in the wiring of the wire, and therefore is applicable to a semiconductor device operating at high speed. It gets harder. In addition, since the area where the wiring film is provided is limited to the surface of the substrate, each pattern is subdivided to increase the resistance, and the wiring film is provided by dividing the wiring board into planes. However, there is also a problem in that the semiconductor device has a higher probability of malfunctioning due to noise due to a decrease of about 1/4 to 1/40 as compared with the multilayer substrate.

In view of the above points, the present invention is low cost,
In addition, the wiring can be easily routed, and since the wires in the package are connected with low inductance and high capacitance, there is a large degree of freedom in wiring layout, which makes it suitable for packaging high-speed semiconductor elements The purpose is to provide a strong package structure.

[0013]

In order to solve the above problems, the present invention has the following configuration. A semiconductor device according to a first aspect of the present invention includes a semiconductor chip having electrodes, a substrate on which the semiconductor chip is fixed and a first wiring film is provided, lead terminals electrically connected to the semiconductor chip, and lead terminals. A wiring substrate having a wiring film is provided between the substrate and a wire for connecting the electrode and a cap that cooperates with the substrate to hermetically seal the semiconductor chip. It is a thing.

According to another aspect of the semiconductor device of the present invention, a semiconductor chip having electrodes, a substrate on which the semiconductor chip is fixed and a first wiring film is provided, and lead terminals electrically connected to the semiconductor chip. A wire for connecting the lead terminal and the electrode and a cap that cooperates with the substrate to hermetically seal the semiconductor chip, form a second wiring film on the inner surface of the cap, and use it as a wiring substrate It is characterized by.

A semiconductor device according to a third aspect of the present invention comprises a substrate,
It is characterized in that a connecting portion for electrically connecting the wiring board is provided. A semiconductor device according to a fourth aspect of the present invention is characterized in that the wire is brought into contact with a wiring board to form a connecting portion for connecting the lead terminal and the semiconductor chip to the wiring board.

A semiconductor device according to a fifth aspect of the present invention is characterized in that the connecting portion is a conductive pin that connects the substrate and the wiring substrate. A sixth aspect of the semiconductor device according to the present invention is characterized in that the conductive pin is inserted into a connection hole formed in the wiring board.

A semiconductor device according to a seventh aspect of the present invention is characterized in that the conductive pins are projected onto the upper surface of the wiring board, and the protruding portions of the conductive pins are deformed to connect to the board. is there. The semiconductor device according to the invention of claim 8 is characterized in that a positioning recess for aligning the conductive pin is provided on the first substrate.

[0018]

According to the first aspect of the invention, by forming the wiring film on the upper surface of the substrate, the area where the wiring film is provided is expanded. Further, by providing the wiring board, the area where the wiring film is formed is expanded. By widening the region where the wiring film is formed, the area of each wiring film is increased, the connection resistance is reduced, and the inductance of the wiring is reduced.

Further, by connecting the wire to the wiring film close to the lead terminal and connecting it to the electrode through the wiring film, the wiring of the wire is simplified and the degree of freedom of the wiring layout is increased, Wiring design is simplified.
According to the invention of claim 2, by forming a wiring film on the inner surface of the cap and using it as a wiring board, there is no need to newly provide a wiring board, and therefore, there is no need to change the design of the package. Is simple. Further, since the number of electronic parts of the semiconductor device is reduced, the assembling work becomes easy.

According to the invention of claim 3, an electrical connection can be obtained at an arbitrary position between the substrate and the wiring substrate by the connecting portion. According to the invention of claim 4, by using the wire already existing in the semiconductor device as the connecting member, it is not necessary to secure a space for newly providing another connecting portion in the substrate or the wiring substrate. Therefore, a space for the wiring film on the wiring board can be provided.

In the semiconductor device of the fifth aspect of the present invention, when the connecting portion is a conductive pin, the shape is simple, so that a desired material having excellent conductivity can be selected and the area required for installation is small. It is provided at an arbitrary position between the board and the wiring board. According to the invention of claim 6, forming the connection hole and inserting the conductive pin increases the contact area between the conductive pin and the wiring board, thereby reducing the resistance of the connection between the conductive pin and the wiring board. And increase the strength of fixation.

In the semiconductor device according to the invention of claim 7, the contact area between the conductive pin and the wiring board is increased by deforming the protruding portion of the conductive pin, so that the connection between the conductive pin and the wiring board is reduced in resistance and fixed. Increase the strength of. According to the semiconductor device of the invention of claim 8, the positioning recess of the substrate improves the positioning accuracy of the conductive pin.

[0023]

EXAMPLE A structure of a semiconductor device according to a first example which is an example of the present invention will be described. FIG. 1 is a schematic configuration diagram showing a semiconductor device of this embodiment. The semiconductor device according to the present embodiment is the same component parts as the two-layer quad-type package, that is, the semiconductor chip 18 and the first wiring film 1.
A substrate 17 on which a semiconductor chip is fixed, and 3a is formed;
In order to provide lead terminals 12a and 12b electrically connected to the semiconductor chip, a main body portion including a cap 16 that cooperates with the substrate to hermetically seal the semiconductor chip, and second wiring films 13b and 13c The wiring board 61 and the conductive pin 20 as a connecting portion for connecting both.

First, regarding the structure of a two-layer quad-quad package serving as a main body, a wiring film first 13a is patterned and formed on a ceramic substrate 17. A semiconductor chip is fixed to the center of the substrate 17 with an adhesive 19, lead terminals 12a and 12b are sandwiched by a low melting point glass 15 as a glass material, and a cap 16 is covered to seal the semiconductor chip 18. Wiring board 61 arranged in a two-layer squard type serving as a main body
Is a ceramic frame-shaped substrate called a wind frame. The outer periphery is substantially the same as the substrate 17, and the center is the substrate 1.
The semiconductor chip 18 to be mounted on the board 7 is cut out to a size slightly larger than the semiconductor chip 18.

The structure of the wind frame will be described with reference to FIG. FIG. 2 is a view taken along the broken line AA ′ in FIG. The wiring board 61 is provided for the purpose of expanding the space for providing the wiring film in the two-layer quad-type package 1. Therefore, both surfaces thereof are coated with second wiring films 13b (not shown in FIG. 2) and 13c, and the wiring film is patterned so that wiring can be easily routed. In this embodiment, aluminum is used as the material for the wiring films 13a, 13b, 13c. Further, the conductive pin 20 is disposed on the lower surface of the wiring board 61 and is not shown in FIG. The position where the conductive pin 20 is provided is equal to the position where the through hole 20a (not shown in FIG. 2) is provided.

In the present embodiment, the wiring film 13c is provided on the upper surface of the wiring board 61 as shown in the drawing, and the second wiring film 13b on the lower surface of the wiring board 61 is connected to the lead terminals 12a as shown in the sectional view. The substrate 17 (not shown in FIG. 2) is also provided on the surface opposite to 12b and the surface on which the wiring film is provided is provided.
In addition to the three surfaces, the three surfaces are provided. In the configuration diagram of the present embodiment, the wiring substrate 61 is the lead terminal 12
The wiring board 6 is disposed between the caps 16a, 12b and the cap 16.
1, the lead terminal 12 and the cap 16 are insulated from each other by a low melting point glass 15 which is a glass material.
Further, the wiring board 61 is provided with a through hole 20a, and the conductive pin 20 is inserted therein.

The conductive pin 20 is a first pin on the surface of the substrate 17.
The wiring film 13a, the second wiring film 13b on the lower surface of the wiring board 61, and the wiring film 13c on the upper surface of the wiring board 61 are electrically connected to each other at locations where they need to be electrically connected. The inside of the through hole 20a is filled with a conductive paste (for example, Ag-glass or the like), and the conductive pin 20 is further filled.
And the first wiring film 13a on the board 17 and the wiring board 61.
A conductive paste is also applied to the connection portion of the second wiring film 13b on the lower surface to further ensure conduction. With the above configuration, since the area where the second wiring films 13b and 13c are provided is widened, the degree of freedom in designing the wiring is increased,
The wiring length can also be shortened. In addition, the wiring film 13a,
By ensuring that the individual patterns 13b and 13c are sufficiently large, the connection of the wire 14 can be made low in inductance. In addition, the second wiring films 13 b, 13 are formed on the wiring board 61.
The capacity was increased by arranging c in layers.
As a result, high-speed semiconductor devices can be supported, and a package resistant to noise can be realized.

In addition, in the present embodiment, the conventional multilayer ceramic substrate had to be made of gold, which is expensive in the process, as the metal for wiring, but it is cheaper and more compatible with the ceramic. Since high-quality aluminum can be used, it is possible to provide a highly reliable and low-cost package. Next, the second embodiment will be described.

In this embodiment, the cap of the package is used for the wiring board in the package of the first embodiment. FIG. 3 is a schematic configuration diagram of the second embodiment.
In the figure, a semiconductor chip 28 is adhered and fixed on a substrate 27 having the same structure as that of the first embodiment with an adhesive 29, and lead terminals 22a and 22b are sandwiched by a low melting point glass 25 as in the first embodiment, and a wire is used. Electrode 28 of semiconductor chip 28 at 24
a and the lead terminal 22a are connected.

Here, the cap 26 is covered to seal the semiconductor chip 28. In this embodiment, the cap 2 is used.
The wiring film 23b for wiring is provided on the lower surface of 6 and is used for the same purpose as the wiring board 61 in the first embodiment. Also in this embodiment, the first wiring film 23a of the substrate
And the second wiring film 23b provided on the lower surface of the cap 26
As described in the first embodiment, the conductive pin 30 is provided at a position where electrical conduction with the above should be established.

Although the wiring film is provided on the lower surface of the cap 26 in this embodiment, the cap 26 may be used as a metal cap and used as a pattern that can be commonly used by many electrodes (eg, ground). Is. In this case, the entire surface of the cap 26 serves as a wiring film, which is advantageous in sufficiently reducing the inductance. Next, a third embodiment will be described with reference to FIG.

In this embodiment, as the connecting portion of the semiconductor device 11 of the first embodiment, the wire 14 is used in place of the conductive pin 20, and is provided on the first wiring film 13a on the substrate and the lower surface of the wiring substrate. The configuration is characterized in that the second wiring film 13b is connected. Therefore, the same components as those of the package 11 of the first embodiment are designated by the same reference numerals. First, the wire 14 is processed into a loop shape. First on board 17
Wiring film 13a and the second wiring film provided on the lower surface of the wiring board 61.
The wire 18 having the loop shape is brought into contact with the wiring film 13b at a position where conduction is desired to connect the electrode 18a of the semiconductor chip 18 and the lead terminal 12,
In addition, it is connected to the second wiring film 13b of the wiring board with low resistance.

The wire 14 connected to the electrode 18a is brought into contact with the second wiring film 13b of the wiring board 61 after being connected to the lead terminal 12, and the contact portion between the second wiring film 13b and the wire 14 is also conductive. The paste 14b is applied to increase the fixing strength of the second wiring film 13b and the wire 14 and expand the contact area to reduce the resistance.

Since the wire 14 is further connected to the first wiring film 13a of the substrate via the lead terminal 12, the electrode 18a, the second wiring film 13b, the lead terminal 12 and the first wiring film 13a are mutually connected. It is electrically connected. In this embodiment, since it is not necessary to install the connecting portion, it is possible to have a unique effect that the alignment between the connecting portion and the substrate becomes unnecessary.

Although the invention using the wire as the connecting portion is used for the semiconductor device of the first embodiment in the configuration diagram of this embodiment, it can be used for the semiconductor device of the second embodiment. Is. Next, a fourth embodiment will be described. FIG. 5 is a schematic configuration diagram of a conductive pin 40 that is a feature of the fourth embodiment.

Since the package structure of the semiconductor device according to the present invention has a structure in which the conductive pins of the package of the first embodiment are replaced with the conductive pins 40, the same structure as that of the first embodiment is the same. The reference numerals are attached to omit the overall view. When the conductive pin 40 is inserted into the through hole 40a, which serves as a connection hole provided in the wiring board, there is a portion protruding on the upper surface of the wiring board 61. By crushing this portion and transforming it into a size equal to or larger than the diameter of the through hole 40a, the fixing strength of the conductive pin 40 to the wiring board 61 becomes stronger.

Similar to the first embodiment, in this embodiment as well, the conductive paste 40b is applied to the inside of the through hole 40a and the connecting portion between the substrate, the wiring board 61 and the conductive pin 40 to reduce the connection resistance. Configured as Next, claim 7
A fifth embodiment corresponding to will be described. FIG. 6 is a schematic configuration diagram of a conductive pin 50 that is a feature of the fifth embodiment. In the present embodiment as well, the semiconductor device 11 of the first embodiment is characterized by the connecting method for connecting the conductive pin 50 to the first wiring film 13a of the substrate. Similar to the embodiment, the overall view is omitted.

A positioning recess 50a is provided on the first wiring film 13a of the substrate, and a conductive paste 50b is applied to provide the conductive pin 50. With this configuration, it is possible to improve the alignment accuracy of the connection position of the conductive pin 50. Further, since the conductive paste 50b is gel and easily collects in the recess 50a, the conductive paste 50b is sufficiently applied to the connection position of the conductive pin 50 and contributes to reduce the resistance between the conductive pin 50 and the substrate.

In the configuration diagram of this embodiment, the concave portion is provided only on the surface of the substrate, but it may be provided on the lower surface of the wiring substrate to improve the alignment accuracy of the conductive pin with respect to the wiring substrate. Have.

[0040]

As described above, according to the invention of claim 1, by using the upper surface of the substrate as a wiring substrate,
The area of each wiring film can be increased. Further, the wiring length can be shortened by providing the wiring board separately. Further, once the wire length is connected to a metal having a large area, the inductance generated in the wire can be reduced, and the signal current switched at high frequency can be mounted on the semiconductor chip.

Further, since the wiring film is provided on the wiring substrate so as to form a layer, the capacity of the semiconductor device is increased. Therefore, the structure of the semiconductor device against noise from the outside can be strengthened. This makes it possible to reduce the inductance of the wiring and package a semiconductor chip using a signal current switching at high frequency.

According to the second aspect of the invention, the wiring board can be provided with a structure similar to that of the conventional technique for manufacturing a package. Therefore, the process of manufacturing the package can be easily changed. According to the invention of claim 3, it becomes possible to electrically connect only the desired position between the substrate and the wiring substrate.

According to the fourth aspect of the present invention, it is possible to omit the process such as the positioning for accommodating the conductive pins and to simplify the manufacturing process of the package. According to the invention of claim 5, since the shape of the connecting portion is simple, the choice of constituent members is large. Further, since the area required for the arrangement is small, it is possible to increase the area for providing the wiring film on the wiring board.

According to the sixth aspect of the present invention, the strength and reliability of the package can be increased by increasing the fixing strength of the conductive pin to the wiring board. According to the invention of claim 7, the strength and reliability of the package can be improved by increasing the fixing strength of the conductive pin to the wiring board.

According to the invention of claim 8, the reliability of the package can be improved by improving the positioning accuracy of the conductive pins and reducing the connection resistance to the substrate.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a cross section of a semiconductor device structure of a first embodiment of the present invention.

FIG. 2 is a view of the semiconductor device of FIG. 1 taken along the broken line AA ′.

FIG. 3 is a schematic configuration diagram showing a cross section of a semiconductor device structure according to a second embodiment of the present invention.

FIG. 4 is a schematic configuration diagram showing a cross section of a semiconductor device of a third embodiment of the present invention.

FIG. 5 is a schematic configuration diagram of a conductive pin which is a main part of a fourth embodiment of the present invention.

FIG. 6 is a schematic configuration diagram of an alignment recess, which is a main part of a fifth embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a conventional two-layer quad-type package structure.

8 is a view of the semiconductor device of FIG. 7 taken along the broken line BB ′.

[Explanation of symbols]

 1, 11 and 21 Semiconductor device 2a, 12a, 22a Lead terminal 2b, 12b, 22b Lead terminal 3, 13a, 23a First wiring film 13b, 13c, 23b Second wiring film 4, 14, 24 Wire 5 , 15, 25 Glass material 6, 16, 26 Cap 7, 17, 27 Substrate 8, 18, 28 Semiconductor chip 8a, 18a, 28a Semiconductor chip electrode 61 Wiring substrate 20, 30, 40, 50 Conductive pin 20a, 40a Connection hole 50a Positioning recess

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Michio Hayakawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (8)

[Claims] 1. A semiconductor chip having an electrode, a substrate on which the semiconductor chip is fixed and a first wiring film is provided, lead terminals electrically connected to the semiconductor chip, the lead terminals, and A wiring board connecting an electrode and a cap that cooperates with the substrate to hermetically seal the semiconductor chip, and a wiring board having a wiring film is arranged between the substrate and the cap. Semiconductor device. 2. A semiconductor chip having an electrode, a substrate on which the semiconductor chip is fixed and a first wiring film is provided, lead terminals electrically connected to the semiconductor chip, the lead terminals, and A wire for connecting to an electrode, and a cap that cooperates with the substrate to hermetically seal the semiconductor chip, and a second wiring film is formed on the inner surface of the cap to be used as a wiring substrate. Semiconductor device. 3. The semiconductor device according to claim 1, further comprising a connecting portion for electrically connecting the substrate and the wiring substrate. 4. The semiconductor device according to claim 3, wherein the wire is brought into contact with the wiring board to form the connecting portion for connecting the lead terminal and the semiconductor chip to the wiring board. 5. The semiconductor device according to claim 3, wherein the connecting portion is a conductive pin that connects the substrate and the wiring substrate. 6. The semiconductor device according to claim 5, wherein the conductive pin is inserted into a connection hole formed in the wiring board. 7. The semiconductor device according to claim 5, wherein the conductive pin is connected to the substrate by projecting the conductive pin on the upper surface of the wiring substrate and deforming the projecting portion of the conductive pin. . 8. The alignment recess of a conductive pin is provided on the first substrate, as claimed in claim 5.
The semiconductor device according to any one of 1.