JPH0472750A - Glass sealed type semiconductor device - Google Patents
Glass sealed type semiconductor deviceInfo
- Publication number
- JPH0472750A JPH0472750A JP18597990A JP18597990A JPH0472750A JP H0472750 A JPH0472750 A JP H0472750A JP 18597990 A JP18597990 A JP 18597990A JP 18597990 A JP18597990 A JP 18597990A JP H0472750 A JPH0472750 A JP H0472750A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- lead frame
- semiconductor element
- lead
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000011521 glass Substances 0.000 title abstract description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 239000000919 ceramic Substances 0.000 abstract description 16
- 238000002844 melting Methods 0.000 abstract description 12
- 230000008018 melting Effects 0.000 abstract description 11
- 238000000034 method Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 238000007665 sagging Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229920006015 heat resistant resin Polymers 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はガラス封止型半導体装置に関し、特に多ビン用
のガラス封止型半導体装置の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a glass-sealed semiconductor device, and particularly to the structure of a glass-sealed semiconductor device for multiple bottles.
［従来の技術］
従来の多ビン用のガラス封止型半導体装置には第４図に
示すように、セラミック基板１にリードフレーム２を低
融点ガラス３で固着し、セラミックキャップ４で半導体
素子７を気密封止した構造のサークアッド型半導体装置
がある。このものにおいて、半導体素子７はリードフレ
ーム２にボンディングワイヤー８により電気的に接続さ
れており、リードフレーム２の材質として、４２合金又
は４５合金のものを用いている。リードフレーム２は単
層で、１００ビン以上の多ビンの場合、エツチングによ
ってパターンを形成している。現在、１００ビン以上の
パッケージにおいて、リードフレーム厚０．１５〜０．
２Ｍでリード幅０．１鵬、リードピッチ０゜２ｍ程度で
あるが、これは、エツチングによるパターン形成の限界
である。[Prior Art] As shown in FIG. 4, in a conventional glass-sealed semiconductor device for multiple bottles, a lead frame 2 is fixed to a ceramic substrate 1 with a low-melting glass 3, and a semiconductor element 7 is secured with a ceramic cap 4. There is a circad type semiconductor device that has a hermetically sealed structure. In this device, a semiconductor element 7 is electrically connected to a lead frame 2 by a bonding wire 8, and the lead frame 2 is made of 42 alloy or 45 alloy. The lead frame 2 is a single layer, and in the case of 100 or more bins, a pattern is formed by etching. Currently, for packages with 100 bins or more, the lead frame thickness is 0.15 to 0.
For 2M, the lead width is about 0.1m and the lead pitch is about 0.2m, but these are the limits of pattern formation by etching.
したがって、今後、多ビン化が進展すると、キャビティ
サイズはビン数に比例して大きくなり、パッケージ全体
の大きさが増大し、実装密度が低下する。そのため、電
子機器の小型化、軽量化、さらには機能向上が疎外され
る。また、外部リード先端部は一列に配置されており、
リード幅０．２閣、リードピッチ０．５ｍｍ程度のもの
が存在するが、変形に対するリード強度による制約から
、これ以上縮小できない。したがって、ピン数理に比例
して外部リードの総ピツチが増大し、パッケージサイズ
増を招いている。Therefore, as the number of bins increases in the future, the cavity size will increase in proportion to the number of bins, the overall size of the package will increase, and the packaging density will decrease. As a result, miniaturization, weight reduction, and even functional improvement of electronic devices are neglected. In addition, the tips of the external leads are arranged in a row,
There are some with a lead width of about 0.2mm and a lead pitch of about 0.5mm, but they cannot be made any smaller due to restrictions on lead strength against deformation. Therefore, the total pitch of external leads increases in proportion to the pin mathematics, leading to an increase in package size.
従来のガラス封止型半導体装置は、リードフレームが単
層であった。したがって、キャビティを拡大せずに多ビ
ン化を行うためには、内部リードの細線化が必要であっ
た。しかし、エツチングの限界から、リード幅を０．１
ｍｍ以下に細くすることは困難であるため、１００ビン
以上の多ピンの場合、ビン数に比例してキャビティを拡
大しなければならず、パッケージサイズが大きくなる。A conventional glass-sealed semiconductor device has a single-layer lead frame. Therefore, in order to increase the number of bins without enlarging the cavity, it was necessary to make the internal leads thinner. However, due to the limitations of etching, the lead width was reduced to 0.1
Since it is difficult to make the pins thinner than mm, in the case of a large number of pins of 100 or more bins, the cavity must be enlarged in proportion to the number of bins, which increases the package size.
その結果、実装密度が低下してしまうという問題点があ
る。As a result, there is a problem that the packaging density decreases.
また、半導体素子はビン数の増大に比例して大きくなら
ないため、キャビティサイズ拡大に伴い、ワイヤー長が
長くなる。そのため、ワイヤーボンディング時にワイヤ
ータレ、カールなどが発生し、信頼性の低下を招くとい
う問題点がある。Furthermore, since the semiconductor element does not increase in size in proportion to the increase in the number of bins, the wire length increases as the cavity size increases. Therefore, there is a problem in that wire sagging, curling, etc. occur during wire bonding, leading to a decrease in reliability.
一方、外部リードもリード強度の制約から、リード幅を
縮小できないため、−列に配置した場合、総ピツチが大
きくなり、パッケージの大型化を招いている。On the other hand, the lead width of the external leads cannot be reduced due to restrictions on lead strength, so if they are arranged in the negative column, the total pitch becomes large, leading to an increase in the size of the package.
本発明の目的はキャビティサイズを縮小化することによ
り、従来の問題点を解消したガラス封止型半導体装置を
提供することにある。An object of the present invention is to provide a glass-sealed semiconductor device that eliminates the conventional problems by reducing the cavity size.
［課題を解決するための手段］
前記目的を達成するため、本発明に係るガラス封止型半
導体装置においては、基板と、多層配線板と、キャップ
とを有するガラス封止型半導体装置であって、
基板は、半導体素子を搭載するものであり、多層配線板
は、複数のリードフレームを相互間を絶縁して多層に積
層したもので、基板上に搭載されるものであり、前記半
導体素子と各リードフレームとの間はボンディングワイ
ヤーで電気的に接続されるものであり、
キャップは、半導体素子及び該半導体素子とリードフレ
ームとの接続部を気密封止するものである。[Means for Solving the Problems] In order to achieve the above object, a glass-sealed semiconductor device according to the present invention includes a substrate, a multilayer wiring board, and a cap. The board is a board on which a semiconductor element is mounted, and the multilayer wiring board is a board in which a plurality of lead frames are laminated in multiple layers with insulation between them, and is mounted on the board, and the semiconductor element and the multilayer wiring board are mounted on the board. Each lead frame is electrically connected with a bonding wire, and the cap hermetically seals the semiconductor element and the connection portion between the semiconductor element and the lead frame.
半導体素子に電気的に接続されるリードフレームはセラ
ミック基板上に、相互間を絶縁した多層構造に積層させ
である。これにより、単層型のリードフレームに比較し
て内部リードピッチを縮小化することができる。A lead frame electrically connected to a semiconductor element is laminated on a ceramic substrate in a multilayer structure with mutual insulation. As a result, the internal lead pitch can be reduced compared to a single-layer lead frame.
次に本発明について図面を参照して説明す・る。 Next, the present invention will be explained with reference to the drawings.
（実施例１） 第１図は本発明の実施例１を示す縦断面図である。(Example 1) FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention.
図において、セラミック板５の上下両面に高融点ガラス
６を塗布し、第１のリードフレーム２ａと第２のリード
フレーム２ｂとを固着し、多層配線板Ｂを形成する。ま
た、第１のリードフレーム２ａと第２のリードフレーム
２ｂとは千鳥足状に相互の位置をずらせて設けてあり、
各々下向きに直角に折曲げである。In the figure, high melting point glass 6 is applied to both the upper and lower surfaces of a ceramic board 5, and a first lead frame 2a and a second lead frame 2b are fixed to form a multilayer wiring board B. Further, the first lead frame 2a and the second lead frame 2b are provided with their positions shifted from each other in a staggered manner,
Each is bent downward at a right angle.
この多層配線板Ｂは低融点ガラス３によってセラミック
基板ｌの周縁に固着されており、基板１の中央部に半導
体素子７が搭載され、半導体素子７とリードフレーム２
ａ、 ２ｂとの間はボンディングワイヤー８で電気的に
接続されている。セラミックキャップ４は低融点ガラス
３によって多層配線板Ｂの上面に接着され、半導体素子
７及び素子７とリードフレーム２ａ、 ２ｂとの接続部
を気密封止している。This multilayer wiring board B is fixed to the periphery of a ceramic substrate l by a low melting point glass 3, and a semiconductor element 7 is mounted in the center of the substrate 1, and the semiconductor element 7 and a lead frame 2
A and 2b are electrically connected by a bonding wire 8. Ceramic cap 4 is adhered to the upper surface of multilayer wiring board B with low melting point glass 3, and hermetically seals semiconductor element 7 and the connection portion between element 7 and lead frames 2a, 2b.
本実施例では、第２図に示すように内部リードピッチを
従来例（第５図）より縮小できるため、同一ビン数での
キャビティサイズが小さくなり、パッケージサイズを縮
小できる。また、キャビティサイズが小さいため、ワイ
ヤー長が短く、ワイヤーのタレ、カール等の不具合が防
止できる。一方、外部リードピッチも従来例より縮小で
きるため、さらにパッケージサイズが小さくなり、実装
密度が向上する。In this embodiment, as shown in FIG. 2, the internal lead pitch can be reduced compared to the conventional example (FIG. 5), so the cavity size is smaller for the same number of bins, and the package size can be reduced. Furthermore, since the cavity size is small, the wire length is short, and problems such as sagging and curling of the wire can be prevented. On the other hand, since the external lead pitch can also be reduced compared to the conventional example, the package size is further reduced and the packaging density is improved.
（実施例２）
第３図は本発明の実施例２を示す縦断面図である。本実
施例は、耐熱性を持つ樹脂板９の上下両面に接着剤ｌＯ
を塗布し、第１のリードフレーム２ａと第２のリードフ
レーム２ｂとをそれぞれ上面と下面に接着して多層配線
板Ｂを形成する。その多層配線板Ｂをセラミック基板１
に低融点ガラス３で固着し、セラミックキャップ４を低
融点ガラス３で多層配線板Ｂに封着する。気密性を保つ
ため、多層配線板Ｂの形成時に、樹脂板９の外側にテー
プ状の低融点ガラスを配置し、多層配線板をセラミック
基板ｌに固着する際に溶かし、リードフレーム間を低融
点ガラスで埋める。第１のリードフレーム２ａと第２の
リードフレーム２ｂとは千鳥足状に成形する。(Example 2) FIG. 3 is a longitudinal sectional view showing Example 2 of the present invention. In this embodiment, adhesive lO is applied to both the upper and lower surfaces of the heat-resistant resin plate 9.
is applied, and the first lead frame 2a and the second lead frame 2b are adhered to the upper and lower surfaces, respectively, to form the multilayer wiring board B. The multilayer wiring board B is a ceramic substrate 1
and the ceramic cap 4 is sealed to the multilayer wiring board B using the low melting point glass 3. In order to maintain airtightness, a tape-shaped low melting point glass is placed on the outside of the resin plate 9 when forming the multilayer wiring board B, and is melted when the multilayer wiring board is fixed to the ceramic substrate l, so that the low melting point glass is placed between the lead frames. Fill it with glass. The first lead frame 2a and the second lead frame 2b are formed into a staggered shape.
本実施例によれば、内部リードピッチを縮小できるため
、実施例１と同様に、パッケージサイズ縮小化による実
装密度の向上、ボンディングの信頼性向上が期待できる
。さらに、外部リードピッチを縮小できるため、パッケ
ージサイズを縮小できる。また、本実施例では、絶縁板
として樹脂板を使用しており、セラミック板の板厚が０
．１ｍｍ限界であるのに対し、数十ミクロンメートル厚
で製作できるため、パッケージの厚さも薄型化できると
いう利点を有する。According to this embodiment, since the internal lead pitch can be reduced, similar to the first embodiment, it is expected that the packaging density will be improved by reducing the package size and the reliability of bonding will be improved. Furthermore, since the external lead pitch can be reduced, the package size can be reduced. Furthermore, in this example, a resin plate is used as the insulating plate, and the thickness of the ceramic plate is 0.
．． Although the thickness is limited to 1 mm, it can be manufactured to a thickness of several tens of micrometers, which has the advantage that the thickness of the package can also be made thinner.
［発明の効果］
以上説明したように本発明は複数のリードフレームを相
互間を絶縁して積層し多層配線化しているため、従来の
単層型のガラス封止型半導体装置に比較して、内部リー
ドピッチを縮小化できる。[Effects of the Invention] As explained above, the present invention has a plurality of lead frames stacked and insulated from each other to form multilayer wiring, so compared to a conventional single-layer glass-sealed semiconductor device, Internal lead pitch can be reduced.
その結果、キャビティサイズを縮小化できるため、パッ
ケージサイズが小さくなり、実装密度を向上できるとい
う効果がある。また、キャビティサイズを小さく抑えら
れるため、ワイヤー長が短縮され、ワイヤーのタレ、カ
ール等によるボンディング歩留り低下が防止できる効果
を有する。As a result, since the cavity size can be reduced, the package size can be reduced and the packaging density can be improved. Furthermore, since the cavity size can be kept small, the wire length can be shortened, which has the effect of preventing a decrease in bonding yield due to sagging, curling, etc. of the wire.
第１図は本発明の実施例１を示す縦断面図、第２図は実
施例１のワイヤーボンディング状態を示した部分平面図
、第３図は本発明の実施例２を示す縦断面図、第４図は
従来のガラス封止型半導体装置を示す縦断面図、第５図
は従来のガラス封止型半導体装置のワイヤーボンディン
グ状態を示す部分平面図である。
１・・・セラミック基板 ２・・・リードフレー
ム２ａ・・・第１のリードフレーム
２ｂ・・・第２のリードフレーム ３・・・低融点ガラ
ス４・・・セラミックキャップ ５・・・セラミック
板６・・・高融点ガラス ７・・・半導体素子
８・・・ボンディングワイヤー ９・・・樹脂板１０・
・・接着剤
第１図FIG. 1 is a longitudinal sectional view showing a first embodiment of the present invention, FIG. 2 is a partial plan view showing a wire bonding state of the first embodiment, and FIG. 3 is a longitudinal sectional view showing a second embodiment of the present invention. FIG. 4 is a longitudinal cross-sectional view showing a conventional glass-sealed semiconductor device, and FIG. 5 is a partial plan view showing a state of wire bonding of the conventional glass-sealed semiconductor device. DESCRIPTION OF SYMBOLS 1...Ceramic substrate 2...Lead frame 2a...1st lead frame 2b...2nd lead frame 3...Low melting point glass 4...Ceramic cap 5...Ceramic plate 6 ...High melting point glass 7...Semiconductor element 8...Bonding wire 9...Resin plate 10.
・Adhesive Figure 1
Claims (1)
ス封止型半導体装置であって、 基板は、半導体素子を搭載するものであり、多層配線板
は、複数のリードフレームを相互間を絶縁して多層に積
層したもので、基板上に搭載されるものであり、前記半
導体素子と各リードフレームとの間はボンディングワイ
ヤーで電気的に接続されるものであり、 キャップは、半導体素子及び該半導体素子とリードフレ
ームとの接続部を気密封止するものであることを特徴と
するガラス封止型半導体装置。(1) A glass-sealed semiconductor device having a substrate, a multilayer wiring board, and a cap, where the substrate mounts a semiconductor element, and the multilayer wiring board connects a plurality of lead frames between each other. The cap is insulated and laminated in multiple layers and is mounted on a substrate, and the semiconductor element and each lead frame are electrically connected with bonding wires. A glass-sealed semiconductor device characterized in that a connection portion between the semiconductor element and a lead frame is hermetically sealed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18597990A JPH0472750A (en) | 1990-07-13 | 1990-07-13 | Glass sealed type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18597990A JPH0472750A (en) | 1990-07-13 | 1990-07-13 | Glass sealed type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0472750A true JPH0472750A (en) | 1992-03-06 |
Family
ID=16180232
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18597990A Pending JPH0472750A (en) | 1990-07-13 | 1990-07-13 | Glass sealed type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0472750A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5451815A (en) * | 1993-06-25 | 1995-09-19 | Fujitsu Limited | Semiconductor device with surface mount package adapted for vertical mounting |
| US5497030A (en) * | 1993-06-24 | 1996-03-05 | Shinko Electric Industries Co., Ltd. | Lead frame and resin-molded-type semiconductor device |
| US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
| US5819403A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Method of manufacturing a semiconductor chip carrier |
| US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
| US6141869A (en) * | 1998-10-26 | 2000-11-07 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
-
1990
- 1990-07-13 JP JP18597990A patent/JPH0472750A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5497030A (en) * | 1993-06-24 | 1996-03-05 | Shinko Electric Industries Co., Ltd. | Lead frame and resin-molded-type semiconductor device |
| US5451815A (en) * | 1993-06-25 | 1995-09-19 | Fujitsu Limited | Semiconductor device with surface mount package adapted for vertical mounting |
| US5821457A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Semiconductor die carrier having a dielectric epoxy between adjacent leads |
| US5819403A (en) * | 1994-03-11 | 1998-10-13 | The Panda Project | Method of manufacturing a semiconductor chip carrier |
| US5824950A (en) * | 1994-03-11 | 1998-10-20 | The Panda Project | Low profile semiconductor die carrier |
| US6339191B1 (en) * | 1994-03-11 | 2002-01-15 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
| US6828511B2 (en) | 1994-03-11 | 2004-12-07 | Silicon Bandwidth Inc. | Prefabricated semiconductor chip carrier |
| US6977432B2 (en) | 1994-03-11 | 2005-12-20 | Quantum Leap Packaging, Inc. | Prefabricated semiconductor chip carrier |
| US6141869A (en) * | 1998-10-26 | 2000-11-07 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
| US6857173B1 (en) | 1998-10-26 | 2005-02-22 | Silicon Bandwidth, Inc. | Apparatus for and method of manufacturing a semiconductor die carrier |
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