JPH02306657A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02306657A
JPH02306657A JP1129123A JP12912389A JPH02306657A JP H02306657 A JPH02306657 A JP H02306657A JP 1129123 A JP1129123 A JP 1129123A JP 12912389 A JP12912389 A JP 12912389A JP H02306657 A JPH02306657 A JP H02306657A
Authority
JP
Japan
Prior art keywords
cases
ceramic
case
type
sealed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1129123A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Tsushima
津島 和好
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1129123A priority Critical patent/JPH02306657A/en
Publication of JPH02306657A publication Critical patent/JPH02306657A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1532Connection portion the connection portion being formed on the die mounting surface of the substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/162Disposition
    • H01L2924/1627Disposition stacked type assemblies, e.g. stacked multi-cavities

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To place two dies in a package and to reduce its mounting area by stacking two PGA type ceramic cases vertically and forming an integrated structure in which both the cases are adhered and sealed with low melting point glass. CONSTITUTION:A lower ceramic case 1 is formed in a face-up type, and an upper ceramic case 2 is formed in a face-down type. These cases are individually die mounted and bonded to be assembled. The assembled cases 1, 2 are aligned at bonding faces 5, and the cavities of both the cases are simultaneously sealed with low melting point glass. Thus, since the two dies can be placed in a package and two PGA type ceramic cases are stacked in an integral structure, its mounting area is reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置に関し、特に高密度実装用のセラ
ミックPGA型集積回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor devices, and particularly to ceramic PGA type integrated circuits for high-density packaging.

〔従来の技術〕[Conventional technology]

従来のセラミックPGA型の半導体装置は、一つのケー
スに単一のダイ(半導体チップ)を搭載するもので、第
5図〜第7図に示すようなタイプのものであった。
A conventional ceramic PGA type semiconductor device has a single die (semiconductor chip) mounted in one case, and is of the type shown in FIGS. 5 to 7.

封止方法に関しては、単一のケース・キャビティをセラ
ミック・キャップで低融点ガラスにより接着封止するフ
リットシール方式(第5図)と、金属キャップで電気溶
接により封止するシームウェルド方式く第6図、第7図
)がある。
Regarding the sealing methods, there are two methods: the frit seal method (Fig. 5), in which a single case cavity is sealed with a ceramic cap using low melting point glass, and the seam weld method, in which the single case cavity is sealed by electric welding with a metal cap. Figure 7).

また、シームウェルド方式では、ダイ表面が実装面に対
して上向きとなるフェース・アップ型のものく第6図)
とダイ表面が実装面に対して下向きとなるフェース・ダ
ウン型のもの(第7図)がある。
In addition, the seam weld method is a face-up type in which the die surface faces upward relative to the mounting surface (Figure 6).
There is also a face-down type (Figure 7) in which the die surface faces downward with respect to the mounting surface.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体装置は、単一ケースに1つのダイ
を搭載するものであるため、例えば、2つのダイを機能
させるためには2つのパッケージを要し、個々にパッケ
ージを実装すると、その分実装面積が広がってしまい、
高密度実装の面での欠点がある。
The conventional semiconductor device described above has one die mounted in a single case, so for example, two packages are required to make two dies function, and if the packages are mounted individually, The mounting area becomes larger,
There is a drawback in terms of high-density packaging.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、半導体チップを搭載した第1の
PGA型セラミックケースに、他の半導体チップを搭載
した第2のPGA型セラミックケースを積み重ね低融点
ガラスで封止したというものである。
In the semiconductor device of the present invention, a first PGA type ceramic case on which a semiconductor chip is mounted and a second PGA type ceramic case on which another semiconductor chip is mounted are stacked and sealed with low melting point glass.

〔実施例〕〔Example〕

次に本発明について、図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の一実施例の縦断面図である。第2図
は、プリント基板に半田付は実装した場合の例を示す側
面図、第3図は、本実施例に示すパッケージの構成要素
を示す図である。
FIG. 1 is a longitudinal sectional view of an embodiment of the present invention. FIG. 2 is a side view showing an example of soldering and mounting on a printed circuit board, and FIG. 3 is a diagram showing the constituent elements of the package shown in this embodiment.

第1図において、1は下部のセラミックケース(第2の
PGA型セラミックケース)、2は上部のセラミックケ
ース(第1のPGA型セラミックケース)であり、1の
ケースはアレイ上の外部ピン3を、また2のケースもア
レイ状の外部ビン4を有している。これらの外部ピンは
、各々のケースにろう付けされ、積層セラミック内の配
線パターンと電気的に接続されている。
In Fig. 1, 1 is the lower ceramic case (second PGA type ceramic case), 2 is the upper ceramic case (first PGA type ceramic case), and case 1 has external pins 3 on the array. , and the second case also has an array of external bins 4. These external pins are brazed to each case and electrically connected to the wiring pattern inside the laminated ceramic.

セラミックケース1,2は熱膨張係数の同じ同一材質に
よるものとし、封止部5(接合面)で低融点ガラスによ
る接着封止がなされる。
The ceramic cases 1 and 2 are made of the same material having the same coefficient of thermal expansion, and are adhesively sealed with low melting point glass at the sealing portion 5 (joint surface).

セラミックケース1には、ダイ(半導体チップ)6がマ
ウントされ、ボンディングワイヤ8でケース側のパター
ンと電気的接続がどれらている。同様に、セラミックケ
ース2には、他のダイアがマウントされ、ボンディング
ワイヤ9でケース側に接続されている。プリント基板上
に実装する場合、第2図に示すように外部ビン3及び4
をプリント基板のスルーホールに立て半田付は部11で
プリント基板(PWB基板)側と電気的接続をとる。
A die (semiconductor chip) 6 is mounted on the ceramic case 1, and electrically connected to a pattern on the case side using bonding wires 8. Similarly, another diamond is mounted on the ceramic case 2 and connected to the case side with a bonding wire 9. When mounting on a printed circuit board, external bins 3 and 4 are used as shown in Figure 2.
Place it in the through hole of the printed circuit board and make an electrical connection with the printed circuit board (PWB board) side at soldering section 11.

次に本発明のパッケージの実施例について、第3図を用
いて組立方法を説明する。大別して、下部のセラミック
ケース組立、上部のセラミックケース組立、及び、上・
下側部の接着・封止から成る。
Next, an assembly method for an embodiment of the package of the present invention will be explained using FIG. Broadly divided, there are lower ceramic case assembly, upper ceramic case assembly, and upper and lower ceramic case assembly.
Consists of gluing and sealing the lower part.

下部のセラミックケースは、フェース・アップタイプの
もので、また、上部のセラミックケースはフェース・ダ
ウンタイプのものである。これら両者は、従来技術によ
って、ダイ・マウント及びボンディングを個別に行って
組立てる。
The lower ceramic case is a face-up type, and the upper ceramic case is a face-down type. Both are assembled by die mounting and bonding separately using conventional techniques.

各々、組立られな上・下2つのセラミックケースにおい
て、5の接合面を位置合わせし、低融点ガラスによる封
止により、両ケースのキャビティを同時に封止してしま
う。
In each of the two unassembled upper and lower ceramic cases, the joint surfaces 5 are aligned, and the cavities of both cases are simultaneously sealed by sealing with low melting point glass.

以上、説明したように本実施例ではパッケージ内に2つ
のダイを搭載でき、2つのPGA型セラミックケースを
縦方向に積み重ねた一体化構造であるため、個々のパッ
ケージを実装した場合に比べて、大幅に実装面積を低減
できるほか専用のキャップが不要となる。
As explained above, in this example, two dies can be mounted in the package, and since it has an integrated structure in which two PGA type ceramic cases are vertically stacked, compared to the case where individual packages are mounted, In addition to significantly reducing the mounting area, there is no need for a dedicated cap.

第4図は、本発明の他の実施例を示す縦断面図である。FIG. 4 is a longitudinal sectional view showing another embodiment of the present invention.

第4図は、下部及び上部の両セラミックケースとも、フ
ェース・ダウン・タイプのものであり、かつ、封止方法
に関し下部のセラミックケース1は、シールリング部1
2で金属キャップ13を溶接で封止(シームウェルド方
式)し、上部のセラミックケース2は、下部のセラミッ
クケース1の背面にある封止部5でガラス接着封止され
る。
FIG. 4 shows that both the lower and upper ceramic cases are of the face-down type, and regarding the sealing method, the lower ceramic case 1 has a seal ring part 1.
2, the metal cap 13 is sealed by welding (seam welding method), and the upper ceramic case 2 is sealed with glass adhesive at the sealing part 5 on the back side of the lower ceramic case 1.

この構造では、両セラミックケースのキャビティが独立
になり、2つのダイに接続されているホンディングワイ
ヤ相互の接触が起りにくい利点がある。
This structure has the advantage that the cavities of both ceramic cases are independent, and the bonding wires connected to the two dies are less likely to come into contact with each other.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、2つのPGA型セラミ
ックケースを縦方向に積み重ね、両ケースを低融点ガラ
スで接着・封止した一体化構造とすることにより、パッ
ケージ内に2つのダイを搭載した半導体装置が得られ、
実装面積の低減が図れるという効果がある。
As explained above, the present invention has an integrated structure in which two PGA type ceramic cases are stacked vertically and both cases are bonded and sealed with low melting point glass, thereby mounting two dies in the package. A semiconductor device with
This has the effect of reducing the mounting area.

図面の簡単な説明 第1図は、本発明の一実施例の半導体集積回路パッケー
ジの構造全体を説明するための縦断面図、第2図は、一
実施例をPWB基板上に実装した例を示す側面図、第3
図は、構成要素の縦断面図、第4図は、本発明の他の実
施例を示す縦断面図、第5図、第6図及び第7図はそれ
ぞれ従来例を示す縦断面図で−ある。
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a vertical cross-sectional view for explaining the entire structure of a semiconductor integrated circuit package according to an embodiment of the present invention, and FIG. 2 is an example in which the embodiment is mounted on a PWB substrate. Side view shown, third
4 is a longitudinal sectional view showing another embodiment of the present invention, and FIGS. 5, 6, and 7 are longitudinal sectional views showing conventional examples, respectively. be.

1・・・第2のPGA型セラミックケース、2・・・第
1のPGA型セラミックケース、3,4・・・外部ピン
、5・・・封止部(接合面)、6.7・・・ダイ(半導
体チップ)、8.9・・・ボンディングワイヤ、10・
・・PWB基板、11・・・半田付は部、12・・・シ
ールリング封止部、13・・・金属キャップ。
DESCRIPTION OF SYMBOLS 1... Second PGA type ceramic case, 2... First PGA type ceramic case, 3, 4... External pin, 5... Sealing part (joint surface), 6.7...・Die (semiconductor chip), 8.9... Bonding wire, 10.
...PWB board, 11...Soldering part, 12...Seal ring sealing part, 13...Metal cap.

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを搭載した第1のPGA型セラミックケー
スに、他の半導体チップを搭載した第2のPGA型セラ
ミックケースを積み重ね低融点ガラスで封止したことを
特徴とする半導体装置。
A semiconductor device characterized in that a first PGA type ceramic case loaded with a semiconductor chip and a second PGA type ceramic case loaded with another semiconductor chip are stacked and sealed with low melting point glass.
JP1129123A 1989-05-22 1989-05-22 Semiconductor device Pending JPH02306657A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1129123A JPH02306657A (en) 1989-05-22 1989-05-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1129123A JPH02306657A (en) 1989-05-22 1989-05-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02306657A true JPH02306657A (en) 1990-12-20

Family

ID=15001651

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1129123A Pending JPH02306657A (en) 1989-05-22 1989-05-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02306657A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206378A (en) * 1992-01-30 1993-08-13 Nec Kyushu Ltd Semiconductor device
JP2004363126A (en) * 2003-05-30 2004-12-24 Seiko Epson Corp Semiconductor device, electronic device, electronic equipment, and method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05206378A (en) * 1992-01-30 1993-08-13 Nec Kyushu Ltd Semiconductor device
JP2004363126A (en) * 2003-05-30 2004-12-24 Seiko Epson Corp Semiconductor device, electronic device, electronic equipment, and method of manufacturing semiconductor device
US7436061B2 (en) 2003-05-30 2008-10-14 Seiko Epson Corporation Semiconductor device, electronic device, electronic apparatus, and method of manufacturing semiconductor device

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