JP2924853B2 - Semiconductor device package and semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device package and a semiconductor device, and more particularly to a ball grid array (BGA) package made of a metal substrate and a semiconductor device.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor devices, the number of pins of packages on which semiconductor devices are mounted has rapidly increased. As an integrated circuit package that supports multiple pins,
Balls in which solder balls that serve as external terminals are arranged in a grid
Grid array (BGA) packages are known.

FIG. 7 is a plan view showing the structure of a first prior art BGA package, FIG. 8A is a sectional view taken along the line DD ′ of FIG. 7, and FIG. FIG. As shown in FIGS. 7 and 8, a conventional package includes a flat metal base 21 made of a metal such as copper, a polyimide 22 formed on the metal base 21, and a polyimide 22 formed on the metal 22. And a wiring 23 formed.

The metal base 21 has a main body 21a formed in a substantially flat plate shape, and a die attach part 21b for mounting an LSI by recessing a part of the main body 21a. Terminals 2 arranged in a grid around the die attach portion 21b
1c is provided. As shown in FIG. 8 (B), the terminal 21c is separated from the metal base portion 2 by a peripheral gap 21d.
1 is electrically insulated from the main body 21a.

[0005] The polyimide 22 is disposed outside the die attach portion 21b of the metal base portion 21. A plurality of bonding stitches 23a are provided on the polyimide 22 near the die attach portion 21b.

The wiring 23 is formed by a bonding stitch 23a.
And a land (not shown) (directly above the terminals). As shown in FIG. 8A, the bonding stitch 23a not connected by the wiring 23 is electrically connected to the metal base 21 via a via hole 24 formed near the bonding stitch 23a. The land portion is electrically connected to the metal base portion 21 by a lead 26 via a via hole 25 formed near the land portion. FIG.
As shown in (B), a solder ball 27 for electrical connection to the outside is provided directly above the land.

In the first prior art BGA package, when the potential of the metal base 21 is fixed to GND,
The bonding stitch 23a and the land (solder ball 27) connected to the metal base 21 through the via holes 24 and 25 all have the GND potential.
Therefore, the solder ball 27 and the bonding stitch 23a serving as GND are determined in advance.

As packages other than the metal-based BGA package, for example, Japanese Patent Application Laid-Open No. 63-246851 and US Pat. No. 5,250,844 disclose packages using a lead frame.

FIG. 9 is an exploded perspective view showing a second prior art composite lead frame, FIG. 10 shows the structure of the composite lead frame of FIG. 9, (A) is a perspective view, and (B) is a sectional view. is there.

A second prior art composite lead frame is:
As shown in FIG. 9, a lead frame 30 and an assembly 40 connected to a lower portion of the lead frame 30 are provided. The lead frame 30 includes a plurality of leads 31 and an opening 32 formed on the tip 31 a side of the lead 31.
And an outer frame portion 33 formed on the periphery of the lead 31 and a tie bar 34 connecting the leads 31 to each other.

The assembly 40 includes a polyimide film 41 for insulation, an inner metal plate 42, a polyimide film 43 for insulation, and an outer metal plate 44. Inner metal plate 42
Are provided with tabs 42a on the sides thereof, and tabs 44a are provided on the outer metal plate 44. As shown in FIG. 10, tabs 42 a and 44 a provided on the inner metal plate 42 and the outer metal plate 44, respectively, are connected by a lead-tab connecting portion 50.
It is electrically connected to a predetermined lead 31.

In the second prior art composite lead frame, the inner metal plate 42 is set at the power supply potential and the outer metal plate 4 is set at the power supply potential.
4 is fixed to the GND potential, the respective tabs 42a,
Predetermined leads 31 to which 44a is connected have respective potentials.

FIGS. 11A and 11B are explanatory views showing a process of assembling a composite lead frame according to the second prior art, wherein FIG. 11A shows a state in which the composite lead frame is assembled, and FIG.
A state where I51 is mounted on the composite lead frame with the Ag paste 52 is shown, and (C) shows a state where wire bonding is performed.

As shown in FIG. 11C, the outer metal plate 4
The wire 53a bonded to the lead 4 has a GND potential, the wire 53b bonded to the inner metal plate 42 has a power supply potential, and the wire 53c bonded to the lead 31 has a signal.

FIG. 12 is an exploded perspective view showing a third prior art composite lead frame.

As shown in FIG. 12, in the third prior art composite lead frame, a first film 60 is connected to an upper portion of the lead frame 30, and a second film 70 is connected to a lower portion of the lead frame 30. You. FIG.
Reference numeral 36 denotes a hanging pin.

The first film 60 is made of a lead frame 3
The insulating plate 60a provided on the 0 side and the lead frame 30
And a conductor plate 60b provided on the side opposite to the side, and an opening 60c is formed in the center. Second film 7
0 is an insulating plate 70a provided on the lead frame 30 side.
And a conductor plate 70b provided on the side opposite to the lead frame 30 side. The insulating plate 70a is composed of two parts, a central island-like part and a ring-like part outside the central part.

FIG. 13 shows the structure of the composite lead frame of FIG. 12, wherein (A) is a perspective view and (B) is a sectional view.
As shown in FIG. 13B, an island-shaped die attach portion 80 and a moat-shaped opening 81 are provided at the center of the composite lead frame.
Is formed.

FIGS. 14A and 14B are explanatory views showing a process of assembling a composite lead frame according to a third prior art. FIG. 14A shows a state in which the composite lead frame is assembled, and FIG.
A state where I51 is mounted on the composite lead frame with the Ag paste 52 is shown, and (C) shows a state where wire bonding is performed. In this example of the prior art, the upper and lower conductor plates 60b and 70b are set to the GND potential.

FIGS. 15A, 15B and 15C show the ground potential (GND) in the third prior art composite lead frame.
It is an explanatory view showing how to take in detail. L for signal destination
The electrode pad 51a of the SI 51 is electrically connected to the lead 31 via the wire 90a (FIG. 15A and FIG.
5 (C)).

In the case of the GND potential, first, the conductor plate 7
0b and the lead 31 are connected by a wire 90b. Then
Connect the ground electrode pad 51b and the lead 31 to the wire 9
Connect at 0c. Finally, the lead 31 and the conductor plate 60b are connected by a wire 90d (FIG. 15A and FIG.
(B)). With this structure, any lead can be set to the GND potential.

Japanese Unexamined Patent Publication No. 61-13687 discloses a through hole provided in a portion of a metal plate other than a portion on which a semiconductor element is mounted, and a metal plate excluding the through hole and a portion on which the semiconductor element is mounted. An insulating layer formed on the surface and side surfaces of the electric circuit formed on the insulating layer on the surface, and a conductive layer formed on the insulating layer formed in the through hole and insulated from the metal plate and conducting with the electric circuit. There is disclosed a wiring board for mounting a semiconductor element, comprising: a conductive layer that is electrically connected to a metal plate and is insulated from an electric circuit; and connection pins that are inserted and fixed in contact with the respective conductive layers.

[0023]

In the first prior art,
Near the bonding stitch and land (solder ball)
In the vicinity, it is electrically connected to the metal base via a via hole. Therefore, different types of LSI
Unless the ND pin arrangement and the electrode pad arrangement are determined, a package must be prepared for each LSI type. As a result, package inventory management becomes complicated, which increases not only the man-hour and cost, but also in the case of a new LSI, the development of a new package and the accompanying
Numerous inconveniences arise, such as the need to anticipate manufacturing costs.

In the second prior art, as in the first prior art, any bonding stitch (lead),
There is a disadvantage that an arbitrary solder ball (external lead) cannot be set to the GND potential or the power supply potential, and is limited to a specific position in advance.

In the third prior art, since the lead and the upper and lower conductors are connected by a wire, the above disadvantages are solved. However, since the connecting wire is thin, the distance between the bonding stitch GND is small. The self-inductance becomes high, and it is difficult to obtain a uniform GND potential. Also,
To reduce self-inductance, a significant number of wires need to be bonded.

Further, since the connection is made only on the LSI chip side, it is more difficult to solve the problem. In order to prevent this, a structure in which the conductor plate is bonded to the lead with a wire on the external lead side is also considered. In some cases, the area occupied by the sealing resin must be extended to the outside, which is larger than the conventional package size.

Japanese Patent Application Laid-Open No. 61-13687 discloses that a through hole is provided in a portion of a metal plate other than a portion on which a semiconductor element is mounted, and a conductive layer is formed in the through hole. There is no disclosure or suggestion about assigning any pin to the power supply / GND later according to the structure or type of the metal-based BGA package.

As described above, the required number of power supply / GND pins and the number of signal pins are different depending on the type of LSI. There was a disadvantage that the package had to be redesigned (minor change). As a result, there arises a problem that design man-hours are increased, a delivery time is lengthened, costs are increased, and labor for managing more materials is generated.

The reason for this is that the assignment of signals, power supplies, and GND pins on the package is determined, and the LSI is designed accordingly.

The present invention has been made to solve the above-mentioned problem, and all the pins (wirings) are signal pins and power supplies.
An object of the present invention is to provide a semiconductor device package and a semiconductor device in which a GND pin is shared and an arbitrary pin can be assigned to a power supply / GND later depending on a product type.

[0031]

According to the present invention, there is provided a semiconductor device package comprising a metal base having a mounting portion for mounting a semiconductor element, and a plurality of metal bases formed on the metal base and electrically connected to the outside. An insulating section having an external connection section,
A wiring for electrically connecting the semiconductor element mounted on the mounting portion to each external connection portion, an opening window formed on a side portion of each wiring and opening from an insulating portion to a metal base portion, and an opening window thereof And a conductive portion that fills a predetermined opening window portion with a conductive material and electrically connects the wiring and the metal base portion.

According to the semiconductor device package of the present invention, for example, when the metal base portion is fixed at the GND potential, of the electrode pads of the semiconductor element such as an LSI mounted on the mounting portion of the metal base portion, the GND potential is reduced. A conductive portion such as a solder is filled in an opening window for a wiring corresponding to the conductive portion to provide a conductive portion.

When a semiconductor device is mounted on the mounting portion of the metal base portion and wire bonding is performed, the GN of the semiconductor device is reduced.
The electrode pad corresponding to the D potential is electrically connected to the metal base via a conductive portion provided at the opening window. Similarly, the external connection portion is also fixed at the GND potential.
In this case, the size of the LSI is increased by increasing the size of the opening window.
It is possible to minimize the self-inductance between -GND.

A semiconductor device package according to another aspect of the present invention has a conductive layer formed between a metal base portion and an insulating portion with an insulating layer interposed therebetween. A first opening window opening from the insulating layer to the conductive layer; and a second opening window opening from the insulating portion to the metal base portion and formed at a position where the conductive layer is not exposed to the side wall. A first conductive portion for electrically connecting the wiring and the conductive layer by filling the first opening window with a conductor, and a wiring and a metal base portion for filling the second opening window with a conductive material. And a second conductive portion that is electrically connected.

A plurality of opening windows may be formed corresponding to one wiring. The opening window may be formed along the longitudinal direction of the wiring.

The conductive portion is, for example, solder for burying the opening window, or may be made of a paste-like metal which solidifies after heating.

The semiconductor device according to the present invention includes a package for the semiconductor device, a semiconductor element mounted on the package for the semiconductor device, a wire for electrically connecting the semiconductor element and the package for the semiconductor device, And a resin for coating the resin.

[0038]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a partially cutaway perspective view showing a package according to a first embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA ′ of FIG.

As shown in FIGS. 1 and 2, the first embodiment of the present invention
The package according to the embodiment has a metal base portion 1, a polyimide 2 formed on the metal base portion 1, and a plurality of wirings 3 formed on the polyimide 2.

The metal base 1 is made of, for example, a metal such as copper or a material plated with gold using an alloy of copper and nickel.
It has a main body 1a formed in a substantially flat plate shape, and a die attach part 1b for mounting an LSI by depressing a part of the main body 1a. Terminals 1c arranged in a lattice are provided around the die attach portion 1b. This terminal 1c is
As shown in the figure, the peripheral gap 1d electrically insulates the main body 1a of the metal base.

The polyimide 2 is arranged outside the die attach portion 1b of the metal base portion 1. A plurality of bonding stitches 3a are provided on the polyimide 2 near the die attach portion 1b.

The wiring 3 is made of a metal such as copper or a material plated with gold using an alloy of copper and nickel. All wiring 3
The bonding stitch 3a and the land 3b immediately below the solder ball 6 are connected to each other on a one-to-one basis. An opening window 5 extending to the metal base 1 is opened in the polyimide 2 located on the side of the wiring 3. The open window 5 is formed for all the wirings 3, and moreover, 2
There are two locations (a location near the land 3b and a location near the bonding stitch 3a).

To protect the surface layer of the package, a solder resist 4 is coated. In the portion of the solder resist 4 located on the opening window 5, a hole is formed so as to straddle the opening window 5 and the portion of the adjacent wiring 3 (see FIG. 2A).

In the package according to the first embodiment,
It is assumed that the metal base 1 is fixed at the GND potential. In this case, in the wiring 3 to be dropped to GND, the opening windows 5 both at the portion near the land portion 3b and at the portion near the bonding stitch 3a are filled with, for example, Pb-Sn based solder 7 (see FIG. 2B). ). As a result, an arbitrary wiring 3 can be allocated to GND, and since it is connected to the metal base 1 near the bonding stitch 3a and near the solder ball (land 3b), the self-inductance generated by the GND connection is minimized. It becomes possible to suppress to.

FIG. 3 is an explanatory diagram for explaining a process of assembling a semiconductor device using the package according to the first embodiment of the present invention. First, the solder 7 is filled in each of the two opening windows 5 of the wiring 3 to be fixed to GND in advance. Thereafter, the LSI 9 is mounted, and further, the LSI 9 and the package are connected by the wire 10 (see FIG. 3A).

Next, in order to protect the LSI 9, LS
The peripheral portion on I9 is covered with resin 12 by potting or the like (see FIG. 3B).

FIG. 4 is a plan view showing a package according to the second embodiment, and FIG. 5 is a sectional view taken along the line BB 'of FIG.
Note that the solder resist 4 is omitted for simplification of the drawing.

The package according to the second embodiment is a modification of the package according to the first embodiment, and has one open window 13 formed per one of the wirings 3. Is characterized by being formed so as to extend along the longitudinal direction.

According to the package of the second embodiment,
The self-inductance up to GND is kept to a minimum as in the first embodiment, and the number of connections with the solder 7 is reduced by about 1
/ 2, so that the process can be simplified.

FIG. 6 is a sectional view showing a package according to the third embodiment. The package of the third embodiment is
It is characterized in that it is formed of five layers of a metal base portion 1, a polyimide 14, a conductive layer 15, a polyimide 2, and a wiring 3. Further, the opening window portion includes a first opening window portion 16 that opens from the polyimide 2 to the conductive layer 15 and a second opening portion that opens from the polyimide 2 to the metal base portion 1 and is formed at a position where the conductive layer 15 is not exposed on the side wall. It has a window 17. Then, the first open window 16 is filled with solder 18 (see FIG. 6A), and the second open window 17 is filled with solder 19 (see FIG. 6B).

The package of the present invention may have an internal structure of five or more layers, and may have three or more open windows for one wiring 3.

The present invention is not limited to the above embodiment, and various changes can be made within the technical scope described in the claims.

For example, in the first embodiment and the second embodiment, the three-layer structure of the metal base 1, the polyimide 2, and the wiring 3 will be described. In any case, the metal base 1 is connected to the GND potential. However, the power supply potential may be used. Further, by dividing the metal base portion 1 in a plane and dividing the metal base portion 1 into the power supply and the GND, it is possible to incorporate both the GND and the power supply in the package without changing the three-layer structure.

[0054]

According to the present invention, since the opening window is formed on the side of the wiring, the signal wiring is kept as it is, and the power supply (GND) fills the opening window with a conductor, so that all the windows are filled. Can easily be assigned later to a signal or a power source / GND. Therefore, it is possible to mount semiconductor elements having different numbers of signal pins and power supply / GND pins in the same package (however, the total number of pins is the same), and to share the package without deteriorating the performance of the package. Can be achieved.

Further, the sharing of the package reduces the need for redesigning the package, thereby eliminating the period for manufacturing a new package and reducing the number of types of package materials. Can be reduced, and the design period is not required.

[Brief description of the drawings]

FIG. 1 is a partially cutaway perspective view showing a package according to a first embodiment of the present invention.

FIG. 2 is a sectional view taken along line A-A 'of FIG.

FIG. 3 is an explanatory diagram for explaining a step of assembling the semiconductor device using the package according to the first embodiment of the present invention;

FIG. 4 is a plan view showing a package according to a second embodiment.

FIG. 5 is a sectional view taken along line B-B ′ of FIG. 4;

FIG. 6 is a cross-sectional view illustrating a package according to a third embodiment.

FIG. 7 is a plan view showing the structure of a first prior art BGA package.

8A is a sectional view taken along line DD of FIG. 7, and FIG.
It is CC sectional view taken on the line of FIG.

FIG. 9 is an exploded perspective view showing a second prior art composite lead frame.

FIG. 10 shows the structure of the composite lead frame of FIG. 9,
(A) is a perspective view, (B) is a sectional view.

FIG. 11 is an explanatory view showing an assembling process of a composite lead frame according to a second prior art.

FIG. 12 is an exploded perspective view showing a third prior art composite lead frame.

FIG. 13 shows the structure of the composite lead frame of FIG. 12,
(A) is a perspective view, (B) is a sectional view.

FIG. 14 is an explanatory view showing an assembling process of a composite lead frame according to a third prior art.

FIG. 15 is an explanatory diagram showing in detail how to take a ground potential (GND) in the composite lead frame of the third prior art.

[Explanation of symbols]

 1: Metal base part 1a: Main body 1b: Die attach part 1c: Terminal 2: Polyimide (insulating part) 3: Wiring 3a: Bonding stitch 3b: Land part 4: Solder resist 5: Opening window part 6: Solder ball 7: Solder 9: LSI 10: Wire 12: Resin

Claims (7)

(57) [Claims] A metal base portion having a mounting portion on which a semiconductor element is mounted; an insulating portion formed on the metal base portion and having a plurality of external connection portions electrically connected to the outside;
Wiring for electrically connecting the semiconductor element mounted on the mounting portion and each external connection portion, and an open window formed on the side of each wiring and open from the insulating portion to the metal base portion, A semiconductor device package, comprising: a conductive portion that fills a predetermined opening window portion of the opening windows with a conductor to electrically connect the wiring and the metal base portion. A conductive layer formed between said metal base portion and said insulating portion with an insulating layer interposed therebetween; and said open window portion having a first opening extending from said insulating portion to said conductive layer. A first opening window portion, a second opening window portion formed from the insulating portion to the metal base portion and formed at a position where the conductive layer is not exposed to a side wall, wherein the conductive portion has a predetermined first opening A first conductive portion for electrically connecting the wiring and the conductive layer by filling a window with a conductive material; and a wiring and a metal base portion for filling the predetermined second opening window with a conductive material. The semiconductor device package according to claim 1, further comprising: a second conductive portion that is electrically connected. 3. The semiconductor device package according to claim 1, wherein a plurality of opening windows are formed corresponding to one wiring. 4. The semiconductor device package according to claim 1, wherein said opening window is formed along a longitudinal direction of said wiring. 5. The semiconductor device according to claim 1, wherein the conductive portion is a solder for burying the opening window.
4. The semiconductor device package according to any one of the above items. 6. The semiconductor device package according to claim 1, wherein said conductive portion is made of a paste-like metal which solidifies after heating. 7. A semiconductor device package according to claim 1, wherein the semiconductor device mounted on the semiconductor device package, and the semiconductor device and the semiconductor device package are electrically connected to each other. A semiconductor device comprising: a wire connected to the semiconductor device; and a resin covering the semiconductor element.