JPH04216652A - Package structure of semiconductor device - Google Patents
Package structure of semiconductor deviceInfo
- Publication number
- JPH04216652A JPH04216652A JP2411197A JP41119790A JPH04216652A JP H04216652 A JPH04216652 A JP H04216652A JP 2411197 A JP2411197 A JP 2411197A JP 41119790 A JP41119790 A JP 41119790A JP H04216652 A JPH04216652 A JP H04216652A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- conductive layer
- conductive
- flange
- cap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000003566 sealing material Substances 0.000 claims abstract description 12
- 238000007789 sealing Methods 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 49
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011231 conductive filler Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 239000005394 sealing glass Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、半導体装置を導電性キ
ャップで覆うことにより気密シールするパッケージ構造
に関するものである。更に詳しく述べると、上面に半導
体素子を搭載した回路基板の下面側に導電層を設け、導
電スルーホールで導電性封着部と接続することにより、
気密性と電磁シールド性の両方をもたせた封着技術に関
するものである。この技術はハイブリッドＩＣ等のパッ
ケージに好適である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a package structure in which a semiconductor device is hermetically sealed by covering it with a conductive cap. More specifically, by providing a conductive layer on the bottom side of the circuit board with a semiconductor element mounted on the top surface and connecting it to the conductive sealing part with a conductive through hole,
This relates to sealing technology that provides both airtightness and electromagnetic shielding. This technology is suitable for packages such as hybrid ICs.
【０００２】0002
【従来の技術】回路基板上に各種半導体素子を搭載した
半導体装置（例えばハイブリッドＩＣ等）では、半導体
素子と外気との間を遮断するために気密封止を行ってい
る。他方、発振モジュールなどを同一回路基板上に搭載
する半導体装置では、気密封止の他に電磁シールドも併
せて要求される。2. Description of the Related Art Semiconductor devices (such as hybrid ICs) in which various semiconductor elements are mounted on a circuit board are hermetically sealed to isolate the semiconductor elements from the outside air. On the other hand, in a semiconductor device in which an oscillation module and the like are mounted on the same circuit board, electromagnetic shielding is required in addition to hermetic sealing.
【０００３】一般に、このように気密封止と電磁シール
ドとを併せ持つパッケージ構造としては、抵抗溶接法に
より封止する金属ケースが知られている。この金属ケー
スは外部リードを保持するステムとキャップとの組み合
わせからなる。回路基板上に半導体素子を取り付けて金
ワイヤなどでボンディングした半導体装置を、ステム上
に固定しキャップを被せて封止する。Generally, a metal case sealed by resistance welding is known as a package structure having both hermetic sealing and electromagnetic shielding. This metal case consists of a combination of a stem and a cap that hold the external leads. A semiconductor device, in which a semiconductor element is mounted on a circuit board and bonded with gold wire or the like, is fixed on a stem and sealed with a cap.
【０００４】また最近では回路基板の中間層に第２の導
電層を形成し、フランジの無いキャップを被せ、回路基
板の外周端面で半田付けして第２の導電層とキャップと
を導通させて電磁シールドするパッケージ構造も提案さ
れている。Recently, a second conductive layer is formed on the intermediate layer of a circuit board, a cap without a flange is placed over the circuit board, and the second conductive layer and the cap are electrically connected by soldering on the outer peripheral edge of the circuit board. Package structures that provide electromagnetic shielding have also been proposed.
【０００５】[0005]
【発明が解決しようとする課題】上記従来技術のうち前
者の場合は、回路基板を収納する金属ケース（ステムと
キャップ）を必要とすることから、コスト高、重量増加
を招き、更には専用の封止装置が不可欠である等の欠点
があり、近年の軽薄短小化の要求に対応することが著し
く困難となっている。[Problems to be Solved by the Invention] Among the above conventional techniques, the former requires a metal case (stem and cap) to house the circuit board, which increases cost and weight, and furthermore requires a dedicated There are drawbacks such as the necessity of a sealing device, and it has become extremely difficult to meet the recent demands for miniaturization.
【０００６】また後者の場合は回路基板にキャップを被
せるだけの構成であるため、小型化軽量化できる利点は
あるものの、回路基板の端面でキャップを半田付けを行
うため、回路基板を１個ずつ分離した後、別々に封着し
なければならず、作業性が悪く量産化には不向きである
。In the latter case, the circuit board is simply covered with a cap, so although it has the advantage of being smaller and lighter, the cap is soldered to the edge of the circuit board, so the circuit boards are assembled one by one. After separation, they must be sealed separately, which is difficult to work with and unsuitable for mass production.
【０００７】本発明の目的は、上記のような従来技術の
欠点を解消し、気密性と電磁シールドとを併せ持ち、そ
れでいて小型軽量化でき、簡単な構造で封着作業性が良
好なため安価に量産できる半導体装置のパッケージ構造
を提供することである。The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, to provide both airtightness and electromagnetic shielding, yet to be small and lightweight, to have a simple structure and good sealing workability, and thus to be inexpensive. An object of the present invention is to provide a package structure for semiconductor devices that can be mass-produced.
【０００８】[0008]
【課題を解決するための手段】本発明は基本的には、回
路基板の上面に半導体素子を搭載した半導体装置を導電
性キャップで覆い気密シールする半導体装置のパッケー
ジ構造である。このようなパッケージ構造において、キ
ャップは周囲にフランジを有する形状をなし、回路基板
はその上面の前記フランジに対応する箇所に形成した第
１の導電層と、下面側を覆う第２の導電層と、前記第１
の導電層の真下でほぼ均等に分散し該第１の導電層と第
２の導電層との間を接続する多数の導電スルーホールを
有する。そしてフランジと第１の導電層との間を導電性
封着材により封着する。The present invention basically provides a package structure for a semiconductor device in which a semiconductor device having a semiconductor element mounted on the upper surface of a circuit board is covered with a conductive cap and hermetically sealed. In such a package structure, the cap has a shape with a flange around the periphery, and the circuit board has a first conductive layer formed on the upper surface of the cap at a location corresponding to the flange, and a second conductive layer covering the lower surface side. , said first
The conductive layer has a large number of conductive through-holes that are substantially evenly distributed beneath the conductive layer and connect between the first conductive layer and the second conductive layer. Then, the flange and the first conductive layer are sealed using a conductive sealing material.
【０００９】通常、第１の導体層は、回路基板の外周に
沿って枠状に形成する。単層の回路基板を用いる場合は
、その下面の半導体装置のリード電極を除くほぼ全面に
第２の導電層を形成する。多層回路基板を用いる場合は
、中間層のほぼ全面に第２の導電層を形成する。本発明
のパッケージ構造は、例えばハイブリッドＩＣ等に特に
好適である。[0009] Usually, the first conductor layer is formed in a frame shape along the outer periphery of the circuit board. When a single-layer circuit board is used, the second conductive layer is formed on almost the entire surface of the circuit board except for the lead electrodes of the semiconductor device on the lower surface. When a multilayer circuit board is used, the second conductive layer is formed on almost the entire surface of the intermediate layer. The package structure of the present invention is particularly suitable for, for example, hybrid ICs.
【００１０】0010
【作用】キャップのフランジと回路基板の第１の導電層
とを導電性封着材を用いて封着することにより、気密封
止が達成される。封止を回路基板の上面で行うため、多
数個取りが可能でなる。電磁シールドは、上方はキャッ
プにより、また側方と下方は導電性封着材、第１の導体
層、導電スルーホール、及び第２の導電層により達成さ
れる。側方の電磁シールドを受け持つ多数の導電スルー
ホールは、第１の導電層の真下に位置し、そのため回路
基板の面積は必要以上に増大することはなく、省スペー
ス化に貢献する。[Operation] Hermetic sealing is achieved by sealing the flange of the cap and the first conductive layer of the circuit board using a conductive sealing material. Since sealing is performed on the top surface of the circuit board, it is possible to manufacture multiple pieces. Electromagnetic shielding is achieved by the cap on the top and the conductive sealant, the first conductive layer, the conductive through-holes, and the second conductive layer on the sides and below. A large number of conductive through holes serving as side electromagnetic shields are located directly under the first conductive layer, so that the area of the circuit board does not increase more than necessary, contributing to space saving.
【００１１】[0011]
【実施例】図１は本発明における半導体装置のパッケー
ジ構造の一実施例を示す断面図であり、図２はその回路
基板の平面図である。この例は単層回路基板を用いる場
合である。回路基板１０は、アルミナあるいは窒化アル
ミニウムなどからなる。回路基板１０の上面に回路パタ
ーン１２を設けて各種半導体素子１４を搭載し、金ワイ
ヤ１６によって接続して半導体装置を構成する。図２の
一点鎖線でしめす領域（符号１８で示す）が半導体装置
形成部分である。このような回路基板１０の上に金属製
のキャップ２０を被せる。本実施例ではキャップ２０は
、その外周下端部分に水平方向外向きに突出するフラン
ジ２２を有する形状をなしており、全体にニッケル・メ
ッキが施されている。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view showing an embodiment of a package structure for a semiconductor device according to the present invention, and FIG. 2 is a plan view of a circuit board thereof. This example is a case where a single layer circuit board is used. The circuit board 10 is made of alumina, aluminum nitride, or the like. A circuit pattern 12 is provided on the upper surface of the circuit board 10, various semiconductor elements 14 are mounted thereon, and connected by gold wires 16 to form a semiconductor device. The area indicated by the dashed line in FIG. 2 (indicated by reference numeral 18) is the area where the semiconductor device is formed. A metal cap 20 is placed over such a circuit board 10. In this embodiment, the cap 20 has a flange 22 projecting horizontally outward at the lower end of its outer periphery, and is entirely plated with nickel.
【００１２】本実施例において回路基板１０には、その
上面（半導体素子搭載面）の前記フランジ２２に対応す
る箇所に枠状の第１の導電層２４を形成し、下面のほぼ
全体（リード電極２６及びその近傍を除く）を覆うよう
に第２の導電層２８を形成する。そして前記第１の導電
層２４の真下に多数の導電スルーホール３０を形成して
第１の導電層２４と第２の導電層２８とを接続する。こ
れらの導電スルーホール３０は、回路基板１０の周囲で
ほぼ均等に分散するように設ける。この例では１２本ほ
ぼ等間隔で形成してある。これらの導電層は、厚膜印刷
、エッチング、選択メッキ、積層法やスルーホール技術
を用いて容易に行える。In this embodiment, a frame-shaped first conductive layer 24 is formed on the upper surface (semiconductor element mounting surface) of the circuit board 10 at a location corresponding to the flange 22, and almost the entire lower surface (lead electrode 26 and its vicinity). Then, a large number of conductive through holes 30 are formed directly under the first conductive layer 24 to connect the first conductive layer 24 and the second conductive layer 28. These conductive through holes 30 are provided so as to be almost evenly distributed around the circuit board 10. In this example, 12 wires are formed at approximately equal intervals. These conductive layers can be easily created using thick film printing, etching, selective plating, lamination methods, or through-hole techniques.
【００１３】実際の作業手順では、まず上記のように回
路基板１０に各種導電層を形成した後、半導体素子１４
等を搭載して装置を構成する。次に第１の導電層２４上
に、例えば錫−鉛系半田プリフォームのような導電性封
着材３２を載せ、それを介してキャップ２０のフランジ
２２を載せてリフロー炉などを通し結合する。このよう
にして気密封止と電磁シールドを同時に満足するパッケ
ージ構造を得ることができる。In the actual work procedure, first, various conductive layers are formed on the circuit board 10 as described above, and then the semiconductor element 14 is formed.
etc. to configure the device. Next, a conductive sealing material 32 such as a tin-lead solder preform is placed on the first conductive layer 24, and the flange 22 of the cap 20 is placed thereon and bonded through a reflow oven or the like. . In this way, a package structure that simultaneously satisfies hermetic sealing and electromagnetic shielding can be obtained.
【００１４】なお、導電性封着材３２として錫−鉛系半
田ペーストを用いる場合には、半導体素子を搭載する前
に第１の導電層２４の封着面に半田ペーストを印刷し、
リフロー炉を通して半田層を設けておくことも可能であ
る。また例えば導電性封着材として、耐熱性の高い高温
半田や導電性フィラー入り封止用ガラスを用い、回路基
板の下面のリード電極に錫−鉛系普通半田を施すとＳＭ
Ｄ（表面実装部品）対応型のパッケージ構造にもなる。When using a tin-lead solder paste as the conductive sealing material 32, the solder paste is printed on the sealing surface of the first conductive layer 24 before the semiconductor element is mounted.
It is also possible to provide a solder layer through a reflow oven. For example, if high-temperature solder with high heat resistance or sealing glass containing conductive filler is used as a conductive sealing material, and tin-lead ordinary solder is applied to the lead electrodes on the bottom surface of the circuit board, SM
It also has a package structure compatible with D (surface mount components).
【００１５】本発明では回路基板の上面でキャップを結
合するため、１枚の基板に上記のような導電層及び導電
スルーホールを持つ多数の回路基板部分を並べて一度に
形成し、それぞれ半導体素子などを搭載して半導体装置
を構成した後、金属製キャップを順次取り付け封着して
から、１個ずつに切断分離する工程を採用でき、それに
よって安価に大量に製造できる。In the present invention, in order to bond the cap on the upper surface of the circuit board, a large number of circuit board parts having the above-mentioned conductive layers and conductive through holes are formed at once on one board, and each part is connected to a semiconductor element, etc. After configuring the semiconductor device by mounting the metal caps, a process can be adopted in which metal caps are successively attached and sealed, and then the semiconductor devices are cut and separated one by one, thereby making it possible to manufacture them in large quantities at low cost.
【００１６】図３は本発明の他の実施例の断面図である
。この例は多層回路基板を用いる場合である。基本的な
構成は前記の実施例と同様であるから、対応する部分に
は同一符号を付し、それらについての詳細な説明は省略
する。回路基板４０は、上面に回路パターン１２を設け
ると共に、フランジ２２に対応する箇所に枠状の第１の
導電層２４を形成し、中間層のほぼ全体（リード引出し
用導電スルーホール部４２及びその近傍を除く）に第２
の導電層４４を形成する。そして前記第１の導電層２４
の真下に多数の導電スルーホール３０を形成して第１の
導電層２４と第２の導電層４４とを接続する。これらの
導電スルーホール３０は、回路基板４０の周囲でほぼ均
等に分布するように設ける。このような回路基板４０に
半導体素子１４等を搭載し、金ワイヤ１６で接続して半
導体装置を構成する。次に第１の導電層２４上に導電性
封着材３２を介してキャップ２０のフランジ２２を載せ
て結合する。FIG. 3 is a cross-sectional view of another embodiment of the invention. An example of this is a case where a multilayer circuit board is used. Since the basic configuration is the same as that of the previous embodiment, corresponding parts are denoted by the same reference numerals, and detailed explanation thereof will be omitted. The circuit board 40 has a circuit pattern 12 on its upper surface, a frame-shaped first conductive layer 24 at a location corresponding to the flange 22, and almost the entire intermediate layer (the conductive through-hole section 42 for leading out and its conductive layer 24). (excluding neighbors)
A conductive layer 44 is formed. and the first conductive layer 24
A large number of conductive through holes 30 are formed directly under the conductive layer 44 to connect the first conductive layer 24 and the second conductive layer 44 . These conductive through holes 30 are provided so as to be approximately evenly distributed around the circuit board 40. Semiconductor elements 14 and the like are mounted on such a circuit board 40 and connected with gold wires 16 to form a semiconductor device. Next, the flange 22 of the cap 20 is placed on the first conductive layer 24 via the conductive sealing material 32 and bonded.
【００１７】また本発明は、大きな回路基板の一部に形
成した半導体装置部分にキャップを被せて気密封止と電
磁シールドを施す場合にも適用できる。The present invention can also be applied to the case where a semiconductor device formed on a part of a large circuit board is covered with a cap to provide hermetic sealing and electromagnetic shielding.
【００１８】[0018]
【発明の効果】本発明は上記のように周囲にフランジを
有するキャップを用い、回路基板の上面の前記フランジ
に対応する箇所に第１の導電層を形成して、フランジと
第１の導電層との間を導電性封着材により封着するから
、気密シールができる。また回路基板は、下面側を覆う
第２の導電層と、ほぼ均等に分散し両導電層間を接続す
る多数の導電スルーホールを有し、導電性キャップ及び
導電性封着材を用いるため、上方はキャップにより、側
方及び下方は導電性封着材、第１の導電層、導電スルー
ホール、及び第２の導電層で囲まれ、電磁シールドされ
る。Effects of the Invention The present invention uses a cap having a flange around the periphery as described above, forms a first conductive layer at a location corresponding to the flange on the upper surface of a circuit board, and connects the flange and the first conductive layer. Since the conductive sealing material is used to seal between the two, an airtight seal can be achieved. In addition, the circuit board has a second conductive layer that covers the lower surface side and a large number of conductive through holes that are almost evenly distributed and connects both conductive layers, and uses a conductive cap and a conductive sealing material. is surrounded by a cap on the sides and below by a conductive sealing material, a first conductive layer, a conductive through hole, and a second conductive layer, and is electromagnetically shielded.
【００１９】また本発明では、第１の導電層と第２の導
電層間を接続する導電スルーホールが、前記第１の導電
層の真下に位置しているため、回路基板サイズは気密シ
ールに必要な最小限度に小型化でき、省スペース化を図
ることがでる。重量の大きい金属ステムも不要なため軽
量化を図ることもできる。更に基板構造上、容易にＳＭ
Ｄ対応型のパッケージ構造になる。Further, in the present invention, since the conductive through hole connecting the first conductive layer and the second conductive layer is located directly below the first conductive layer, the circuit board size is limited to the size necessary for airtight sealing. It is possible to reduce the size to the minimum possible size and save space. It also eliminates the need for a heavy metal stem, making it possible to reduce weight. Furthermore, due to the substrate structure, it is easy to use SM.
It becomes a D-compatible package structure.
【００２０】また本発明では、キャップを回路基板の上
面で封着するため、同一基板に多数の回路基板部分を一
度に並べて形成し、そのまま半導体装置を構成した後、
順次キャップを被せて封着し、最後に１個１個に切断分
離する製造工程を採用できるため、量産化に適し、コス
トを低減できる。Furthermore, in the present invention, since the cap is sealed on the upper surface of the circuit board, a large number of circuit board parts are formed on the same board at once, and after configuring the semiconductor device as it is,
It is possible to employ a manufacturing process in which caps are sequentially placed and sealed, and finally the caps are cut and separated one by one, making it suitable for mass production and reducing costs.
【図１】本発明に係るパッケージ構造の一実施例を示す
断面図。FIG. 1 is a sectional view showing an embodiment of a package structure according to the present invention.
【図２】図１のパッケージで用いる回路基板の平面図。FIG. 2 is a plan view of a circuit board used in the package of FIG. 1.
【図３】本発明に係るパッケージ構造の他の実施例を示
す断面図。FIG. 3 is a sectional view showing another embodiment of the package structure according to the present invention.
１０ 回路基板 １４ 半導体素子 ２０ キャップ ２２ フランジ ２４ 第１の導電層 ２８ 第２の導電層 ３０ 導電スルーホール ３２ 導電性封着材 10 Circuit board 14 Semiconductor element 20 Cap 22 Flange 24 First conductive layer 28 Second conductive layer 30 Conductive through hole 32 Conductive sealing material
Claims (3)
た半導体装置を導電性キャップで覆い気密シールするパ
ッケージにおいて、キャップは周囲にフランジを有し、
回路基板は、その上面の前記フランジに対応する箇所に
形成した第１の導電層と、下面側を覆う第２の導電層と
、前記第１の導電層の真下でほぼ均等に分散し該第１の
導電層と第２の導電層との間を接続する多数の導電スル
ーホールとを有し、フランジと第１の導電層との間を導
電性封着材により封着することを特徴とする半導体装置
のパッケージ構造。1. A package in which a semiconductor device having a semiconductor element mounted on the top surface of a circuit board is covered and hermetically sealed with a conductive cap, the cap having a flange around the periphery,
The circuit board includes a first conductive layer formed on the upper surface of the circuit board at a location corresponding to the flange, a second conductive layer covering the lower surface side, and a first conductive layer that is almost evenly distributed directly below the first conductive layer. It has a large number of conductive through holes connecting the first conductive layer and the second conductive layer, and the flange and the first conductive layer are sealed with a conductive sealing material. package structure of semiconductor devices.
て枠状に形成し、第２の導電層を回路基板の下面の半導
体装置のリード電極を除くほぼ全面に形成した請求項１
記載のパッケージ構造。2. Claim 1, wherein the first conductive layer is formed in a frame shape along the outer periphery of the circuit board, and the second conductive layer is formed on almost the entire surface of the lower surface of the circuit board except for the lead electrodes of the semiconductor device.
Package structure as described.
て枠状に形成し、第２の導電層を回路基板の中間層のほ
ぼ全面に形成した請求項１記載のパッケージ構造。3. The package structure according to claim 1, wherein the first conductive layer is formed in a frame shape along the outer periphery of the circuit board, and the second conductive layer is formed on substantially the entire surface of the intermediate layer of the circuit board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41119790A JP2849479B2 (en) | 1990-12-17 | 1990-12-17 | Package structure of semiconductor device |
| TW083102121A TW377499B (en) | 1990-12-17 | 1992-06-02 | Method of manufacturing an electrode external to semiconductor package and the same apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP41119790A JP2849479B2 (en) | 1990-12-17 | 1990-12-17 | Package structure of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04216652A true JPH04216652A (en) | 1992-08-06 |
| JP2849479B2 JP2849479B2 (en) | 1999-01-20 |
Family
ID=18520236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP41119790A Expired - Fee Related JP2849479B2 (en) | 1990-12-17 | 1990-12-17 | Package structure of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2849479B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11238818A (en) * | 1998-02-20 | 1999-08-31 | Kyocera Corp | Package for accommodating electronic component |
| KR100698570B1 (en) * | 2005-11-03 | 2007-03-21 | 신테크 컴퍼니, 리미티드 | Package device with electromagnetic interference shield |
| JP2010067989A (en) * | 2002-07-19 | 2010-03-25 | Panasonic Corp | Module component |
| JP2015015477A (en) * | 2014-08-06 | 2015-01-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2016076669A (en) * | 2014-10-09 | 2016-05-12 | クラスターテクノロジー株式会社 | Semiconductor element mounting package and method of manufacturing the same, and substrate plate for manufacturing package |
| JP2020014064A (en) * | 2018-07-13 | 2020-01-23 | 日本電波工業株式会社 | Piezoelectric device |
-
1990
- 1990-12-17 JP JP41119790A patent/JP2849479B2/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11238818A (en) * | 1998-02-20 | 1999-08-31 | Kyocera Corp | Package for accommodating electronic component |
| JP2010067989A (en) * | 2002-07-19 | 2010-03-25 | Panasonic Corp | Module component |
| JP2010080968A (en) * | 2002-07-19 | 2010-04-08 | Panasonic Corp | Method of manufacturing module component |
| KR100698570B1 (en) * | 2005-11-03 | 2007-03-21 | 신테크 컴퍼니, 리미티드 | Package device with electromagnetic interference shield |
| JP2015015477A (en) * | 2014-08-06 | 2015-01-22 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
| JP2016076669A (en) * | 2014-10-09 | 2016-05-12 | クラスターテクノロジー株式会社 | Semiconductor element mounting package and method of manufacturing the same, and substrate plate for manufacturing package |
| JP2020014064A (en) * | 2018-07-13 | 2020-01-23 | 日本電波工業株式会社 | Piezoelectric device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2849479B2 (en) | 1999-01-20 |
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| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |