JPS6365649A - Pickage for semiconductor - Google Patents

Pickage for semiconductor

Info

Publication number
JPS6365649A
JPS6365649A JP61210223A JP21022386A JPS6365649A JP S6365649 A JPS6365649 A JP S6365649A JP 61210223 A JP61210223 A JP 61210223A JP 21022386 A JP21022386 A JP 21022386A JP S6365649 A JPS6365649 A JP S6365649A
Authority
JP
Japan
Prior art keywords
metallized
aluminum oxide
cap
wall
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61210223A
Other languages
Japanese (ja)
Inventor
Toru Kamata
徹 鎌田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61210223A priority Critical patent/JPS6365649A/en
Publication of JPS6365649A publication Critical patent/JPS6365649A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To maintain airtightness by a method wherein a through-hole metallized layer on a ceramic cavity side wall electrically connecting a cap-sealing metallized pattern and external lead fitting metallized pattern is provided on a ceramic cavity inner wall. CONSTITUTION:A cap-sealing metallized layer 4 is provided on an aluminum oxide sheet 1 and, on its inner wall, a side-wall through-hole metallized layer 6 is provided by through-hole metallization. A metallized wiring layer 5 and external lead fitting metallized layer 10 are provided on an aluminum oxide sheet 2. The aluminum oxide sheets 1 and 2 with metallized elements thereon are laminated, and then baked for the formation of an aluminum oxide cavity. An external lead 9 is bonded with Ag-Cu solder to the aluminum oxide cavity. Next, metal portions all over the package are subjected to plating with Ni and then with Au. A semiconductor element 8 is die-bonded to this semiconductor package. Wire-bonding is accomplished and, finally, a cap 7 is sealed by Au-Sn solder 3 for the construction of a semiconductor device.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体用パッケージに関し、特にキャップがA
u−3n共晶合金等の低融点ソルダによって封止される
マイクロ波半導体用バ・1ケージの構造に関する。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a semiconductor package, and in particular, the cap is A
The present invention relates to the structure of a microwave semiconductor package sealed with a low melting point solder such as U-3N eutectic alloy.

〔従来の技術〕[Conventional technology]

従来の半導体用パッケージの一例を示す縦断面図の第3
図に示すように、従来、キャップ7をAu−5nソルダ
3で封止してなる半導体パッケージにおいては、キャッ
プシール用メタライズパターンはセラミックキャビテイ
外側壁の一部を通じて外部リード9と電気的に導通され
る構造となっている。これは、キャップシール用メタラ
イズパターンへのめっき作業を容易にすると共にメタラ
イズパターンのサイズに起因する高周波での共振周波数
を上げるために行なわれている。
The third vertical cross-sectional view showing an example of a conventional semiconductor package
As shown in the figure, in a conventional semiconductor package in which a cap 7 is sealed with an Au-5n solder 3, a metallized pattern for cap sealing is electrically connected to an external lead 9 through a part of the outer wall of a ceramic cavity. It has a structure that allows This is done to facilitate the plating work on the metallized pattern for the cap seal and to increase the resonance frequency at high frequencies due to the size of the metallized pattern.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述しな従来の半導体用セラミックパッケージは、高周
波領域での電気的特性を向上させるためパッケージサイ
ズは極力小型化されている。マイクロ波用パッケージを
プリント配線板へ実装する方法として半田付けが行なわ
れるが、高周波信号の入出力端子を構成する半導体パッ
ケージの外部リードはできるだけリード根元でプリント
配線板へ半田付けすることが望ましい。パッケージ本体
から半田付は部までの距離が大きくなると高周波特性が
劣化してくるのが一般的である。したが−〉で、従来の
パッケージにおいてはキャップのAu−3nシ一ル部と
リードの5n−Pb半田付は部は接近しており、しかも
セラミック外側壁のメタライズ層が存在するため、外部
リード9を半田付けする際に5n−Pb半田11はパッ
ケージの外側壁メタライズ層5を通じてキャップシール
のAu−8n部まで流れて、Au−5nソルダ3をアタ
ックして気密性等を損なうという欠点がある。
In the conventional ceramic package for semiconductors as described above, the package size is minimized to improve electrical characteristics in a high frequency range. Soldering is used as a method for mounting a microwave package on a printed wiring board, and it is desirable to solder the external leads of a semiconductor package, which constitute input/output terminals for high-frequency signals, to the printed wiring board as much as possible at the base of the lead. Generally, as the distance from the package body to the soldering part increases, the high frequency characteristics deteriorate. However, in the conventional package, the Au-3n seal part of the cap and the 5n-Pb solder part of the lead are close to each other, and there is a metallized layer on the ceramic outer wall, so the external lead When soldering 9, the 5n-Pb solder 11 flows through the outer wall metallized layer 5 of the package to the Au-8n portion of the cap seal, attacking the Au-5n solder 3 and impairing airtightness. .

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体用パッケージは、キャップシール用メタ
ライズパターンを有する積層セラミックパッケージにお
いて、前記キャップシール用メタライズパターンはセラ
ミックキャビティの内側壁のスルーホールメタライズ層
を通じて少なくとも1つの外部リードと電気的に導通さ
れていることを特徴とする。
The semiconductor package of the present invention is a multilayer ceramic package having a metallized pattern for cap sealing, wherein the metallized pattern for cap sealing is electrically connected to at least one external lead through a through-hole metallized layer on the inner wall of the ceramic cavity. It is characterized by the presence of

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)、(b)は本発明の第1の実施例の縦断面
図、上面内観図である。
FIGS. 1(a) and 1(b) are a vertical sectional view and a top internal view of a first embodiment of the present invention.

同図において、アルミナシート1にはキャップシール用
メタライズ層4が、またその内側壁にはスルーホールメ
タライズ法により側面スルーボールメタライズ層6が設
けられ、アルミナシート2にはメタライズ配線層5及び
外部リード取付はメタライズ層10が設けられている。
In the same figure, an alumina sheet 1 is provided with a metallized layer 4 for cap sealing, a side through-ball metallized layer 6 is provided on its inner wall by a through-hole metallization method, and an alumina sheet 2 is provided with a metalized wiring layer 5 and an external lead layer. For attachment, a metallized layer 10 is provided.

メタライズが形成されたアルミナシート1.2は積層、
焼成されてアルミナキャビティをなす。外部リード9は
アルミナキャビティにAg−Cuろう付けされ、その後
パッケージ全体の金属部にNiめっき、AUめっ壱(図
中省略〉が順次族される。
Alumina sheets 1.2 on which metallization is formed are laminated,
It is fired to form an alumina cavity. The external lead 9 is brazed with Ag-Cu to the alumina cavity, and then Ni plating and AU plating (not shown) are sequentially applied to the metal parts of the entire package.

このように構成された半導体パッケージには半導体素子
8がダイボンディング、ワイヤボンディングされ、最後
にキャップ7がAu−3nソルダ3によって封止され半
導体装置として完成する。
The semiconductor element 8 is die-bonded and wire-bonded to the semiconductor package thus constructed, and finally the cap 7 is sealed with the Au-3n solder 3 to complete the semiconductor device.

次に、第2図は本発明の第2の実施例の上面内観図であ
る。
Next, FIG. 2 is a top internal view of a second embodiment of the present invention.

同図においては、側面スルーポールメタライズ層26は
第1の実施例とは異なり丸孔で構成され、セラミックキ
ャビティの内部コーナに設けられている。
In the figure, the side surface through-pole metallization layer 26 is formed of a round hole, unlike the first embodiment, and is provided at the inner corner of the ceramic cavity.

この第2の実施例においても、セラミックの側面導通パ
ターンは内部に設けられており、外部リード9の半田付
は時に半田がAu−5nソルダを、  アタックするこ
とはない。
In this second embodiment as well, the ceramic side conductive pattern is provided inside, so that the solder does not attack the Au-5n solder when soldering the external leads 9.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、キャップシール用メタラ
イズパターンと外部リード取付はメタライズパターンと
を電気的に導通するセラミックキャビティ側壁のスルー
ホールメタライズ層をセラミックキャビティ内壁に設け
ることにより、半導体装置が半田付は実装される際に5
n−Pb半田がキャップシール用Au−5nソルダをア
タックすることがなくなるので、気密性を損なわない効
果がある。
As explained above, the present invention provides a through-hole metallized layer on the ceramic cavity side wall that electrically connects the cap seal metallized pattern and the external lead attachment to the ceramic cavity side wall, so that the semiconductor device can be soldered. 5 when implemented
Since the n-Pb solder does not attack the Au-5n solder for the cap seal, there is an effect that the airtightness is not impaired.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、(b)は本発明の半導体用パッケージの
第1の実施例の縦断面図、上面内観図、第2図は本発明
の第2の実施例の上面内観図、第3図は従来の半導体用
パッケージの一例を示す縦断面図である。 1.2・・・アルミナシート、3・・・Au−5nソル
ダ、4・・・キャップシール用メタライズ層、5・・・
メタライズ配線層、6.26・・・側面スルーホールメ
タライズ層、7・・・キャップ、8・・・半導体素子、
9・・・外部リード、10・・・外部リード取付はメタ
ライ−1−l 躬1図 (a) (b) 第2図 躬3図 乙とブリ)ト西らf兼玖
1(a) and (b) are a vertical sectional view and a top internal view of a first embodiment of a semiconductor package of the present invention, and FIG. 2 are a top internal view and a top internal view of a second embodiment of the present invention. FIG. 3 is a longitudinal sectional view showing an example of a conventional semiconductor package. 1.2... Alumina sheet, 3... Au-5n solder, 4... Metallized layer for cap seal, 5...
Metallized wiring layer, 6.26... Side through hole metallized layer, 7... Cap, 8... Semiconductor element,
9... External lead, 10... External lead installation is metallized - 1-l Fig. 1 (a) (b) Fig. 2 Fig. 3

Claims (1)

【特許請求の範囲】[Claims] キャップシール用メタライズパターンを有する積層セラ
ミックパッケージにおいて、前記キャップシール用メタ
ライズパターンはセラミックキャビティの内側壁のスル
ーホールメタライズ層を通じて少なくとも1つの外部リ
ードと電気的に導通されていることを特徴とする半導体
用パッケージ。
A laminated ceramic package having a cap seal metallization pattern, wherein the cap seal metallization pattern is electrically connected to at least one external lead through a through-hole metallization layer on an inner wall of a ceramic cavity. package.
JP61210223A 1986-09-05 1986-09-05 Pickage for semiconductor Pending JPS6365649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61210223A JPS6365649A (en) 1986-09-05 1986-09-05 Pickage for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61210223A JPS6365649A (en) 1986-09-05 1986-09-05 Pickage for semiconductor

Publications (1)

Publication Number Publication Date
JPS6365649A true JPS6365649A (en) 1988-03-24

Family

ID=16585825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61210223A Pending JPS6365649A (en) 1986-09-05 1986-09-05 Pickage for semiconductor

Country Status (1)

Country Link
JP (1) JPS6365649A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392539A2 (en) * 1989-04-17 1990-10-17 Sumitomo Electric Industries, Ltd. Semiconductor device package and sealing method therefore
EP1278242A2 (en) * 2001-06-27 2003-01-22 Sumitomo Electric Industries, Ltd. Hermetically sealing enclosure for housing photo-semiconductor devices and photo-semiconductor module incorporating the enclosure
CN109494197A (en) * 2018-11-13 2019-03-19 中国电子科技集团公司第十三研究所 Ceramic package shell

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574147A (en) * 1980-06-10 1982-01-09 Nec Corp Semiconductor device and its manufacturing process
JPS6329949B2 (en) * 1984-07-31 1988-06-15 Nippon Kokuen Kogyo Kk

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS574147A (en) * 1980-06-10 1982-01-09 Nec Corp Semiconductor device and its manufacturing process
JPS6329949B2 (en) * 1984-07-31 1988-06-15 Nippon Kokuen Kogyo Kk

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0392539A2 (en) * 1989-04-17 1990-10-17 Sumitomo Electric Industries, Ltd. Semiconductor device package and sealing method therefore
EP1278242A2 (en) * 2001-06-27 2003-01-22 Sumitomo Electric Industries, Ltd. Hermetically sealing enclosure for housing photo-semiconductor devices and photo-semiconductor module incorporating the enclosure
EP1278242A3 (en) * 2001-06-27 2004-03-17 Sumitomo Electric Industries, Ltd. Hermetically sealing enclosure for housing photo-semiconductor devices and photo-semiconductor module incorporating the enclosure
CN109494197A (en) * 2018-11-13 2019-03-19 中国电子科技集团公司第十三研究所 Ceramic package shell

Similar Documents

Publication Publication Date Title
US4038488A (en) Multilayer ceramic multi-chip, dual in-line packaging assembly
US5635751A (en) High frequency transistor with reduced parasitic inductance
US10249564B2 (en) Electronic component mounting substrate, electronic device, and electronic module
JP2938344B2 (en) Semiconductor device
JP2728322B2 (en) Semiconductor device
JPS6365649A (en) Pickage for semiconductor
JPH0322060B2 (en)
JPH01168045A (en) Hermetically sealed circuit device
US4297722A (en) Ceramic package for semiconductor devices having metalized lead patterns formed like a floating island
JPH04216652A (en) Package structure of semiconductor device
JP3445761B2 (en) Ceramic package for electronic devices
JP3800358B2 (en) Terminal of semiconductor hermetically sealed container and the same container
JPH05347324A (en) Semiconductor package
JP4454165B2 (en) Electronic component mounting board
JPH0812888B2 (en) Package for semiconductor device
JPH0710495Y2 (en) Semiconductor device
JPH083011Y2 (en) Package for semiconductor device
JP2509904B2 (en) Package for semiconductor device
JP2666588B2 (en) Semiconductor device
JP2710893B2 (en) Electronic components with leads
JP3051225B2 (en) Package for integrated circuit
JPS62114246A (en) Semiconductor device
JPS6336688Y2 (en)
JPH05166965A (en) Package structure
JPH0629419A (en) Semiconductor device