JPH0794630A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the degree of freedom in the electrical connection of a chip device in a packaged semiconductor device and to allow packaging of a chip device even in a resin sealed semiconductor device. CONSTITUTION:In order to seal a semiconductor element 2 mounted on a case board 1, a circuit pattern is formed on the inner face of a cap 7 applied thereto. A chip capacitor 8 being connected electrically with the circuit pattern is then mounted and the circuit pattern is formed such that it is connected electrically with external lead pins arranged on the case board 1 when the cap 7 is applied thereto. When the chip capacitor 8 is mounted on the cap 7, the chip capacitor 8 can be connected electrically with the semiconductor element 2 through the circuit pattern and the external lead pins 3 and thereby the degree of freedom is increased in the configuration of circuitry.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a chip capacitor inside a package.

[0002]

2. Description of the Related Art With the recent increase in operation speed of semiconductor devices,
Power supply noise is generated by the high-speed switching operation,
There is a possibility that the stable operation of a semiconductor device or a device in which it is mounted deteriorates. Therefore, it has been attempted to incorporate a capacitor for absorbing this kind of noise in the package of the semiconductor device. FIG. 6 is a sectional view showing an example thereof, which is described in Japanese Patent Application Laid-Open No. 1-108751. A recess 101a is formed in the center of the upper surface of the ceramic case substrate 101 to mount the semiconductor element 102, and the wiring pattern 103 formed around the recess 101a is electrically connected by a metal wire 104. In addition, a plurality of external lead pins 105 are provided on the lower surface of the case substrate 101.
Are planted and connected to the wiring pattern 103.

Further, a cap 106 made of a conductive material is provided on the upper surface of the case substrate 101 to form the conductive seal ring 10.
It is attached via 7 to seal the semiconductor element and the like. In addition, the chip capacitor 10 is provided on the inner surface of the cap 106.
8 of the chip capacitors 108 is connected to the wiring pattern 103 when the cap 106 is attached to the case substrate 101. Therefore, if the chip capacitor 108 is connected to the cap 106, the other electrode of the chip capacitor 108 can be connected to the wiring pattern 103 at the same time when the cap 106 is attached to the case substrate 101, and the chip capacitor 108 serves as a power source. It is possible to absorb the power supply noise by inserting it to the ground.

[0004]

In such a conventional semiconductor device, since one electrode of the chip capacitor 108 is connected to the cap 106, the cap itself must be made of a conductive material and ground. In order to do so, it is necessary to attach it to the case substrate 101 using the conductive seal ring 107. Therefore, the chip capacitor 1
This configuration cannot be applied when one electrode of 08 is not grounded. Further, when a plurality of chip capacitors are incorporated, one electrode of all the chip capacitors is commonly connected via the cap 106, which is a constraint in forming a circuit.

Further, since the respective electrodes of the chip capacitor 108 are connected to the cap 106 and the case substrate 101, when there is a difference in thermal expansion coefficient between the two, the electrode portion of the chip capacitor 108 is changed by the temperature change of the semiconductor device. There is also a problem that stress is generated in the connection and the connection is easily damaged. In addition, the semiconductor element 10 mounted on the case substrate 101
2 is sealed with resin or the like, the semiconductor element 10
2. The wiring pattern 103 may be resin-sealed together with the metal wire 104. In such a case, it is difficult to connect the other electrode of the chip capacitor 108 to the wiring pattern 103. It should be noted that such a problem occurs not only in the case of the chip capacitor but also in the case of incorporating a chip resistor or other chip parts in the package of the semiconductor device. It is an object of the present invention to provide a semiconductor device in which the degree of freedom of electrical connection of chip components to be embedded is increased and the chip components can be embedded even in a resin-sealed semiconductor device.

[0006]

According to the present invention, a circuit pattern is formed on an inner surface of a cap which is attached to a case substrate and seals a semiconductor element, and a chip component electrically connected to the circuit pattern is mounted. Moreover, when the cap is attached to the case substrate, the circuit pattern is electrically connected to the external lead pin provided on the case substrate. The cap forms a required circuit pattern on its inner surface, forms a pad for a chip component in a part of this circuit pattern, and connects the other part of the circuit pattern to a through hole provided in the cap,
When the cap is attached to the case substrate, the through hole is inserted into the external lead pin and electrically connected to the external lead pin.

[0007]

Since the chip component is mounted on the circuit pattern provided on the cap and the circuit pattern is electrically connected to the semiconductor element through the external lead pin, it is not necessary to connect the chip component to the case substrate. Therefore, it is possible to freely design a circuit without electrically connecting the chip component to the cap, and solve the problems associated with the thermal stress on the chip component and the resin sealing of the semiconductor element.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention, (a) is a bottom view,
(B) is the AA sectional view taken on the line. The print case substrate 1 is formed in a rectangular plate shape, and a recess 1a is formed in the center of the lower surface of the print case substrate 1. The semiconductor element 2 is mounted in the recess 1a with an adhesive or the like. A wiring pattern 4 is formed around the recess 1a on the lower surface of the case substrate 1, and a plurality of external lead pins 3 connected to the wiring pattern 4 are planted on the lower surface of the case substrate 1. That is, the case substrate 1 is formed of a resin material such as glass cloth epoxy, glass cloth triazine, glass cloth polyimide, and the external lead pins 3 are formed of phosphor bronze, kovar, 42 alloy, etc., and the surface thereof is covered with solder. There is. Then, a metal thin film is formed on the lower surface of the case substrate 1, the wiring pattern 4 is formed by patterning the metal thin film by a photolithography technique, and a through hole is formed in the case substrate 1. The external lead pins 3 are planted.

The semiconductor element 2 is electrically connected to the wiring pattern 4 by the metal wire 5, and further electrically connected to the external lead pin 3 via the wiring pattern 4. A resin 6 is coated so as to cover the semiconductor element 2, the metal wire 5, and the inner peripheral portion of the wiring pattern 4, and these are resin-sealed. Here, after the resin is sealed, the same resin is further supplied thereon to fill the space between the resin and the cap 7 attached from the outside.

The cap 7 is shown in a plan view and BB in FIG.
As shown in the line enlarged cross-sectional view, it is formed in a rectangular shallow dish shape smaller than the case substrate 1. Here, the cap 7
Is formed of a metal core substrate, has a metal core portion 71 formed of aluminum or copper at the center, and has an insulating film 72 made of epoxy resin or the like on the outer surface and the inner surface, respectively.
73 is formed. Then, on the inner surface, a circuit pattern 74 is formed of a conductive thin film on the insulating film 73 by a photolithography technique, and a chip capacitor pad 74a is formed on a part of the circuit pattern 74.

The other portion of the circuit pattern 74 is extended to the peripheral portion of the cap 7 and a through hole 74b is formed in the peripheral portion. In this embodiment, the external lead pin 3 described above is provided at a plurality of locations on the periphery of the cap 7.
With a pitch dimension corresponding to, a semicircular shape is projected outward, and a through hole 74b is formed in this projected portion. The area of the circuit pattern 74 other than the pads 74a and the through holes 74b is covered with an insulating film 75 called a solder resist.

Then, the chip capacitor 8 is connected to the chip capacitor pad 74a of the circuit pattern 74 by the solder reflow method. Then, as shown in FIG. 1, this cap 7 is attached to the lower surface of the case substrate 1 on which the semiconductor element 2 is mounted. When attaching this, cap 7
The through-holes 74b provided in the above are inserted into the corresponding external lead pins 3, the cap 7 is temporarily fixed, and then the solder dip is performed to solder the through-holes 74b of the cap 7 and the external lead pins 3 to each other. 7 is attached to the case substrate 1. Note that FIG. 3 is a flowchart showing an outline of the manufacturing process of the semiconductor device described above.

Therefore, in the semiconductor device having this structure,
The chip capacitor 8 mounted on the cap 7 is to be connected to the external lead pin 3 via the circuit pattern 74 and the through hole 74b, and is also electrically connected to the semiconductor element 2 via the wiring pattern 4 at the external lead pin 3. Therefore, it is possible to configure an arbitrary circuit. Then, the chip capacitor 8 will be installed inside the package by utilizing the circuit pattern 74 provided on the cap 7, but since the circuit pattern 74 is not directly electrically connected to the cap 7, the chip capacitor 8 Can have any circuit configuration. Therefore,
The chip capacitor is not limited to the noise absorbing chip capacitor connected between the ground and the power supply, and can be installed as a chip capacitor for any purpose. In addition, it becomes possible to arbitrarily connect each of the plurality of chip capacitors to the circuit. As a result, the cap 7 is not necessarily made of a conductive material and is not grounded.

Further, since the chip capacitor 8 need only be mounted on the cap 7 and does not need to be directly electrically connected to the case substrate 1, thermal stress is exerted regardless of the difference in thermal expansion coefficient between the cap 7 and the case substrate 1. Does not affect, and even if the wiring pattern 4 of the case substrate 1 is covered with resin, its electrical connection is not affected, and it can be applied to a resin-sealed package. The chip capacitor 8
When changing the external lead pin 3 for connecting the, the position of the through hole 74b provided on the outer peripheral portion of the cap 7
It may be changed according to the position of the external lead pin 3 to be connected. Further, the circuit pattern 74 may be formed in accordance with this.

FIG. 4 is a sectional view of another embodiment of the present invention, in which parts equivalent to those of the embodiment of FIG. 1 are designated by the same reference numerals. In this embodiment, in addition to the configuration shown in FIG. 1, a recess 1b is also formed in the center of the upper surface of the case substrate 1, and a metal plate 9 is bonded thereto as a heat sink. The inner surface of the metal plate 9 is exposed to the recess 1a provided on the lower surface of the case substrate 1, and the semiconductor element 2 is mounted on the exposed inner surface of the metal plate 9. Further, the peripheral portion 7a of the cap 7 is extended to the outside, and this is bent by approximately 90 degrees so as to stand between the external lead pins 3 at a required height. In this configuration, the metal plate 9 can reduce the thermal resistance of the semiconductor element 2 and enhance the heat dissipation. Further, by erected the cap peripheral portion 7a, it can be used as a stopper in the height direction when the package is mounted on a mounting board or the like, and the lower surface of the cap 7 and the wiring circuit of the mounting board are short-circuited. It is possible to prevent it in advance.

FIG. 5 shows another embodiment of the present invention.
(A) is a bottom view and (b) is a sectional view taken along the line C-C. In this embodiment, the outer shape and dimensions of the cap 7A are set to the case substrate 1
It has the same shape and the same size as. A through hole 75 having a diameter larger than that of the external lead pin 3 is formed at a portion not connected to the external lead pin 3, and no metal plating is formed in the through hole 75 so that the external lead pin 3 does not come into contact with the external lead pin 3. . In addition, the through-hole 7 having a small diameter is plated with metal only at the portion connected to the external lead pin 3.
b is formed. According to this configuration, the circuit pattern 74, that is, the chip capacitor 8 can be electrically connected only to an arbitrary external lead pin among all the external lead pins 3 implanted in the case substrate 1, and thus the circuit design can be freely performed. It is possible to increase the degree.

Here, in each of the above-described embodiments, an example in which the chip capacitor is installed in the package is shown, but it is also possible to install a chip resistor and other chip type electronic parts. In this case, the active component is not limited to the passive component, and it is possible to incorporate the active component. Further, in the above embodiment, the cap having the metal core structure is used,
It is also possible to form it with resin or another material.

[0018]

As described above, according to the present invention, the circuit pattern is formed on the inner surface of the cap, the chip component is mounted on the circuit pattern, and the circuit pattern is attached to the case substrate when the cap is attached to the case substrate. Since it is configured to be electrically connected to the external lead pin provided, it is not necessary to electrically connect the chip component to the cap, and free circuit connection of the chip component is possible, while the cap does not necessarily have to be grounded. The effect is that the degree of freedom in circuit design is improved. Also, when a pad for a chip component is formed on a part of the circuit pattern provided on the inner surface of the cap, the other part of the circuit pattern is connected to a through hole provided on the cap, and the cap is attached to the case substrate. Since the through hole is inserted into the external lead pin and electrically connected thereto, it is not necessary to electrically connect the chip component between the cap and the case substrate. Therefore, generation of thermal stress to the chip component can be prevented, damage to the chip component can be prevented, and there is no need to expose the wiring pattern for connecting the chip component on the case substrate. It is also possible to apply to a semiconductor device in which the pattern is sealed with resin.

[Brief description of drawings]

FIG. 1 shows an embodiment of the present invention, (a) is a bottom view,
(B) is the AA sectional view taken on the line.

2 shows a cap used in the semiconductor device of FIG.
(A) is a top view and (b) is the BB line expanded sectional view.

FIG. 3 is a flowchart showing a schematic process of a method for manufacturing the semiconductor device of FIG.

FIG. 4 is a sectional view of another embodiment of the present invention.

5A and 5B show still another embodiment of the present invention, in which FIG. 5A is a bottom view and FIG. 5B is a sectional view taken along the line CC.

FIG. 6 is a cross-sectional view of an example of a semiconductor device incorporating a conventional chip capacitor.

[Explanation of symbols]

1 Case Board 2 Semiconductor Element 3 External Lead Pin 4 Wiring Pattern 6 Resin 7, 7A Cap 74 Circuit Pattern, 74a Pad, 74b Through Hole 8 Chip Capacitor 9 Metal Plate

Claims (4)

[Claims] 1. A semiconductor element is mounted on a case substrate and electrically connected to external lead pins implanted in the case substrate,
Further, in a semiconductor device configured to seal the semiconductor element with a cap, a circuit pattern is formed on an inner surface of the cap, and a chip component electrically connected to the circuit pattern is mounted, and the cap is attached to the case substrate. A semiconductor device, wherein the circuit pattern is configured to electrically connect to the external lead pin when attached. 2. A desired circuit pattern is formed on the inner surface of the cap, a pad for a chip component is formed on a part of this circuit pattern, and the other part of the circuit pattern is connected to a through hole provided on the cap, The semiconductor device according to claim 1, wherein the through hole is inserted into the external lead pin and electrically connected to the external lead pin when the cap is attached to the case substrate. 3. The semiconductor device according to claim 1, wherein the chip component is a chip capacitor. 4. The case substrate is provided with a wiring pattern, the semiconductor element and an external lead pin are electrically connected through the wiring pattern, and the semiconductor element and the wiring pattern are sealed with a resin. Any semiconductor device.