JPH0810402A - Game apparatus - Google Patents

Abstract

PURPOSE:To facilitate the mounting of circuit elements composing a control circuit on a substrate while preventing abusing in a processing of generating random number. CONSTITUTION:An integrated circuit 60 is an IC in which an ROM 62 having a control program of a pachinko game device 1 stored to be executed with a CPU 40 and a random number generation circuit 64 to generate a random number of 16 bit according to a control signal from the CPU 40 are sealed into one package. The ROM 62 and the random number generation circuit 64 are connected to the CPU 40 with various buses branched within the integrated circuit 60 and the CPU 40 can be handled in the same way just as the a ROM 62 and the random number generation circuit 64 are sealed into separate packages. As a result, the wiring of a substrate can be made handy as compared with the case where the a ROM 62 and the random number generation circuit 64 are packaged separately thereby enabling the miniaturization of a controller 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a game machine, more specifically, a game machine provided with a control circuit for executing a predetermined process using a random number based on a game state and changing the advantage of the game state according to the result of the process. Regarding the device.

[0002]

2. Description of the Related Art Conventionally, various types of game devices such as a pachinko game device, an arrange ball game device, a slot machine or a card game machine have been known, and by changing the advantage of the game state, It is designed to enhance playability. Such a gaming device that changes the advantage of the gaming state by using a random number will be described below by taking a pachinko gaming device as an example.

In the pachinko game machine, it has been proposed that when a pachinko ball is won in a specific winning opening, a big hit occurs with a predetermined probability. When a pachinko ball enters the specific winning opening, a random number is generated based on the random number table stored in the non-volatile storage element, and a predetermined process is performed using this random number, and when specific conditions are met. It is called a big hit, and a game state advantageous to the player is revealed (for example, JP-A-2-98381). In this pachinko gaming apparatus, a random number table in which two different digits are randomly arranged is stored in a nonvolatile storage element in the control circuit, and a two-digit numerical value read from the random number table in sequence at predetermined time intervals. The 3-digit random number is generated by interposing the 1-digit numerical value between the 2-digit numerical value and the separately prepared 1-digit numerical value. As the one-digit numerical value used to generate the random number, the first digit of the number of times that the random number table is cycled and read back repeatedly is used.

When a pachinko ball is won in a specific winning opening, the pachinko gaming machine sequentially changes the numerical value of a three-digit numerical display arranged in the center of the playing surface, and after a predetermined time has passed or when the user makes a numerical value. Whether or not it is a big hit is determined based on the random number generated when the switch for stopping the change of the display is pressed. And when you hit the jackpot,
It executes jackpot processing such as driving the members on the game board so that the pachinko balls can easily win.

[0005]

However, in a device that stores a random number table in a non-volatile storage element in a control circuit and uses this random number table to generate random numbers, the random numbers are generated by software. There has been a problem that the manipulation of the winning probability by adjusting the random numbers becomes easy and fraud is likely to occur. For example, falsification of the random number table in which the random number table stored in the non-volatile memory element is rewritten to a random number table having a desired hit probability, and in addition to the random number table stored in the non-volatile memory element, a random number table of the desired hit probability is prepared. Then, the random number table is replaced and a fraud such as a replacement in which a biased random number is generated is likely to occur.

In order to solve this problem, it is conceivable to newly provide an element (random number generating element) for generating a random number of 8 bits, 16 bits or more for a predetermined control signal, but in this case, The wiring becomes complicated due to the necessity of connection with the CPU, and it becomes difficult to assemble and handle the board.

The gaming machine of the present invention has the following constitution for the purpose of solving these problems, preventing fraud in the random number generation process, and facilitating the assembling and handling on the board.

[0008]

A gaming machine of the present invention is provided with a control circuit for executing a predetermined process using a random number based on a game state and changing the advantage of the game state according to the result of the process. In a gaming device in which the control circuit is configured as an arithmetic logic operation circuit having a CPU, the control circuit generates at least a part of the circuits forming the arithmetic logic operation circuit and a random number used for the predetermined processing. The gist of the present invention is to provide an integrated circuit in which a random number generation circuit and a single package are enclosed.

[0009]

The gaming machine of the present invention configured as described above,
The random number generation circuit generates a random number used for predetermined processing based on the game state. The random number generation circuit is enclosed in one package together with at least a part of the circuits forming the arithmetic logic operation circuit to form an integrated circuit. As a result, it is possible to prevent fraud in the random number generation process.
Further, the wiring of the substrate on which the integrated circuit is mounted is simplified, and the control circuit can be downsized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to further clarify the structure and operation of the present invention described above, a pachinko gaming machine 1 as a preferred embodiment of the present invention will be described below. FIG. 1 is a front view showing the outer appearance of the pachinko gaming apparatus 1.

As shown in the figure, a metal frame 3 is provided around the opening of a frame 2 of the pachinko gaming machine 1 and a glass door frame 4 and a front plate 5 are provided in the metal frame 3. It is openable and closable. Behind the glass door frame 4, a game board 6 detachably attached to a game board fixing frame (not shown) fixed to the back surface of the front frame 2 is arranged. On the front surface of the game board 6, a guide rail 8 for guiding a pachinko ball is planted in a substantially circular shape, and a game area 9 is formed in an area surrounded by the guide rail 8.

A variable winning a prize device 10 is provided substantially in the center of the game area 9. The variable winning device 10 has a pair of opening and closing blades 11a and 11b, and these opening and closing blades 11a and 11b are kept under a certain condition for a certain period (for example, 30
The jackpot operation is performed in which a large number of winning balls are generated in a short time by opening for a second or ten winning balls and repeating such an opened state a plurality of times (for example, 16 times). In addition, a jackpot lamp 1a is provided on the back surface of the variable winning device 10, and the lamp 1a is operated during the jackpot operation.
By blinking a, it is visually displayed to the player that the jackpot operation which is different from the normal game state is being performed.

A variable display 12 made up of a plurality of digital displays is formed below the variable winning device 10, and its display mode is a pachinko ball at start winning holes 13a to 13c provided below the game area 9. Changes randomly by winning, and presses the stop switch 14 provided on the front frame 2 or for a fixed time (for example, 5 seconds)
Stop when the time has passed. Then, when the display mode of the variable display device 12 at the time of the stop is a predetermined display mode (for example, the same three-digit number), the variable winning device 10 executes the jackpot operation. .

Further, in the game area 9, general winning openings 15a to 15d are provided in addition to the variable winning apparatus 10 and the starting winning openings 13a to 13c, and any winning apparatus described above or any winning opening. Also, an out port 16 is formed through which a pachinko ball that has not won a prize is guided.

On the surface of the front plate 5, prize balls (pachinko balls) paid out due to the generation of prize balls are preferentially stored,
Moreover, the upper plate 18 for guiding the pachinko balls to the firing position is attached. The front frame 2 has two lamps 1b,
1c is embedded, and a state in which a player has started playing a game on the pachinko gaming apparatus 1 or a gaming state in which an illegal act has been performed is explicitly displayed.

In addition to this, below the front frame 2, a firing strength adjusting handle 20 that is operated by the player is fixed in a protruding manner. The firing strength adjusting handle 20 is rotatably provided with an adjusting lever X for adjusting the elastic force of a pachinko ball. Below the front frame 2 and to the side of the firing strength adjusting handle 20, a lower plate 23 for storing a prize ball that is further paid out when the upper plate 18 is full is attached.

FIG. 2 is a block diagram illustrating the outline of the electrical configuration of the pachinko gaming machine 1. As shown in the figure, the pachinko game machine 1 is mainly configured by a control device 30 electrically. The control device 30 has a CPU 4
RAM that temporarily stores 0 and data required for control
42 and an input / output interface (hereinafter referred to as “I / O”) that controls input / output of various electronic components provided in the pachinko game machine 1.
Abbreviated. ) 44 and a clock generation circuit 46 for outputting a predetermined clock signal to the integrated circuit 60 and the CPU 40.

The CPU 40 is an "Z80" 8-bit microcomputer, and is connected to the RAM 42, I / O 44 and the integrated circuit 60 by the control bus CB, address bus AB and data bus DB. R
The AM 42 is a storage element that temporarily stores necessary data when the CPU 40 executes a control program stored in a ROM 62 described later.

The I / O 44 is a circuit for matching the control device 30 and various electric components provided in the pachinko gaming machine 1. Therefore, the I / O 44 is composed of the open / close blades 11a, 1
Waveforms connected to a solenoid 11 for driving 1b, a variable display 12, a driver 50 connected to the jackpot lamp 1a, etc., a winning switch 13 for detecting a winning of a pachinko ball into the starting winning openings 13a to 13c, and a stop switch 14. It is connected to the shaping circuit 52 and the like.

The integrated circuit 60 is an IC in which a ROM 62 and a random number generation circuit 64 are enclosed in one package. R
The OM 62 and the random number generation circuit 64 are connected to the CPU 40 by various buses branched inside the integrated circuit 60. The ROM 62 and the random number generation circuit 64 have different allocations on the memory map. Therefore, the integrated circuit 60 is
The ROM 62 and the random number generation circuit 64 are enclosed in separate packages and are in the same state as when they are connected by various buses.
As a result, electrically, the CPU 40 can handle the ROM 62 and the random number generation circuit 64 in exactly the same way as when they are enclosed in separate packages. The clock required for the random number generation circuit 64 to generate a random number is C
The basic clock generated by the clock generation circuit 46 for the PU 40 is received via the control bus CB and used.

The ROM 62 is an electrically writable programmable ROM, and non-volatilely stores the control program executed by the CPU 40 and various data necessary for executing the program. In the M1 cycle, the ROM 62 outputs the instruction stored in the address designated by the program counter to the data bus DB according to the control signal from the CPU 40. The CPU 40 reads this instruction and executes its processing. In addition, the ROM 62, in the processing when the pachinko balls are won in the starting winning openings 13a to 13c, the deviation numerical value table in which the deviation numerical values displayed on the variable display 12 are randomly arranged when it is judged as a deviation, and the jackpot. It stores a hit number table in which the numbers of the big hits displayed on the variable display 12 when it is determined that the hit numbers are arranged. An example of the deviation numerical value table is shown in FIG. 3, and an example of the hit numerical value table is shown in FIG. ROM62
Arranged the jackpot numbers (16-bit numbers) in order to determine whether or not it was a jackpot in comparison with the random numbers generated by the random number generation circuit 64 when the pachinko balls were won in the starting winning openings 13a to 13c. A hit determination table (not shown) is stored.

The random number generation circuit 64 is a circuit for outputting a 16-bit random number in response to a control signal from the CPU 40. The CPU 40 divides the 16-bit random number output from the random number generation circuit 64 into upper 8 bits and lower 8 bits, and reads them through the data bus DB.

Next, regarding the operation of the pachinko gaming apparatus 1 thus constructed, a random number generation routine illustrated in FIG. 5, a winning determination routine illustrated in FIG. 6, a winning determination routine illustrated in FIG. 7 and FIG. 8 are illustrated. A description will be given based on the hit processing routine. When the pachinko gaming machine 1 is powered on, first an initialization routine (not shown) is executed to set initial values for variables and flags used in each routine. After that, each routine is executed at every predetermined time set in each routine.

The random number generation routine (FIG. 5) is executed every predetermined time (for example, every 1 msec). When this routine is executed, first, the CPU 40 outputs a control signal requesting the output of a random number to the random number generation circuit 64, and the 16-bit random number output by the random number generation circuit 64 is output twice based on this control signal. The process of reading the data through the data bus DB is executed (step S100). Then, the read random number is written to the predetermined address AD of the RAM 42 (step S110).

Next, the address J of the outlier numerical value table is compared with the set value Jset (step S120), and when the address J is equal to or more than the set value Jset, the value 1 is substituted for the address J (step S130), and the address J is set. Set value Jse
When it is smaller than t, the address J is incremented (step S135). Here, the set value Jset is the value of the final address of the outlier numerical value table. Subsequently, the address K of the hit numerical value table is compared with the set value Kset (step S140), and when the address K is equal to or larger than the set value Kset, the value 1 is substituted into the address K (step S15).
0), if the address K is smaller than the set value Kset, the address K is incremented (step S155),
This routine ends. Here, the set value Kset is the value of the final address of the hit numerical value table.

From the above, the contents of the predetermined address AD are rewritten with the random number generated by the random number generation circuit 64 at every predetermined time (every time when this routine is executed), and the address J of the deviation numerical value table and the address of the hit numerical value table are rewritten. K
Is incremented.

The winning determination routine (FIG. 6) is executed every predetermined time (for example, every 1 msec). When this routine is executed, the CPU 40 causes the start winning openings 13a to 13a.
The state of the winning switch 13 that is turned on when a pachinko ball is won in any of c is read (step S20).
0). Next, the state of the winning switch 13 (on or off)
Is determined (step S210), and when the winning switch 13 is off, this routine is ended. When the winning switch 13 is on, the winning counter C1 is incremented by 1 (step S220), and this routine is finished. Here, the winning award counter C1 is a starting winning award 13a ~
It is to count the number of pachinko balls that have won 13c. The winning counter C1 is set to a value 0 by the initialization routine when the power of the pachinko gaming apparatus 1 is turned on.

According to the above routine, even if a plurality of pachinko balls enter the starting winning openings 13a to 13c in a short time,
Pachinko balls that have won prizes can be counted regardless of the subsequent processing. In the embodiment, the winning counter C1 is incremented each time a pachinko ball wins the starting winning openings 13a to 13c, but an upper limit value (for example, value 4) of the winning counter C1 is set, and when the winning counter C1 is the upper limit value. A configuration without increment is also suitable.

The hit determination routine (FIG. 7) is executed every predetermined time (for example, every 2 msec). When this routine is executed, the value of the hit determination flag F indicating whether or not the jackpot processing is being executed is checked (step S30).
0). The hit determination flag F is set to a value of 0 in the initialization routine (not shown) described above, and is set to a value of 1 when a big hit is made as described later. When the hit determination flag F has a value of 1, that is, when it is a big hit, this routine is ended without doing anything. When the hit determination flag F is 0, the value of the winning counter C1 is checked (step S30
2), when the winning counter C1 has a value of 0, the starting winning opening 13
It is judged that there is no winning of the pachinko balls to a to 13c, and this routine is ended. When the value of the winning counter C1 is 1 or more, it is determined that there is a winning of a pachinko ball to the starting winning holes 13a to 13c, and the following processing is performed.

The CPU 40 checks the value of the timer T1 (step S305), and when the value is 1, starts the process of sequentially changing the numerical value of the variable display 12 (step S30).
7) Until the timer T1 becomes equal to or more than the set value T1set or the stop switch 14 is pressed, the process of incrementing the timer T1 (steps S305 to S330) is repeated with the numerical value of the variable display 12 being sequentially changed. Here, the set value T1set is the stop switch 1
Even when 4 is not pressed, the timing to shift to the process after being pressed (for example, 5 seconds after the timer T1 starts counting) is determined.

When the timer T1 exceeds the set value T1set or the stop switch 14 is pressed, the CPU 4
0 reads the random number stored in the predetermined address AD of the RAM 42 (step S340), and the read random number is R
It is determined whether or not it is a big hit by comparing it with a numerical value of a hit determination table (not shown) stored in the OM 62 (step S345). The result of the determination is set in a flag or the like. Next, with reference to this flag and the like, when it is determined that the jackpot is a big hit (step S350), the changing speed of the variable display 12 is slowed down, and when stopped, the numerical value stored in the address K of the hit numerical value table is variably displayed. The process displayed on the container 12 is executed (step S360), and the hit determination flag F is set to the value 1 (step S365). On the other hand, if it is determined in step S350 that it is out of position, the changing speed of the variable display 12 is slowed down, and when stopped, a process of displaying the value stored in the address J of the out-of-range value table on the variable display 12 is executed. (Step S36
2). Then, the value 1 is assigned to the timer T1 (step S3
70), the winning counter C1 is decremented (step S375), and this routine is finished.

The hit processing routine (FIG. 8) is executed every predetermined time (for example, every 2 msec). When this routine is executed, the value of the hit determination flag F is checked (step S400), and when the hit determination flag F has a value of 0, it is determined that the big hit process is unnecessary and the routine is ended. When the hit determination flag F has a value of 1, it is determined that a big hit process is necessary, and the following process is executed. First, it is determined whether or not the timer T2 is 1 (step S410),
When the value is 1, the open / close wing piece 11a is opened by the solenoid 11.
11b is released (step S415), and when the timer T2 is not the value 1, the process proceeds to the next step S420.

Then, the timer T2 is incremented (step S420), and the timer T2 and the set value T2set are set.
And are compared (step S430). Here, the set value T
2set sets the time (for example, 30 seconds) during which the open / close blades 11a and 11b are released. When the timer T2 is smaller than the set value T2set, it is determined that the release time has not yet elapsed, and the open / close blades 11a, 11
This routine is terminated with b released. When the timer T2 is equal to or greater than the set value T2set, it is determined that the release time has elapsed and the opening / closing blades 11a and 11b are closed (step S440).

Next, the value 1 is assigned to the timer T2 (step S445), and the open / close counter C3 and the value 16 are compared (step S450). The open / close counter C3 counts the number of times the open / close blades 11a and 11b are opened / closed per jackpot. In this embodiment, the opening / closing wing piece 11
The a and 11b are set to open and close 16 times. When the open / close counter C3 is smaller than the value 16, that is, when the open / close blades 11a and 11b have not been opened / closed 16 times, the open / close counter C3 is incremented (step S45).
5) Then, this routine is finished. The open / close counter C3 has the value 1
When it is 6 or more, it is determined that the opening and closing blades 11a and 11b have been opened and closed 16 times, the value 1 is assigned to the opening / closing counter C3 (step S460), and the hit determination flag F is set to the value 0 (step S465). This routine ends.

In the embodiment, in the case of a big hit, the opening / closing blade piece 1
Although the operation of releasing 1a and 11b for a predetermined time (for example, 30 seconds) is repeated 16 times,
The process of repeating the operation of releasing b until the number of 10 pachinko balls wins, a process of repeating V inside the opening / closing blades 11a and 11b.
Various measures can be taken such as providing a winning opening and repeating the operation of releasing the opening / closing blades 11a and 11b for a predetermined time up to 16 times when a pachinko ball wins the V winning opening.

According to the pachinko gaming machine 1 as the embodiment described above, the ROM 62 and the random number generation circuit 64 are enclosed in one package, so that it is possible to prevent tampering such as falsification of random numbers and replacement of the random number generation circuit. it can. In addition, various buses that branch inside the integrated circuit 60
Since the OM 62 and the random number generation circuit 64 are connected, RO
The wiring of the substrate can be simplified and the control device 30 can be downsized as compared with the case where the M62 and the random number generation circuit 64 are packaged separately. further,
Since the random number generated by the random number generation circuit 64 is 16 bits, the jackpot probability can be set in 1/2 ¹⁶ units.

According to the pachinko game machine 1 of the embodiment, the random number generation circuit 64 regularly reads the random numbers regardless of whether or not the pachinko balls are won at the start winning holes 13a to 13c. Even with a circuit that generates a random number, the regularity of the circuit is not perceived by the user. Further, since the address J of the outlier numerical value table and the address K of the hit numerical value table are incremented every predetermined time, the regularity of the numerical values displayed on the variable display 12 can be eliminated.

In the embodiment, the random number generation circuit 64 is configured as a circuit for generating a 16-bit random number, but it may be configured as a circuit for generating a random number of any bit number. This is because the number of bits of the random number is determined by the jackpot probability setting.

In the embodiment, the type of hit is 1 for big hits.
Although the types are set, it is also preferable to provide a plurality of types such as a big hit, a medium hit, and a small hit. In this case, the embodiment may be modified as follows. For example, in the ROM 62,
The hit determination table for determining the hit by comparing with the generated random number is stored for each hit type, and the set value T2set of the hit processing routine is set for each hit type. By doing this, depending on the type of hit, the wing blade 1
The release time for each release of 1a and 11b can be changed. Alternatively, step S45 of the hit processing routine
When the value is 0, the numerical value to be compared with the open / close counter C3 is changed for each winning type. This makes it possible to change the number of times the open / close blades 11a and 11b are released depending on the type of hit.

In this embodiment, the clock required by the random number generation circuit 64 for generating the random number is the clock generated by the clock generation circuit 64 for the CPU 40.
As shown in FIG.
5, the random number generation circuit 64 can be operated by a clock different from the clock of the CPU 40. In this case, the operation of the CPU 40 and the operation of the random number generation circuit 64 are completely asynchronous even when viewed at the level of the system clock, so that the operation of the CPU 40 may be performed under some condition (for example, the blinking timing of the variable display 12). It is also impossible to detect and read the timing of random number generation. Therefore, the operation timing of the CPU 40 can be analyzed to eliminate any attempt to artificially intervene in the generation of random numbers. The clock generation circuit 65 may be externally attached to the integrated circuit 60.
Further, the clock generating circuit 65 may be configured such that an oscillating crystal, a tuning fork oscillator, an oscillating circuit such as CR or LC, or the like is externally attached. In this case, the clock and the tuning fork vibrator are highly dependent on the environment (for example, temperature), and the resistors and capacitors forming the CR and LC oscillation circuits are highly dependent on the temperature, and the clock generation circuit It is also preferable to deliberately change the frequency of the clock generated by 65.

Next, a pachinko game machine 1A as a second embodiment of the present invention will be described with reference to FIG. FIG. 10 is a block diagram illustrating a part of the electrical configuration of the pachinko gaming machine 1A of the second embodiment. As shown in the figure, the pachinko gaming machine 1A of the second embodiment is an integrated circuit 7
It has the same structure as the pachinko gaming machine 1 of the first embodiment except for the structure relating to 0 and the ROM 62A. Therefore, of the configurations of the pachinko gaming machine 1A, the same configurations as those of the pachinko gaming machine 1 of the first embodiment are designated by the same reference numerals and the description thereof will be omitted.

The ROM 62A of the pachinko gaming machine 1A is
ROM of the pachinko gaming machine 1 of the first embodiment except that it is not enclosed in the random number generation circuit 64 and one package.
It is the same as 62.

The integrated circuit 70 is an IC in which the random number generation circuit 64A and the security CPU 72 are enclosed in one package. Random number generation circuit 64A and security CPU
72 is connected to the CPU 40 by various buses branched inside the integrated circuit 70. Therefore, the integrated circuit 70
Is in the same state as that in which the random number generation circuit 64A and the security CPU 72 are enclosed in separate packages and connected by various buses. As a result, the CPU 40 can handle the random number generation circuit 64A and the security CPU 72 in exactly the same way as when they are enclosed in separate packages.

The random number generation circuit 64A has the same configuration as the random number generation circuit 64 of the first embodiment, and is a circuit which outputs a 16-bit random number in response to a control signal from the CPU 40.

The security CPU 72 is an arithmetic logic operation circuit for checking whether or not the ROM 62A is a genuine product by a check program stored in advance in a ROM (not shown) provided therein. Security CPU
72 includes output ports P1 \ and P2 \ for outputting signals P1 \ and P2 \, a signal P3 \ and input ports P3 \ and INT \ for inputting interrupt signals. Here, "\" indicates that the signal is "low active (negative logic)".

Output port P1 of security CPU 72
\ Is connected to the port RESET \ of the CPU 40 via the OR circuit 76 together with a signal line from the outside of the control device 30A, and the security CPU 72 sets the signal P1 \ to a low level (hereinafter referred to as "L"). By CPU
40 is reset. Output port P2 \ is CP
It is connected to the port BUSRQ \ of U40, and the security CPU 72 requests the CPU 40 to occupy various buses by setting the signal P2 \ to "L". The input port P3 \ is connected to the port BUSAK \ of the CPU 40. Therefore, the security CPU 72
Knows that the CPU 40 can occupy various buses by receiving a low level signal BUSAK \ output in response to a request for occupying various buses. Each port of the security CPU 72 connected to various buses is normally in a high-impedance state and outputs "L" from the port P2 \, resulting in the port P3.
Connection with various buses is enabled only when "L" is input from \.

Input port IN of security CPU 72
T \ is connected to the interrupt signal generation circuit 74. The interrupt signal generation circuit 74 is a logic circuit that randomly generates an interrupt signal. The security CPU 72 receives the interrupt signal generated by the interrupt signal generation circuit 74 from the input port INT.
When input to \, the interrupt process is started according to a predetermined sequence, and the check program described later is executed.

The CPU 40 of the pachinko gaming machine 1A configured as described above executes the same routine as an unillustrated initialization routine executed by the CPU 40 of the pachinko gaming machine 1 of the first embodiment immediately after the power is turned on, After that, similarly, a random number generation routine (FIG. 5), a winning determination routine (FIG. 6), a winning determination routine (FIG. 7) and a winning processing routine (FIG. 5) that are executed at predetermined intervals by the CPU 40 of the pachinko gaming machine 1 of the first embodiment. The same routine as 8) is executed. When the CPU 40 of the pachinko gaming machine 1A is executing such a routine, the security CPU 72
The check program shown in the flowchart of FIG. 11 is being executed. The check program shown in FIG. 11 is a program burned in the internal ROM of the security CPU 72, and the signal from the interrupt signal generation circuit 74 is IN.
Every time it is input to T \, the processing based on this check program is started and repeatedly executed while the power is supplied.

Security CPU 72 port INT \
When a low-level interrupt signal is input to the security CPU 72, the security CPU 72 first sets the signal P2 \ to "L" (step S500). Low level signal P2 \ is port BUS
The CPU 40 input to RQ \ places the connection with various buses in a high impedance state after the end of the currently executed machine cycle, and interrupts the control of the pachinko machine. As will be described later, the interruption of the control of the pachinko machine is only for a few machine cycles of the security CPU 72, so that the game is apparently continued without any trouble.

Next, the security CPU 72 waits until a low level signal is input to the input port P3 \ (step S510), and validates the connection with various buses (step S520). The CPU 40 sends a signal BUSAK when the connection with various buses becomes a high impedance state.
Since \ is set to "L", if the security CPU 72 receives this signal and validates the connection with various buses,
40 and the security CPU 72 are not connected to various buses at the same time.

The identification code is read from the predetermined address of the ROM 62A by using the various buses in which the connection with the security CPU 72 is thus valid (step S53).
0). When the identification code is read, the security CPU 7
2 is connected to various buses in a high impedance state (step S540), and the signal P2 \ is set to "H" (step S550). By setting the signal P2 \ to "H", the connection between the CPU 40 and various buses is validated, and the CPU
Control of the pachinko machine by 40 is restarted. Therefore, the interruption of the control of the pachinko machine by the CPU 40 is R
Since it is only a time to access the OM62A, which is extremely short, there is no influence on the pachinko machine user due to the interruption of the control.

Next, it is judged whether or not the identification code read from the ROM 62A is a predetermined correct value (step S560), and if it is correct, this routine is ended. If it is determined that the identification code is incorrect, the signal P1 \ from the output port is set to "L" (step S57).
0), the CPU 40 is reset.

Here, in determining whether the ROM 62A is a proper one, the security CPU 72 determines a value that correlates with the program code written in the ROM 62A.
In addition to the method of writing the data in the internal ROM of the ROM 62 and discriminating it, the predetermined calculation result for the data stored in the plurality of addresses of the ROM 62A is described in advance in the specific address of the ROM 62A, and the security CPU 72 causes the ROM 6
A method of reading the data of each address of 2A, performing a predetermined calculation, and comparing the result with the value of the specific address to determine the internal ROM and ROM 62 of the security CPU 72.
It is assumed that a predetermined identification code is written in both of A and A, and a method for discriminating the coincidence of the identification code, the same program code described in the ROM 62A is previously recorded in the internal ROM of the security CPU 72, and RO
A method of determining by comparing the contents of M62A with the contents of internal ROM, a method of calculating the checksum of the program code written in ROM62A, and determining whether this is the value previously written in internal ROM, multiple ROM62A A variety of methods are used, such as a method of reading the value of the address of the above, performing a predetermined calculation, and comparing the result of the calculation with a value described in advance at a predetermined address of the ROM 62A or a predetermined address of the internal ROM of the security CPU 72. be able to.

Further, in the second embodiment, the CPU 40 is configured to be reset when it is determined that the identification code is not correct, but any means for prohibiting the normal operation of the CPU 40 may be used. May be configured to stop its own operation. Further, since it is sufficient to stop the normal operation, various measures such as executing a demo can be considered.

According to the pachinko game machine 1A as the second embodiment described above, since the security CPU 72 and the random number generation circuit 64A are enclosed in one package,
It is possible to prevent fraud such as falsification of random numbers and replacement of the random number generation circuit. Further, since the security CPU 72 and the random number generation circuit 64A are connected by various buses branched inside the integrated circuit 70, the security CPU 72
The wiring of the substrate can be simplified and the control device 30A can be downsized as compared with the case where the and the random number generation circuit 64A are packaged separately.

The check program executed by the security CPU 72 immediately after the power is turned on is used for RO
It is repeatedly determined whether or not the M62A is a genuine product, and when it is determined to be an unauthorized product, the CPU 40 is reset and the operation is prohibited. Therefore, any processing based on an illegal control program written in the illegal ROM is performed. There is no. Further, since the timing at which the security CPU 72 executes the check program is determined by an interrupt signal that is randomly generated, the security CPU 72 causes the ROM 62 to
It is possible to prevent the reading to A from being detected in advance. Therefore, it is possible to prevent illegal control by the ROM. Further, the security CPU 72 is the CPU 4
Since the ROM 62A is checked using various buses for a time that does not hinder the control of the pachinko machine by 0, there is no hindrance to the game. Moreover, CP
The control program of the pachinko gaming machine 1 by U40 is
There is no need to change anything from the conventional one. ROM62A
Since the check is always performed during the operation, it is possible to detect an illegal operation such that the ROM 62A operates from the power-on to a predetermined time and the illegal ROM is switched to after the predetermined time elapses.

In the embodiment, the security CPU 72
Although it is checked whether the ROM 62A is a genuine product, a configuration in which the random number generation circuit 64A is checked whether it is a genuine product is also suitable. Particularly, in a mode in which the security CPU and the random number generation circuit, which will be described later, are enclosed in different packages, the configuration for checking the random number generation circuit can be said to be an extremely preferable configuration from the viewpoint of preventing fraud.

Further, as shown in FIG. 12, the clock generation circuit 65A for the random number generation circuit 64A is provided separately from the clock generation circuit 46 for the CPU 40, and the random number generation circuit 64 is provided.
It is also preferable that the operation timing of A is completely asynchronous with the operation timing of the CPU 40 as in the first embodiment. The clock generation circuit 65A may be built in the integrated circuit 70 or may be provided separately from the integrated circuit 70. Further, an external crystal, tuning fork vibrator, or oscillation circuit such as CR or LC may be externally attached. In this case, the clock and the tuning fork vibrator are highly dependent on the environment (for example, temperature), and the resistors and capacitors forming the CR and LC oscillation circuits are highly dependent on the temperature, and the clock generation circuit 6
It is also preferable to intentionally change the frequency of the clock generated by 5A.

Next, a pachinko gaming machine 1B as a third embodiment of the present invention will be described with reference to FIG. FIG. 13 is a block diagram illustrating a part of the electrical configuration of the pachinko gaming machine 1B of the third embodiment. Of the pachinko gaming machine 1B of the third embodiment, the same configurations as the pachinko gaming machine 1 of the first embodiment or the same configurations as the pachinko gaming machine 1A of the second embodiment are designated by the same reference numerals and their description is omitted. Is omitted. Pachinko gaming machine 1B of the third embodiment
Is an integrated circuit 32, a ROM 62, a driver 50,
A control device 30B including a waveform shaping circuit 52 is provided. The integrated circuit 32 includes a CPU 40B and a RAM 42.
Is an IC in which the I / O 44, the clock generation circuit 46, the interrupt signal generation circuit 74, and the random number generation circuit 64 are enclosed in one package.

The CPU 40B has an internal ROM, and the internal ROM stores a check program for determining whether the ROM 62 is a genuine product. CPU4
0B executes the check program stored in the internal ROM prior to the game program after executing the initialization routine (not shown) described in the first embodiment when the power is turned on. When the ROM 62 is a genuine product, the game program including the routines described in the first embodiment is executed to enable the game. When the ROM 62 is not a genuine product, the subsequent processes are stopped and stopped.

When the ROM 62 is determined to be a genuine product and the game is started, the control device 30B executes a random number generation routine (FIG. 5) and a winning determination routine (FIG. 5) executed by the control device 30 of the first embodiment. 6), hit determination routine (Fig. 7)
The process using the random number generation circuit 64 is executed by the same routine as.

According to the pachinko game machine 1B of the third embodiment described above, most of the control circuits except the ROM 62 and the random number generation circuit 64 are enclosed in one package, so that falsification of random numbers and replacement of the random number generation circuit are performed. Such fraud can be prevented. Moreover, since the number of chips mounted on the board is reduced, the wiring of the board can be simplified and the control device 30B can be downsized.

Also, the pachinko game machine 1B of the third embodiment.
In the same manner as in the first and second embodiments, the random number generation circuit 64
A clock generation circuit 65B for generating a clock for
It is also preferable to provide it separately from the clock generation circuit 46 for the PU 40B. FIG. 14 shows a configuration in which an external crystal 48 is provided in the clock generation circuit 46 for the CPU 40B, and an external CR oscillation circuit 68 is provided in the clock generation circuit 64B for the random number generation circuit 64. Also in this case, the random number generation timing of the random number generation circuit 64 is completely asynchronous with the operation of the CPU 40B, and
Since the clock generation circuit 46 for the CPU 40B uses a crystal, its oscillation frequency is relatively independent of temperature, and the clock generation circuit 65B for the random number generation circuit 64 is C
Since the R oscillating circuit 68 is used, the operating clock changes due to its temperature dependency and the like. Therefore, the CPU 40B
By analyzing the operation timing of, it is possible to eliminate any attempt to artificially intervene in the generation of random numbers.

<Development of the Concept of the Invention> In the first embodiment, the pachinko game machine is taken as an example, and the random number generation circuit 64 and the ROM are used.
62 and 62 are enclosed in one package, but as a preferred embodiment of the present invention, circuit elements such as CPU, ROM, RAM, and I / O in various game devices such as arrange ball game devices, slot machines, card game machines, etc. There is a package in which at least one of the above and a random number generation circuit are enclosed in one package. That is, CPU, ROM, RA
A mode in which one of M and I / O and a random number generation circuit are enclosed in one package (4 modes), CPU,
A mode in which two of ROM, RAM and I / O and a random number generation circuit are enclosed in one package (6 modes), C
A mode in which three of PU, ROM, RAM, and I / O and a random number generation circuit are enclosed in one package (four modes), and CPU, ROM, RAM, I / O, and random number generation circuit are all included in one package. It is a mode (1 mode) of encapsulating.

In the second embodiment, the pachinko game machine is taken as an example, and the random number generation circuit 64A and the security CPU are used.
72 and 72 are enclosed in one package, but as a preferred embodiment of the present invention, CPU, ROM, RAM, I / O, security CPU, etc. in various game devices such as arrangement ball game devices, slot machines, card game machines, etc. There is one in which at least one of the circuit elements and the random number generation circuit are enclosed in one package. That is,
CPU, ROM, RAM, I / O and security C
A mode in which any one of PUs and a random number generation circuit is enclosed in one package (5 modes), CPU, ROM, R
A mode in which two of AM, I / O, and security CPU and a random number generation circuit are enclosed in one package (1
0 mode), a mode in which three of the CPU, ROM, RAM, I / O, and the security CPU and the random number generation circuit are enclosed in one package (10 mode), CPU, RO
Mode (5 modes) in which four of M, RAM, I / O and security CPU and random number generation circuit are enclosed in one package, CPU, ROM, RAM, I / O, security CPU and random number generation circuit Is a mode (1 mode) in which is enclosed in one package.

In the third embodiment, a pachinko game machine is taken as an example, and most of the control circuits except the ROM 62 and the random number generation circuit 64 are enclosed in one package, but the preferred embodiment of the present invention is the first embodiment. Similar to the aspect developed in the example, C in various game devices such as an arrangement ball game device, a slot machine or a card game machine.
It is possible to enclose at least one of circuit elements such as PU, ROM, RAM and I / O and a random number generation circuit in one package.

As described as a modification of each of the above-described embodiments, the random number generation circuit is enclosed in the same package as at least a part of the circuits constituting the arithmetic logic operation circuit, and its clock is used for arithmetic logic operation. If it is generated by a clock generation circuit different from the clock of the circuit to be performed, the timing of random number generation and the control of the game device can be completely separated, and the timing of random number generation can be artificially intervened from the outside, It is possible to eliminate any attempt to intervene in the game by knowing the timing of random number generation.

The embodiments of the present invention have been described above.
The present invention is not limited to these embodiments, and, for example, an aspect in which a circuit other than the above and a random number generating circuit which constitute a control circuit incorporated in a game device are enclosed in one package, and the like. Needless to say, the present invention can be implemented in various modes without departing from the above. Further, the random number generation circuit may be configured by a wired logic or may be calculated by the CPU (software-like one). When the random number generation circuit is calculated by the CPU, the CPU may of course have a ROM or / and a security function for the random number generation circuit.

[0069]

As described above, in the game device of the present invention, at least a part of the circuits forming the arithmetic logic operation circuit and the random number generating circuit for generating the random number used for the predetermined processing are contained in one package. Since the enclosed integrated circuit is used, it is possible to prevent fraudulent adjustment of the random number such as falsification of the random number table or replacement of the random number table. Moreover, the wiring of the substrate can be simplified as compared with the case where the wiring is enclosed in a separate package. As a result,
It is possible to easily mount the circuit element forming the control circuit on the substrate, and it is possible to reduce the size of the control circuit.

[Brief description of drawings]

FIG. 1 is a pachinko gaming device 1 as one embodiment of the present invention.
It is a front view showing the appearance of.

FIG. 2 is a block diagram illustrating an electrical configuration of a pachinko gaming machine 1 as an embodiment.

FIG. 3 is an explanatory diagram showing an example of a deviation numerical value table stored in a ROM 62.

FIG. 4 is an explanatory diagram showing an example of a hit number table stored in a ROM 62.

5 is a flowchart showing a random number generation routine executed by the CPU 40. FIG.

FIG. 6 is a flowchart showing a winning determination routine executed by the CPU 40.

FIG. 7 is a flowchart showing a hit determination routine executed by the CPU 40.

FIG. 8 is a flowchart showing a hit processing routine executed by the CPU 40.

FIG. 9 is a schematic configuration diagram showing a modified example of the pachinko gaming machine 1 as the first embodiment.

FIG. 10 is a block diagram illustrating a part of an electrical configuration of a pachinko gaming machine 1A as a second embodiment.

FIG. 11 is a flowchart illustrating a check program executed by the CPU 40 of the second embodiment.

FIG. 12 is a schematic configuration diagram showing a modified example of the second embodiment.

FIG. 13 is a block diagram illustrating a part of the electrical configuration of a pachinko gaming machine 1B as a third embodiment.

FIG. 14 is a schematic configuration diagram showing a modified example of the third embodiment.

[Explanation of symbols]

 1, 1A, 1B ... Pachinko gaming device 1a ... Big hit lamp 1b, 1c ... Lamp 2 ... Front frame 3 ... Metal frame 4 ... Glass door frame 5 ... Front plate 6 ... Game board 8 ... Guide rail 9 ... Gaming area 10 ... Fluctuation Prize winning device 11 ... Solenoids 11a, 11b ... Open / close wing piece 12 ... Variable indicator 13 ... Prize winning switch 13a-13c ... Start winning hole 14 ... Stop switch 15a-15d ... General winning hole 16 ... Out mouth 18 ... Upper plate 20 ... Launch Strength adjusting handle 23 ... Lower plate 30, 30A, 30B ... Control device 32 ... Integrated circuit 40, 40B ... CPU 42 ... RAM 44 ... I / O 46 ... Clock generation circuit 50 ... Driver 52 ... Waveform shaping circuit 60 ... Integrated circuit 62 , 62A ... ROM 64, 64A ... Random number generation circuit 65, 65A, 65B ... Clock generation circuit 70 ... Integrated circuit 72 ... Security I CPU 74 ... interrupt signal generating circuit 76 ... OR circuit AB ... address bus CB ... control bus DB ... data bus X ... adjusting lever

Claims (1)

[Claims] 1. An arithmetic logic operation having a control circuit for executing a predetermined process using a random number based on a game state and changing the advantage of the game state according to the processing result, the control circuit having a CPU. In the gaming device configured as a circuit, the control circuit encloses at least a part of the circuit that constitutes the arithmetic logic operation circuit and a random number generation circuit that generates a random number used for the predetermined processing in one package. A game device with an integrated circuit.