JPH0747901Y2 - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPH0747901Y2 JPH0747901Y2 JP1987146999U JP14699987U JPH0747901Y2 JP H0747901 Y2 JPH0747901 Y2 JP H0747901Y2 JP 1987146999 U JP1987146999 U JP 1987146999U JP 14699987 U JP14699987 U JP 14699987U JP H0747901 Y2 JPH0747901 Y2 JP H0747901Y2
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- substrate
- component
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案は印刷配線板に関し、特に電子部品を表面実装す
るパッド部の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a printed wiring board, and more particularly to a structure of a pad portion for surface mounting an electronic component.
従来、印刷配線板上に表面実装用電子部品を実装する場
合、第２図に示すように、基板基材２の部品実装位置に
平坦な銅箔パッド部1aを配線し、このパッド部1aに部品
のリード部3aとの接続を行っていた。Conventionally, when mounting a surface mounting electronic component on a printed wiring board, as shown in FIG. 2, a flat copper foil pad portion 1a is wired at the component mounting position on the substrate 2, and the pad portion 1a is mounted on the pad portion 1a. The connection was made with the lead portion 3a of the component.
上述した従来の印刷配線板は、表面実装部品用に平坦な
パッド部1aを用いているので、次のような欠点があっ
た。The conventional printed wiring board described above has the following drawbacks because it uses the flat pad portion 1a for the surface mount component.
（１） 部品実装時に、表面実装部品の正確な位置決め
が困難である。(1) It is difficult to position the surface mount component accurately when mounting the component.
（２） 半田付け時に、部品実装位置にずれが生ずる。(2) The component mounting position is displaced during soldering.
また、この表面実装部品のうちチップ部品は、その大き
さが小さいので、平坦なパッド部1aに性格に位置決めす
るのが困難であった。Further, of the surface-mounted components, the chip component is small in size, so that it is difficult to accurately position it on the flat pad portion 1a.
本考案の目的は、このような従来の欠点を解消し、チッ
プ部品の正確な位置決めができると共に半田付けの位置
ずれをなくした印刷配線板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a printed wiring board which eliminates the above-mentioned conventional drawbacks, enables accurate positioning of chip components, and eliminates misalignment of soldering.
本考案の構成は、基板と、基板上に設けれた複数の回路
パターンと、これら回路パターン上または基板上に形成
された半田レジスト層とを有する印刷配線板において、
前記基板上にチップ部品のリード部が挿入できる幅で断
面がＶ字形の溝を設け、このＶ字形の溝にチップ部品用
パッド部を埋め込むように形成して、この埋め込んだ部
分とそれ以外の部分の表面とが同一平面となるように構
成されていることを特徴とする。The configuration of the present invention is a printed wiring board having a substrate, a plurality of circuit patterns provided on the substrate, and a solder resist layer formed on these circuit patterns or on the substrate,
A groove having a V-shaped cross section is formed on the substrate with a width that allows the lead portion of the chip component to be inserted. It is characterized in that the surface of the part is flush with the surface.
次に、本考案について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本考案の一実施例を示す印刷配線板の部分断面
斜視図である。本実施例は、パッド部１の位置における
基板基材２にＶ型の溝部４があり、その上のパッド部１
の銅箔がチップ部品５のリード３が挿入できる幅になっ
ている。FIG. 1 is a partial sectional perspective view of a printed wiring board showing an embodiment of the present invention. In this embodiment, there is a V-shaped groove portion 4 on the substrate 2 at the position of the pad portion 1, and the pad portion 1 above it.
The copper foil has a width that allows the leads 3 of the chip component 5 to be inserted.
本実施例の製造方法として、パネルめっきの前の工程に
おいて基板基材２のパッド部１の箇所にＶカットを施す
工程をいれることにより、図示のようにＶ字形の溝にチ
ップ部品用パッド部が埋め込まれるように形成され、こ
の埋め込んだ部分とそれ以外の部分の表面とが同一平面
となるように構成された断面がＶ字型のパッド部１を形
成することができる。このように形成されたパッド部１
の銅箔上にチップ部品５のリード部３を搭載し接続固定
するようにしている。As a manufacturing method of the present embodiment, by inserting a step of V-cutting the pad portion 1 of the substrate base material 2 in the step before panel plating, the pad portion for chip parts is formed in the V-shaped groove as shown in the figure. Can be formed so that the pad portion 1 having a V-shaped cross section is formed so that the embedded portion and the surface of the other portion are flush with each other. The pad portion 1 formed in this way
The lead part 3 of the chip component 5 is mounted on the copper foil and fixedly connected.
以上説明したように本考案は、チップ部品用パッド部を
基板のＶ字型の凹部に設ける事により、次の効果があ
る。As described above, the present invention has the following effects by providing the pad part for the chip component in the V-shaped recess of the substrate.
（１） チップ部品を実装する場合、パッドの凹部によ
る実装位置が強制的に指定されるので、正確な位置への
部品実装が容易になる。(1) When a chip component is mounted, the mounting position is forcibly designated by the recessed portion of the pad, which facilitates component mounting at an accurate position.
（２） チップ部品を自動実装する場合に、部品の実装
位置誤差を吸収できる。(2) When a chip component is automatically mounted, a mounting position error of the component can be absorbed.
（３） チップ部品を半田付けする場合に、位置のずれ
が生じにくい。(3) When soldering the chip component, the position shift is unlikely to occur.
（４） チップ部品の搭載高さが低くなるだけでなく、
パッド面積が大きくならないので高密度化に適してい
る。(4) Not only is the mounting height of the chip components low,
Suitable for high density because the pad area does not increase.
第１図は本考案の印刷配線板の一実施例を部分断面で示
した斜視図、第２図は従来の印刷配線板の一例の部分断
面斜視図である。 １……Ｖ字パッド部、1a……銅箔のパッド部、２……基
板基材、３……リード部、3a……部品リード（電極）、
４……溝部、５……チップ部品。FIG. 1 is a perspective view showing an embodiment of a printed wiring board of the present invention in a partial cross section, and FIG. 2 is a partial sectional perspective view of an example of a conventional printed wiring board. 1 ... V-shaped pad portion, 1a ... Copper foil pad portion, 2 ... Substrate base material, 3 ... Lead portion, 3a ... Component lead (electrode),
4 ... Groove part, 5 ... Chip part.
Claims (1)
ターンと、これら回路パターン上または基板上に形成さ
れた半田レジスト層とを有する印刷配線板において、前
記基板上にチップ部品のリード部が挿入できる幅で断面
がＶ字形の溝を設け、このＶ字形の溝にチップ部品用パ
ッド部を埋め込むように形成して、この埋め込んだ部分
とそれ以外の部分の表面とが同一平面となるように構成
されていることを特徴とする印刷配線板。1. A printed wiring board having a substrate, a plurality of circuit patterns provided on the substrate, and a solder resist layer formed on the circuit patterns or on the substrate, wherein leads of chip components are provided on the substrate. A groove having a V-shaped cross-section with a width that allows the insertion of the chip portion is provided, and the pad portion for the chip component is formed so as to be embedded in the V-shaped groove, and the embedded portion and the surface of the other portion are flush with each other. A printed wiring board characterized by being configured as follows.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987146999U JPH0747901Y2 (en) | 1987-09-25 | 1987-09-25 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987146999U JPH0747901Y2 (en) | 1987-09-25 | 1987-09-25 | Printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6452274U JPS6452274U (en) | 1989-03-31 |
| JPH0747901Y2 true JPH0747901Y2 (en) | 1995-11-01 |
Family
ID=31417008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987146999U Expired - Lifetime JPH0747901Y2 (en) | 1987-09-25 | 1987-09-25 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0747901Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2011077487A1 (en) * | 2009-12-24 | 2011-06-30 | 三菱電機株式会社 | Electronic component device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61160992A (en) * | 1985-01-09 | 1986-07-21 | 松下電器産業株式会社 | Printed wiring board |
-
1987
- 1987-09-25 JP JP1987146999U patent/JPH0747901Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6452274U (en) | 1989-03-31 |
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