JPH0735432Y2 - 集積回路素子の保持構造 - Google Patents
集積回路素子の保持構造Info
- Publication number
- JPH0735432Y2 JPH0735432Y2 JP10543087U JP10543087U JPH0735432Y2 JP H0735432 Y2 JPH0735432 Y2 JP H0735432Y2 JP 10543087 U JP10543087 U JP 10543087U JP 10543087 U JP10543087 U JP 10543087U JP H0735432 Y2 JPH0735432 Y2 JP H0735432Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- circuit board
- holding structure
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Cooling Or The Like Of Electrical Apparatus (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10543087U JPH0735432Y2 (ja) | 1987-07-09 | 1987-07-09 | 集積回路素子の保持構造 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10543087U JPH0735432Y2 (ja) | 1987-07-09 | 1987-07-09 | 集積回路素子の保持構造 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6413145U JPS6413145U (pt) | 1989-01-24 |
JPH0735432Y2 true JPH0735432Y2 (ja) | 1995-08-09 |
Family
ID=31338036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10543087U Expired - Lifetime JPH0735432Y2 (ja) | 1987-07-09 | 1987-07-09 | 集積回路素子の保持構造 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0735432Y2 (pt) |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56172970U (pt) * | 1980-05-20 | 1981-12-21 | ||
JPS57162371A (en) * | 1981-03-30 | 1982-10-06 | Seiko Epson Corp | Mos semiconductor memory device |
JPS5838625U (ja) * | 1981-09-07 | 1983-03-14 | 岩野 勝 | 二分シュ−ト |
JPS6148424A (ja) * | 1984-08-13 | 1986-03-10 | Tokuyama Soda Co Ltd | 導電性を有する含水珪酸の製造方法 |
-
1987
- 1987-07-09 JP JP10543087U patent/JPH0735432Y2/ja not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS6413145U (pt) | 1989-01-24 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS6224658A (ja) | 集積回路パツケ−ジ | |
JPH0325023B2 (pt) | ||
JPH0550134B2 (pt) | ||
US7006353B2 (en) | Apparatus and method for attaching a heat sink to an integrated circuit module | |
JPH0712069B2 (ja) | 電子部品パッケージ | |
JP3744927B2 (ja) | カプセル化電子部品、特に集積回路の製造方法 | |
JPH06103698B2 (ja) | 多数の回路要素を取り付けうる両面回路板 | |
US6093894A (en) | Multiconductor bonded connection assembly with direct thermal compression bonding through a base layer | |
JPH0735432Y2 (ja) | 集積回路素子の保持構造 | |
US4536825A (en) | Leadframe having severable fingers for aligning one or more electronic circuit device components | |
JP2504486B2 (ja) | 混成集積回路構造 | |
JPH11312770A (ja) | 薄型icの放熱フィン | |
JPH0669119B2 (ja) | 電子部品の熱放散装置 | |
US6755229B2 (en) | Method for preparing high performance ball grid array board and jig applicable to said method | |
JP2813683B2 (ja) | 電子部品搭載用基板 | |
JPH01120856A (ja) | リードフレーム | |
JP4656766B2 (ja) | 半導体装置の製造方法 | |
JPH0631723Y2 (ja) | 半導体装置 | |
JP2686156B2 (ja) | 熱放散型半導体パッケージ | |
JP2968704B2 (ja) | 半導体装置 | |
JPH0610718Y2 (ja) | 集積回路素子の保持構造 | |
JPH08167762A (ja) | 厚膜混成集積回路 | |
JP3490780B2 (ja) | 混成集積回路装置 | |
JP2661230B2 (ja) | 混成集積回路装置 | |
JPS5994897A (ja) | 混成集積回路の製造方法 |