JPH0735432Y2 - Integrated circuit element holding structure - Google Patents
Integrated circuit element holding structureInfo
- Publication number
- JPH0735432Y2 JPH0735432Y2 JP10543087U JP10543087U JPH0735432Y2 JP H0735432 Y2 JPH0735432 Y2 JP H0735432Y2 JP 10543087 U JP10543087 U JP 10543087U JP 10543087 U JP10543087 U JP 10543087U JP H0735432 Y2 JPH0735432 Y2 JP H0735432Y2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- integrated circuit
- circuit board
- holding structure
- circuit element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Description
【考案の詳細な説明】 （産業上の利用分野） 本考案は、集積回路素子をプリント基板に取付けるに当
ってその作業性を著しく向上した、集積回路素子の保持
構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to a holding structure for an integrated circuit element, which is remarkably improved in workability in mounting the integrated circuit element on a printed circuit board.
（従来の技術） 集積回路は種々の用途に使用される。この集積回路の素
子はICチップに形成され、基板に取付けられる。基板に
取付けるに当っては、放熱効果を上げる配慮が必要とな
る。そこで本考案者は基板に孔を明けてこの孔にICチッ
プを挿入し、ICチップの下面を基板の下に位置する放熱
板に直接接触させ、放熱効果を向上させるものを案出し
ている。(Prior Art) Integrated circuits are used in various applications. The elements of this integrated circuit are formed on an IC chip and attached to a substrate. When mounting on a board, it is necessary to consider how to improve the heat dissipation effect. Therefore, the present inventor has devised a device in which a hole is formed in a substrate, an IC chip is inserted into this hole, and the lower surface of the IC chip is directly contacted with a heat dissipation plate located under the substrate to improve the heat dissipation effect.
（考案が解決しようとする問題点） この構造によってICチップの放熱効果を著しく向上させ
ることに成功したが、製作過程において一つだけ不便な
ことがある。すなわち、複数個のICチップを１枚の基板
に取り付ける場合において、検査によりそのうちの１個
のみに不良品が出たとき、そのICチップのみを基板から
除去しようとしても、ICチップは接着によって放熱板に
固着されているので、ICチップを孔から除去する作業が
円滑にいかないのである。本考案はこの点に鑑みて成さ
れたものである。(Problems to be solved by the invention) This structure succeeded in significantly improving the heat dissipation effect of the IC chip, but there is one inconvenience in the manufacturing process. That is, when a plurality of IC chips are attached to one board and only one of them is defective due to the inspection, even if it is attempted to remove only that IC chip from the board, the IC chips will radiate heat. Since it is fixed to the plate, the work of removing the IC chip from the hole is not smooth. The present invention has been made in view of this point.
上記問題点を解決するために、本考案の集積回路素子の
保持構造は、良熱伝導材からなる金属の放熱板上に、上
下面に貫通しかつ一縁にのみ向けて開口する切欠きを複
数個設けた積層状態のプリント基板を接合し、前記切欠
き内に露出した前記放熱板に、下面が接するようにICチ
ップを接着し、このICチップのボンディング用蒸着部と
前記プリント基板との間をボンディングワイヤにより接
続し、前記基板の一縁側から個別にICチップを取外し可
能に組み付けたことを特徴としている。In order to solve the above-mentioned problems, the integrated circuit element holding structure of the present invention has a metal heat-dissipating plate made of a good heat conducting material having a notch that penetrates the upper and lower surfaces and is open only to one edge. A plurality of laminated printed circuit boards are joined, the heat dissipation plate exposed in the cutout is bonded with an IC chip so that the lower surface is in contact, and a vapor deposition portion for bonding of the IC chip and the printed circuit board are provided. It is characterized in that the IC chips are individually detachably assembled from one edge side of the substrate by connecting them with a bonding wire.
このような構成とすれば、１枚の基板に複数個のICチッ
プを取付けたものにおいて、検査工程によりそのうちの
１個のみが不良であった場合、その１個を接着剤が溶融
する程度に局部的に加熱し、加熱したところでICチップ
を切欠きの開いている部分から外力で押し出すことによ
り、容易に基板から除去できることになる。除去後は新
品のICチップを取付ければよい。With such a structure, in the case where a plurality of IC chips are attached to one substrate and only one of them is defective in the inspection process, the adhesive is melted to the extent that only one of them is defective. It is possible to easily remove the IC chip from the substrate by heating it locally and pushing the IC chip from the open portion of the notch with external force when heated. After removal, a new IC chip should be attached.
（実施例） 次に、本考案の一実施例を図について説明すると、１は
銅またはアルミニューム等、熱伝導性の良好な材質から
なる放熱板である。この放熱板１の上面には、一部に、
方形で一縁に向けて開口する切欠き２を形成した、ガラ
スエポキシ材からなる積層状態のプリント基板（以下、
基板という）３が接着剤（図示せず）によって接合され
ており、この基板３の切欠き２の部分には周囲を基板３
に接しないようにして、集積回路素子であるICチップ４
が配設されている。(Embodiment) Next, an embodiment of the present invention will be described with reference to the drawings. Reference numeral 1 is a heat dissipation plate made of a material having good thermal conductivity such as copper or aluminum. On the upper surface of this heat dissipation plate 1,
A laminated printed circuit board made of glass epoxy material (hereinafter,
A substrate 3 is bonded by an adhesive (not shown), and the periphery of the notch 2 of the substrate 3 is surrounded by the substrate 3
IC chip 4 which is an integrated circuit element so as not to contact
Is provided.
ICチップ４は、下面が放熱板１の上面に接しており、こ
の部分が熱伝導が良好な材質からなる接着剤（図示せ
ず）によって接合されている。ICチップ４にはその表面
にボンディング用のアルミ蒸着部（図示せず）が設けら
れており、このアルミ蒸着部と積層状態の基板３の間は
金線からなるボンディグワイヤ（以下、ワイヤという）
５によって接続されている。積層状態の基板３は、全体
の回路をたとえば同形の５枚の基板に分割して形成し、
それぞれの基板を重ね合せて圧縮し１個に形成されたも
のである。これによってどのように複雑な回路にも短絡
等の支障なく、対応できることになる。そして、ワイヤ
５は一番上部の基板には直接接続され、２枚目以降の基
板には、その上部の基板に順次孔を明けてその孔を通し
て必要個所に接続されることになる。これによって接続
個所の多いICチップであっても、配線が同一面内で交差
することを回避できるので、短絡の虞れがなくなること
になる。The lower surface of the IC chip 4 is in contact with the upper surface of the heat dissipation plate 1, and this portion is bonded by an adhesive (not shown) made of a material having good heat conduction. The IC chip 4 is provided with an aluminum vapor deposition portion (not shown) for bonding on the surface thereof, and a bonding wire (hereinafter referred to as a wire) made of a gold wire is provided between the aluminum vapor deposition portion and the substrate 3 in a laminated state. )
Connected by five. The substrate 3 in a laminated state is formed by dividing the entire circuit into, for example, five substrates of the same shape,
It is formed by stacking and compressing each substrate. As a result, no matter how complicated the circuit is, it is possible to deal with it without any trouble such as a short circuit. Then, the wire 5 is directly connected to the uppermost substrate, and holes are sequentially formed in the upper substrates of the second and subsequent substrates, and the wires 5 are connected to necessary portions through the holes. As a result, even if the IC chip has many connection points, it is possible to prevent the wirings from crossing in the same plane, so that there is no possibility of short circuit.
このように構成されたこの保持構造によれば、ICチップ
４のうちの１個に不良品が出たときに、そのICチップ４
を温風等により局部的に加熱して接着剤を溶融状態に
し、これに切欠き２から脱出する方向（第１図における
矢印Ａ方向）の外力を加えることによって、ICチップ４
を容易に切欠き２内から除去することができる。なお、
除去するときには、ボンディング用のワイヤは切断され
る。According to the holding structure thus configured, when one of the IC chips 4 has a defective product, the IC chip 4 is defective.
Is locally heated by hot air or the like to melt the adhesive, and an external force is applied to the adhesive in a direction to escape from the notch 2 (direction of arrow A in FIG. 1).
Can be easily removed from the notch 2. In addition,
When removing, the bonding wire is cut.
（考案の効果） 本考案は以上説明したように構成したものであるから、
複数のICチップを個々に切欠きに挿入して取り付けるこ
とで充分な放熱効果を得ることができる。(Effect of the Invention) Since the present invention is configured as described above,
Sufficient heat dissipation effect can be obtained by inserting and mounting multiple IC chips individually in the notches.
また、検査工程で発見されれた不良品のICチップのみを
加熱して、他の部分を熱的に痛めずに、プリント基板の
一縁にのみ向けて横方向に取り外すので、不良品の取り
外し、及び良品の交換が迅速にかつ容易にできる。In addition, since only the defective IC chip found in the inspection process is heated and the other parts are not thermally damaged, it is laterally removed toward only one edge of the printed circuit board. , And good products can be replaced quickly and easily.
第１図は本考案の一実施例の平面図、第２図は第１図の
もののII−II線に沿う断面図である。 １…放熱板、２…切欠き ３…基板、４…ICチップ ５…ワイヤFIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 is a sectional view taken along the line II-II of FIG. 1 ... Heat sink, 2 ... Notch 3 ... Board, 4 ... IC chip 5 ... Wire
Claims (1)
下面に貫通しかつ一縁にのみ向けて開口する切欠きを複
数個設けた積層状態のプリント基板を接合し、前記切欠
き内に露出した前記放熱板に、下面が接するようにICチ
ップを接着し、このICチップのボンディング用蒸着部と
前記プリント基板との間をボンディングワイヤにより接
続し、前記基板の一縁側から個別にICチップを取外し可
能に組み付けたことを特徴とする集積回路素子の保持構
造。1. A printed circuit board in a laminated state, in which a plurality of notches that penetrate the upper and lower surfaces and open toward only one edge are provided on a metal heat dissipation plate made of a good heat conductive material are joined, An IC chip is adhered to the heat sink exposed in the notch so that the lower surface is in contact, and a bonding wire is used to connect the vapor deposition part for bonding of the IC chip and the printed circuit board, individually from one edge side of the circuit board. A holding structure for an integrated circuit element, characterized in that an IC chip is detachably attached to the.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10543087U JPH0735432Y2 (en) | 1987-07-09 | 1987-07-09 | Integrated circuit element holding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10543087U JPH0735432Y2 (en) | 1987-07-09 | 1987-07-09 | Integrated circuit element holding structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413145U JPS6413145U (en) | 1989-01-24 |
| JPH0735432Y2 true JPH0735432Y2 (en) | 1995-08-09 |
Family
ID=31338036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10543087U Expired - Lifetime JPH0735432Y2 (en) | 1987-07-09 | 1987-07-09 | Integrated circuit element holding structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0735432Y2 (en) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56172970U (en) * | 1980-05-20 | 1981-12-21 | ||
| JPS57162371A (en) * | 1981-03-30 | 1982-10-06 | Seiko Epson Corp | Mos semiconductor memory device |
| JPS5838625U (en) * | 1981-09-07 | 1983-03-14 | 岩野 勝 | bifurcated shot |
| JPS6148424A (en) * | 1984-08-13 | 1986-03-10 | Tokuyama Soda Co Ltd | Preparation of hydrous silicic acid having electroconductivity |
-
1987
- 1987-07-09 JP JP10543087U patent/JPH0735432Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6413145U (en) | 1989-01-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS6224658A (en) | Integrated circuit package | |
| JPH0325023B2 (en) | ||
| JPH0550134B2 (en) | ||
| JPH0712069B2 (en) | Electronic component package | |
| US7006353B2 (en) | Apparatus and method for attaching a heat sink to an integrated circuit module | |
| JP3744927B2 (en) | Method for manufacturing encapsulated electronic components, in particular integrated circuits | |
| JPH06103698B2 (en) | Double-sided circuit board to which many circuit elements can be attached | |
| US6093894A (en) | Multiconductor bonded connection assembly with direct thermal compression bonding through a base layer | |
| JPH0735432Y2 (en) | Integrated circuit element holding structure | |
| US4536825A (en) | Leadframe having severable fingers for aligning one or more electronic circuit device components | |
| JP2504486B2 (en) | Hybrid integrated circuit structure | |
| JPH11312770A (en) | Radiation fin for thin ic | |
| JPH0669119B2 (en) | Heat dissipation device for electronic components | |
| US6755229B2 (en) | Method for preparing high performance ball grid array board and jig applicable to said method | |
| JP2813683B2 (en) | Substrate for mounting electronic components | |
| JPH01120856A (en) | Lead frame | |
| JP4656766B2 (en) | Manufacturing method of semiconductor device | |
| JPH0631723Y2 (en) | Semiconductor device | |
| JP2686156B2 (en) | Heat dissipation type semiconductor package | |
| JP2536568B2 (en) | Lead frame | |
| JP2968704B2 (en) | Semiconductor device | |
| JPH0610718Y2 (en) | Integrated circuit element holding structure | |
| JPH08167762A (en) | Thick film hybrid integrated circuit | |
| JP2661230B2 (en) | Hybrid integrated circuit device | |
| JPS5994897A (en) | Method of producing hybrid integrated circuit |