JPH0610718Y2 - Integrated circuit element holding structure - Google Patents
Integrated circuit element holding structureInfo
- Publication number
- JPH0610718Y2 JPH0610718Y2 JP10542987U JP10542987U JPH0610718Y2 JP H0610718 Y2 JPH0610718 Y2 JP H0610718Y2 JP 10542987 U JP10542987 U JP 10542987U JP 10542987 U JP10542987 U JP 10542987U JP H0610718 Y2 JPH0610718 Y2 JP H0610718Y2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- chip
- substrate
- circuit element
- holding structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
Description
【考案の詳細な説明】 （産業上の利用分野） 本考案は、メモリとして記憶容量の大きい集積回路を、
歩留まり良く製作できるようにした、集積回路素子の保
持構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Industrial field of application) The present invention relates to an integrated circuit having a large storage capacity as a memory,
The present invention relates to a holding structure for integrated circuit elements, which can be manufactured with a high yield.
（従来の技術） 集積回路は種々の用途に使用される。この集積回路の素
子はＩＣチップに形成されるが、メモリとして使用され
る場合、その容量を大きくしようとすると必然的に外形
寸法が大きくなるし、また製作にも高度の技術が必要に
なって製作時の歩留まりが悪くなる。そこで記憶容量の
大きいＩＣチップを１個の素子で製作せずに複数個で得
ようという案がでてくる。このようにすれば比較的に製
作し易い（したがって歩留まりが高い）小容量のＩＣチ
ップ複数個で大容量のメモリ回路を組めることになる。
これは、たとえば256ＫビットのＩＣチップ４個で１Ｍ
ビットのＩＣ回路が組めるということである。(Prior Art) Integrated circuits are used in various applications. The element of this integrated circuit is formed on an IC chip, but when it is used as a memory, an attempt to increase its capacity inevitably causes an increase in external dimensions, and also requires a high level of technology for manufacturing. The yield at the time of production will be poor. Therefore, there is a plan to obtain a plurality of IC chips having a large storage capacity without manufacturing them with one element. In this way, a large-capacity memory circuit can be assembled with a plurality of small-capacity IC chips that are relatively easy to manufacture (and therefore have a high yield).
This is 1M with 4 256Kbit IC chips
This means that a bit IC circuit can be assembled.
（考案が解決しようとする問題点） しかしながら複数個のＩＣチップを単純に配設し電気的
な接続を行ったのみでは、全体としての外形寸法が大き
くなって規格寸法のパッケージ内に収容できなくなって
しまう。そこでレイアウトに工夫を凝らして極力全体寸
法の縮減化を図ることになるが、そのようにすると放熱
に特別の考慮を払わない限り熱の影響でＩＣチップの特
性の劣化を招くことになる。本考案はこの点をも考慮し
て成されたものであり、製作時の歩留まりを良くし、あ
わせて全体の外形寸法を極力小さくするとともに、放熱
効果にも優れた構造を提供することを目的とする。(Problems to be solved by the invention) However, if only a plurality of IC chips are simply arranged and electrically connected, the overall external dimension becomes large and the package cannot be accommodated in a standard size package. Will end up. Therefore, the layout should be devised to reduce the overall size as much as possible, but if this is done, the characteristics of the IC chip will be deteriorated by the influence of heat unless special consideration is given to heat dissipation. The present invention has been made in consideration of this point, and it is an object of the present invention to improve the yield at the time of manufacturing, and at the same time, to reduce the overall external dimensions as much as possible and to provide a structure excellent in heat dissipation effect. And
（問題点を解決するための手段） 本考案は上記問題点を解決するための手段として、集積
回路素子の保持構造を、良熱伝導材からなる放熱板の上
面に一部に孔または切欠きを設けた積層状態の基板を接
合し、該基板の前記孔または切欠きにＩＣチップをその
下面が前記放熱板に接するようにして挿入し、該ＩＣチ
ップのボンディングパッドと前記積層状態の各基板との
間をボンディングワイヤにより接続した集積回路素子を
２枚製作し、該２枚の集積回路素子を前記放熱板の部分
において背中合せに接着した構成としたものである。(Means for Solving the Problems) As a means for solving the above problems, the present invention provides a holding structure for an integrated circuit element, which is partially provided with holes or notches on the upper surface of a heat dissipation plate made of a good heat conductive material. Are joined together, and the IC chip is inserted into the hole or notch of the substrate so that the lower surface thereof is in contact with the heat dissipation plate, and the bonding pad of the IC chip and each substrate in the laminated state. Two integrated circuit elements are connected to each other by a bonding wire, and the two integrated circuit elements are bonded back to back at the heat dissipation plate.
（作用） このような構成とすれば、製作に当ってまず背中合せに
接着される前の、１枚の状態の集積回路素子のＩＣチッ
プの検査を行い、この検査によって良品とされたものど
うしの２枚を背中合せに接着することになる。したがっ
て全部のＩＣチップを取付けた状態で検査を行うものに
比し、歩留まりが著しく良いものになる。なた、放熱板
は２枚が接合されることによって薄いもので済むことに
なり、全体としての寸法削減に寄与するとともに、一般
にすべてのＩＣチップが同時に使用されることは少ない
ことから、放熱効果の点においても広い面積での効率の
高い放熱効果が期待できることになる。(Operation) With such a configuration, in manufacturing, first, an IC chip of an integrated circuit element in a state of one sheet before being bonded back to back is inspected, and the IC chips which are judged to be non-defective by this inspection are tested. The two pieces will be glued back to back. Therefore, the yield is remarkably better than that in which the inspection is performed with all the IC chips attached. It should be noted that the heat radiation plate can be made thin by joining the two, which contributes to the overall size reduction and, in general, it is unlikely that all IC chips will be used at the same time. Also in terms of (2), a highly efficient heat dissipation effect in a large area can be expected.
（実施例） 次に、本考案の一実施例を、本考案の完成状態を示した
第１図と、その状態に至る前の状態である第３図(a)、
(b)および第４図(a)、(b)について説明する。なお、第３
図および第４図に(a)および(b)で示すものは、全く同一
あるいは左右対称のものである。これらの図において１
は銅またはアルミニューム等、熱伝導性の良好な材質か
らなる放熱板である。この放熱板１は、次に説明する製
作工程終了の後、２枚が接着剤２によって背中合せに接
合されるものである。放熱板１の上面には、一部に方形
の切欠き３を形成した、ガラスエポキシ材からなる積層
状態のプリント基板（以下、基板という）４が接着剤
（図示せず）によって接合されており、この基板４の切
欠き３の部分には周囲を基板４に接しないようにして、
集積回路素子であるＩＣチップ５が配設されている。Ｉ
Ｃチップ５は、下面が放熱板１の上面に接しており、こ
の部分が熱伝導が良好な材質からなる接着剤（図示せ
ず）によって接合されている。ＩＣチップ５にはその表
面にボンディング用のアルミ蒸着部（図示せず）が設け
られており、このアルミ蒸着部と積層状態の基板４の間
はボンディングワイヤ（以下、ワイヤという）６によっ
て接続されている。積層状態の基板４は、たとえば同形
の５枚の基板が重ね合せられて形成されており、全体の
回路を枚数分に分割したものである。この複数枚の基板
は圧縮されて積層状態にされているため、どのような複
雑な回路にも対応できることになる。ワイヤ６は一番上
部の基板には直接接続され、２枚目以降の基板には、そ
の上部の基板に順次孔を明けてその孔を通して必要個所
に接続されることになる。これによって接続個所の多い
ＩＣチップであっても、配線が同一面内で交差すること
を回避できるので、短絡の虞れがなくなることになる。
以上説明した手順によって製作された、それぞれ２個ず
つＩＣチップ５を有する状態の第３図、第４図に示すも
のを接着剤２によって背中合せに接合すると第１図のも
ののようになる。これに接続用の端子７を取付ければ
（第２図参照）、本考案に係る部分の製作作業は終了す
る。次に、第１図に示す状態のすべてをエポキシ樹脂で
固めれば、完成状態になる。(Embodiment) Next, an embodiment of the present invention is shown in FIG. 1 showing a completed state of the present invention and FIG. 3 (a) showing a state before reaching the state.
(b) and FIGS. 4 (a) and (b) will be described. The third
What is shown in FIGS. 4 and (a) and (b) is exactly the same or symmetrical. 1 in these figures
Is a radiator plate made of a material having good thermal conductivity such as copper or aluminum. Two of the heat dissipation plates 1 are joined back to back with an adhesive 2 after the manufacturing process described below is completed. On the upper surface of the heat sink 1, a printed circuit board (hereinafter referred to as a circuit board) 4 made of a glass epoxy material and having a rectangular notch 3 partially formed is bonded by an adhesive (not shown). , The periphery of the notch 3 of the substrate 4 is not in contact with the substrate 4,
An IC chip 5 which is an integrated circuit element is arranged. I
The lower surface of the C chip 5 is in contact with the upper surface of the heat dissipation plate 1, and this portion is bonded by an adhesive (not shown) made of a material having good heat conduction. The IC chip 5 is provided with an aluminum vapor deposition portion (not shown) for bonding on the surface thereof, and the aluminum vapor deposition portion and the substrate 4 in a laminated state are connected by a bonding wire (hereinafter referred to as wire) 6. ing. The substrate 4 in a laminated state is formed by stacking, for example, five substrates of the same shape, and is obtained by dividing the entire circuit into the number of substrates. Since the plurality of substrates are compressed and laminated, any complicated circuit can be dealt with. The wire 6 is directly connected to the uppermost substrate, and holes are sequentially formed in the upper substrates of the second and subsequent substrates, and the wires 6 are connected to the necessary places through the holes. As a result, even in an IC chip having many connection points, it is possible to prevent the wirings from crossing in the same plane, so that there is no fear of a short circuit.
The two shown in FIGS. 3 and 4 each having two IC chips 5 manufactured by the procedure described above are joined back to back with the adhesive 2 to obtain the one shown in FIG. When the terminal 7 for connection is attached to this (see FIG. 2), the manufacturing work of the part according to the present invention is completed. Next, if all of the states shown in FIG. 1 are hardened with an epoxy resin, a completed state is obtained.
以上説明した実施例にあっては、ＩＣチップ５を基板４
の切欠き３内に配設したが、基板４の切欠き３に代えて
孔を設け、ＩＣチップ５をのの孔内に配設するようにし
ても良いものである。In the embodiment described above, the IC chip 5 is mounted on the substrate 4
Although the IC chip 5 is arranged in the notch 3, the hole may be provided instead of the notch 3 in the substrate 4 and the IC chip 5 may be arranged in the hole 3.
（考案の効果） 本考案は以上説明したように構成したものであるから、
２枚を接着する前の状態で検査したＩＣチップの良品の
みを選別してその２枚を放熱板の部分で背中合せに接着
することができ、最初から全部のＩＣチップを取付けた
状態で検査するものに比し、製作時の歩留まりを著しく
高くすることができる。また、２枚を接着する前の放熱
板の板厚寸法を通常のものより薄くしても２枚の接合に
よって実質的な板厚が増すから、放熱効果に支障を生じ
ないことになる。そしてこのように、放熱板の板厚を薄
くすることができること、および放熱板を背中合せに接
合することに起因して、全体の外形寸法を充分に小さく
することが可能となる。(Effect of the Invention) Since the present invention is configured as described above,
Only good IC chips that have been inspected before being bonded can be selected, and the two can be bonded back to back at the heat sink, and all IC chips can be inspected from the beginning. The yield at the time of manufacture can be made significantly higher than that of products. Further, even if the thickness of the heat radiating plate before bonding the two sheets is smaller than that of a normal one, the substantial thickness increases due to the joining of the two sheets, so that the heat radiation effect is not hindered. As described above, it is possible to reduce the thickness of the heat dissipation plate and to join the heat dissipation plates back to back, whereby the overall outer dimensions can be sufficiently reduced.
第１図は本考案の一実施例を断面で示すもので第２図の
Ｉ−Ｉ線に沿う断面図、第２図は第１図のものの平面
図、第３図(a)、(b)は接合前の状態を示す平面図、第４
図(a)、(b)は第３図のそれぞれａ、ｂ線に沿った断面図
である。 １……放熱板、２……接着剤 ３……切欠き、４……基板 ５……ＩＣチップ、６……ワイヤ ７……端子FIG. 1 is a sectional view showing an embodiment of the present invention, which is a sectional view taken along the line I--I of FIG. 2, FIG. 2 is a plan view of FIG. 1, and FIGS. ) Is a plan view showing a state before joining,
3A and 3B are sectional views taken along the lines a and b in FIG. 3, respectively. 1 ... Heat sink, 2 ... Adhesive, 3 Notch, 4 ... Substrate, 5 ... IC chip, 6 ... Wire, 7 ... Terminal
Claims (1)
孔または切欠きを設けた積層状態の基板を接合し、該基
板の前記孔または切欠きにＩＣチップをその下面が前記
放熱板に接するようにして挿入し、該ＩＣチップのボン
ディングパッドと前記積層状態の各基板との間をボンデ
ィングワイヤにより接続した集積回路素子を２枚製作
し、該２枚の集積回路素子を前記放熱板の部分において
背中合せに接着したことを特徴とする集積回路素子の保
持構造。1. A laminated substrate, in which a hole or a notch is partially provided on an upper surface of a heat dissipation plate made of a good heat conductive material, is bonded, and an IC chip is placed in the hole or the notch of the substrate with the lower surface thereof Two integrated circuit elements which are inserted so as to be in contact with the heat sink and in which bonding pads of the IC chip and each of the stacked substrates are connected by bonding wires are manufactured. A holding structure for an integrated circuit element, characterized in that it is adhered back-to-back at the heat sink.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10542987U JPH0610718Y2 (en) | 1987-07-09 | 1987-07-09 | Integrated circuit element holding structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10542987U JPH0610718Y2 (en) | 1987-07-09 | 1987-07-09 | Integrated circuit element holding structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413144U JPS6413144U (en) | 1989-01-24 |
| JPH0610718Y2 true JPH0610718Y2 (en) | 1994-03-16 |
Family
ID=31338034
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10542987U Expired - Lifetime JPH0610718Y2 (en) | 1987-07-09 | 1987-07-09 | Integrated circuit element holding structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0610718Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10388596B2 (en) * | 2014-11-20 | 2019-08-20 | Nsk Ltd. | Electronic part mounting heat-dissipating substrate |
-
1987
- 1987-07-09 JP JP10542987U patent/JPH0610718Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6413144U (en) | 1989-01-24 |
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