JPS6413145U - - Google Patents

Info

Publication number
JPS6413145U
JPS6413145U JP10543087U JP10543087U JPS6413145U JP S6413145 U JPS6413145 U JP S6413145U JP 10543087 U JP10543087 U JP 10543087U JP 10543087 U JP10543087 U JP 10543087U JP S6413145 U JPS6413145 U JP S6413145U
Authority
JP
Japan
Prior art keywords
notch
chip
heat sink
board
laminated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10543087U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0735432Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10543087U priority Critical patent/JPH0735432Y2/ja
Publication of JPS6413145U publication Critical patent/JPS6413145U/ja
Application granted granted Critical
Publication of JPH0735432Y2 publication Critical patent/JPH0735432Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP10543087U 1987-07-09 1987-07-09 集積回路素子の保持構造 Expired - Lifetime JPH0735432Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10543087U JPH0735432Y2 (ja) 1987-07-09 1987-07-09 集積回路素子の保持構造

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10543087U JPH0735432Y2 (ja) 1987-07-09 1987-07-09 集積回路素子の保持構造

Publications (2)

Publication Number Publication Date
JPS6413145U true JPS6413145U (pt) 1989-01-24
JPH0735432Y2 JPH0735432Y2 (ja) 1995-08-09

Family

ID=31338036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10543087U Expired - Lifetime JPH0735432Y2 (ja) 1987-07-09 1987-07-09 集積回路素子の保持構造

Country Status (1)

Country Link
JP (1) JPH0735432Y2 (pt)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56172970U (pt) * 1980-05-20 1981-12-21
JPS57162371A (en) * 1981-03-30 1982-10-06 Seiko Epson Corp Mos semiconductor memory device
JPS5838625U (ja) * 1981-09-07 1983-03-14 岩野　勝 二分シュ−ト
JPS6148424A (ja) * 1984-08-13 1986-03-10 Tokuyama Soda Co Ltd 導電性を有する含水珪酸の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56172970U (pt) * 1980-05-20 1981-12-21
JPS57162371A (en) * 1981-03-30 1982-10-06 Seiko Epson Corp Mos semiconductor memory device
JPS5838625U (ja) * 1981-09-07 1983-03-14 岩野　勝 二分シュ−ト
JPS6148424A (ja) * 1984-08-13 1986-03-10 Tokuyama Soda Co Ltd 導電性を有する含水珪酸の製造方法

Also Published As

Publication number Publication date
JPH0735432Y2 (ja) 1995-08-09

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