JPH07263694A - 浅い接合金属酸化物半導体電界効果トランジスタの製造方法 - Google Patents
浅い接合金属酸化物半導体電界効果トランジスタの製造方法Info
- Publication number
- JPH07263694A JPH07263694A JP7048597A JP4859795A JPH07263694A JP H07263694 A JPH07263694 A JP H07263694A JP 7048597 A JP7048597 A JP 7048597A JP 4859795 A JP4859795 A JP 4859795A JP H07263694 A JPH07263694 A JP H07263694A
- Authority
- JP
- Japan
- Prior art keywords
- buffer layer
- manufacturing
- layer
- dopant
- ions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
-
- H10P30/204—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/258—Source or drain electrodes for field-effect devices characterised by the relative positions of the source or drain electrodes with respect to the gate electrode
- H10D64/259—Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0147—Manufacturing their gate sidewall spacers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
- H10D84/85—Complementary IGFETs, e.g. CMOS
-
- H10P30/212—
-
- H10P30/225—
-
- H10P32/1414—
-
- H10P32/171—
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US08/208,548 US5439831A (en) | 1994-03-09 | 1994-03-09 | Low junction leakage MOSFETs |
| US08/208548 | 1994-03-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07263694A true JPH07263694A (ja) | 1995-10-13 |
Family
ID=22774995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7048597A Pending JPH07263694A (ja) | 1994-03-09 | 1995-03-08 | 浅い接合金属酸化物半導体電界効果トランジスタの製造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US5439831A (cg-RX-API-DMAC10.html) |
| EP (1) | EP0671759A3 (cg-RX-API-DMAC10.html) |
| JP (1) | JPH07263694A (cg-RX-API-DMAC10.html) |
| KR (1) | KR950034842A (cg-RX-API-DMAC10.html) |
| TW (1) | TW262585B (cg-RX-API-DMAC10.html) |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0151195B1 (ko) * | 1994-09-13 | 1998-10-01 | 문정환 | 박막 트랜지스터의 구조 및 제조방법 |
| KR0144020B1 (ko) * | 1995-02-24 | 1998-08-17 | 김주용 | 낮은 면저항을 갖는 접합 형성방법 |
| US6465295B1 (en) * | 1995-03-24 | 2002-10-15 | Seiko Instruments Inc. | Method of fabricating a semiconductor device |
| JPH0964355A (ja) * | 1995-08-25 | 1997-03-07 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
| US5923999A (en) * | 1996-10-29 | 1999-07-13 | International Business Machines Corporation | Method of controlling dopant diffusion and metal contamination in thin polycide gate conductor of mosfet device |
| US6284633B1 (en) * | 1997-11-24 | 2001-09-04 | Motorola Inc. | Method for forming a tensile plasma enhanced nitride capping layer over a gate electrode |
| TW387151B (en) * | 1998-02-07 | 2000-04-11 | United Microelectronics Corp | Field effect transistor structure of integrated circuit and the manufacturing method thereof |
| US6255180B1 (en) * | 1998-05-14 | 2001-07-03 | Cypress Semiconductor Corporation | Semiconductor device with outwardly tapered sidewall spacers and method for forming same |
| US5998248A (en) * | 1999-01-25 | 1999-12-07 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions with tapered spacer in isolation region |
| US6025242A (en) * | 1999-01-25 | 2000-02-15 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolation |
| US6022771A (en) * | 1999-01-25 | 2000-02-08 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regions |
| US5998273A (en) * | 1999-01-25 | 1999-12-07 | International Business Machines Corporation | Fabrication of semiconductor device having shallow junctions |
| JP3443355B2 (ja) * | 1999-03-12 | 2003-09-02 | 三洋電機株式会社 | 半導体装置の製造方法 |
| KR100395755B1 (ko) * | 2001-06-28 | 2003-08-21 | 삼성전자주식회사 | 비휘발성 메모리 소자 및 그 제조방법 |
| WO2003015138A2 (en) * | 2001-08-09 | 2003-02-20 | Amberwave Systems Corporation | Optimized buried-channel fets based on sige heterostructures |
| DE10146933B4 (de) * | 2001-09-24 | 2007-07-19 | Infineon Technologies Ag | Integrierte Halbleiteranordnung mit Abstandselement und Verfahren zu ihrer Herstellung |
| DE10250888B4 (de) * | 2002-10-31 | 2007-01-04 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterelement mit verbesserten Dotierprofilen und ein Verfahren zur Herstellung der Dotierprofile eines Halbleiterelements |
| US20040097027A1 (en) * | 2002-11-14 | 2004-05-20 | Won-Kyu Park | Method for manufacturing semiconductor device |
| US6720213B1 (en) | 2003-01-15 | 2004-04-13 | International Business Machines Corporation | Low-K gate spacers by fluorine implantation |
| US7737014B2 (en) * | 2003-12-08 | 2010-06-15 | International Business Machines Corporation | Reduction of boron diffusivity in pFETs |
| US8294224B2 (en) * | 2006-04-06 | 2012-10-23 | Micron Technology, Inc. | Devices and methods to improve carrier mobility |
| US7759208B1 (en) * | 2009-03-27 | 2010-07-20 | International Business Machines Corporation | Low temperature ion implantation for improved silicide contacts |
| JP2011249586A (ja) * | 2010-05-27 | 2011-12-08 | Elpida Memory Inc | 半導体装置の製造方法 |
| US10084060B2 (en) * | 2014-08-15 | 2018-09-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure and manufacturing method of the same |
| US10573722B2 (en) | 2016-02-17 | 2020-02-25 | General Electric Company | Systems and methods for in-situ doped semiconductor gate electrodes for wide bandgap semiconductor power devices |
Family Cites Families (39)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4417325A (en) * | 1981-07-13 | 1983-11-22 | Eliyahou Harari | Highly scaleable dynamic ram cell with self-signal amplification |
| US4558507A (en) * | 1982-11-12 | 1985-12-17 | Nec Corporation | Method of manufacturing semiconductor device |
| KR910006249B1 (ko) * | 1983-04-01 | 1991-08-17 | 가부시기가이샤 히다찌세이사꾸쇼 | 반도체 장치 |
| US4663825A (en) * | 1984-09-27 | 1987-05-12 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
| US4859620A (en) * | 1985-04-12 | 1989-08-22 | General Electric Company | Graded extended drain concept for reduced hot electron effect |
| US4701423A (en) * | 1985-12-20 | 1987-10-20 | Ncr Corporation | Totally self-aligned CMOS process |
| US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
| US4755479A (en) * | 1986-02-17 | 1988-07-05 | Fujitsu Limited | Manufacturing method of insulated gate field effect transistor using reflowable sidewall spacers |
| DE3728849C2 (de) * | 1986-08-29 | 1995-07-13 | Toshiba Kawasaki Kk | MIS (Metallisolatorhalbleiter)-Halbleitervorrichtung und Verfahren zur Herstellung derselben |
| US4784965A (en) * | 1986-11-04 | 1988-11-15 | Intel Corporation | Source drain doping technique |
| US4757026A (en) * | 1986-11-04 | 1988-07-12 | Intel Corporation | Source drain doping technique |
| US4728617A (en) * | 1986-11-04 | 1988-03-01 | Intel Corporation | Method of fabricating a MOSFET with graded source and drain regions |
| US4801555A (en) * | 1987-01-14 | 1989-01-31 | Motorola, Inc. | Double-implant process for forming graded source/drain regions |
| US4788160A (en) * | 1987-03-31 | 1988-11-29 | Texas Instruments Incorporated | Process for formation of shallow silicided junctions |
| US4837173A (en) * | 1987-07-13 | 1989-06-06 | Motorola, Inc. | N-channel MOS transistors having source/drain regions with germanium |
| US4928156A (en) * | 1987-07-13 | 1990-05-22 | Motorola, Inc. | N-channel MOS transistors having source/drain regions with germanium |
| US4786609A (en) * | 1987-10-05 | 1988-11-22 | North American Philips Corporation, Signetics Division | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers |
| JPH02502414A (ja) * | 1987-12-02 | 1990-08-02 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | 半導体素子のための自己整列した相互接続 |
| US5081516A (en) * | 1987-12-02 | 1992-01-14 | Advanced Micro Devices, Inc. | Self-aligned, planarized contacts for semiconductor devices |
| US5057902A (en) * | 1987-12-02 | 1991-10-15 | Advanced Micro Devices, Inc. | Self-aligned semiconductor devices |
| US5028555A (en) * | 1987-12-02 | 1991-07-02 | Advanced Micro Devices, Inc. | Self-aligned semiconductor devices |
| US4977108A (en) * | 1987-12-02 | 1990-12-11 | Advanced Micro Devices, Inc. | Method of making self-aligned, planarized contacts for semiconductor devices |
| US5055427A (en) * | 1987-12-02 | 1991-10-08 | Advanced Micro Devices, Inc. | Process of forming self-aligned interconnects for semiconductor devices |
| US4914500A (en) * | 1987-12-04 | 1990-04-03 | At&T Bell Laboratories | Method for fabricating semiconductor devices which include sources and drains having metal-containing material regions, and the resulting devices |
| US4835112A (en) * | 1988-03-08 | 1989-05-30 | Motorola, Inc. | CMOS salicide process using germanium implantation |
| US4912061A (en) * | 1988-04-04 | 1990-03-27 | Digital Equipment Corporation | Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer |
| US4933739A (en) * | 1988-04-26 | 1990-06-12 | Eliyahou Harari | Trench resistor structures for compact semiconductor memory and logic devices |
| US5063422A (en) * | 1988-06-20 | 1991-11-05 | At&T Bell Laboratories | Devices having shallow junctions |
| US5006477A (en) * | 1988-11-25 | 1991-04-09 | Hughes Aircraft Company | Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices |
| US5047812A (en) * | 1989-02-27 | 1991-09-10 | Motorola, Inc. | Insulated gate field effect device |
| US4994404A (en) * | 1989-08-28 | 1991-02-19 | Motorola, Inc. | Method for forming a lightly-doped drain (LDD) structure in a semiconductor device |
| US5012306A (en) * | 1989-09-22 | 1991-04-30 | Board Of Regents, The University Of Texas System | Hot-carrier suppressed sub-micron MISFET device |
| US5235204A (en) * | 1990-08-27 | 1993-08-10 | Taiwan Semiconductor Manufacturing Company | Reverse self-aligned transistor integrated circuit |
| KR930010124B1 (ko) * | 1991-02-27 | 1993-10-14 | 삼성전자 주식회사 | 반도체 트랜지스터의 제조방법 및 그 구조 |
| US5086017A (en) * | 1991-03-21 | 1992-02-04 | Industrial Technology Research Institute | Self aligned silicide process for gate/runner without extra masking |
| US5182619A (en) * | 1991-09-03 | 1993-01-26 | Motorola, Inc. | Semiconductor device having an MOS transistor with overlapped and elevated source and drain |
| EP0537684B1 (en) * | 1991-10-15 | 1998-05-20 | Texas Instruments Incorporated | Improved performance lateral double-diffused MOS transistor and method of fabrication thereof |
| US5268317A (en) * | 1991-11-12 | 1993-12-07 | Siemens Aktiengesellschaft | Method of forming shallow junctions in field effect transistors |
| US5424571A (en) * | 1992-03-30 | 1995-06-13 | Sgs-Thomson Microelectronics, Inc. | Sloped spacer for mos field effect devices |
-
1994
- 1994-03-09 US US08/208,548 patent/US5439831A/en not_active Expired - Fee Related
-
1995
- 1995-01-24 TW TW084100599A patent/TW262585B/zh active
- 1995-01-25 EP EP95100991A patent/EP0671759A3/en not_active Withdrawn
- 1995-02-13 KR KR1019950002571A patent/KR950034842A/ko not_active Ceased
- 1995-03-08 JP JP7048597A patent/JPH07263694A/ja active Pending
-
1997
- 1997-08-11 US US08/908,125 patent/US5872382A/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| EP0671759A2 (en) | 1995-09-13 |
| KR950034842A (ko) | 1995-12-28 |
| TW262585B (cg-RX-API-DMAC10.html) | 1995-11-11 |
| US5872382A (en) | 1999-02-16 |
| EP0671759A3 (en) | 1996-07-17 |
| US5439831A (en) | 1995-08-08 |
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| Date | Code | Title | Description |
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| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050401 |
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| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060120 |
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