JPH07230696A - 半導体記憶装置 - Google Patents

半導体記憶装置

Info

Publication number
JPH07230696A
JPH07230696A JP19884094A JP19884094A JPH07230696A JP H07230696 A JPH07230696 A JP H07230696A JP 19884094 A JP19884094 A JP 19884094A JP 19884094 A JP19884094 A JP 19884094A JP H07230696 A JPH07230696 A JP H07230696A
Authority
JP
Japan
Prior art keywords
memory cell
cell array
memory
word line
driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19884094A
Other languages
English (en)
Japanese (ja)
Inventor
Yasushi Sakui
康司 作井
Hiroshi Nakamura
寛 中村
Tomoharu Tanaka
智晴 田中
Masaki Momotomi
正樹 百冨
Fujio Masuoka
富士雄 舛岡
Takehiro Hasegawa
武裕 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP19884094A priority Critical patent/JPH07230696A/ja
Priority to US08/360,289 priority patent/US5517457A/en
Priority to KR1019940036504A priority patent/KR100192630B1/ko
Priority to TW084100312A priority patent/TW307923B/zh
Publication of JPH07230696A publication Critical patent/JPH07230696A/ja
Priority to US08/598,706 priority patent/US5615163A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/80—Masking faults in memories by using spares or by reconfiguring using programmable devices with improved layout
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Dram (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP19884094A 1993-12-21 1994-08-23 半導体記憶装置 Pending JPH07230696A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP19884094A JPH07230696A (ja) 1993-12-21 1994-08-23 半導体記憶装置
US08/360,289 US5517457A (en) 1993-12-21 1994-12-21 Semiconductor memory device
KR1019940036504A KR100192630B1 (ko) 1993-12-21 1994-12-21 반도체 메모리장치
TW084100312A TW307923B (en:Method) 1993-12-21 1995-01-14
US08/598,706 US5615163A (en) 1993-12-21 1996-02-08 Semiconductor memory device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP32158993 1993-12-21
JP5-321589 1993-12-21
JP19884094A JPH07230696A (ja) 1993-12-21 1994-08-23 半導体記憶装置

Publications (1)

Publication Number Publication Date
JPH07230696A true JPH07230696A (ja) 1995-08-29

Family

ID=26511202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19884094A Pending JPH07230696A (ja) 1993-12-21 1994-08-23 半導体記憶装置

Country Status (4)

Country Link
US (2) US5517457A (en:Method)
JP (1) JPH07230696A (en:Method)
KR (1) KR100192630B1 (en:Method)
TW (1) TW307923B (en:Method)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10188580A (ja) * 1996-12-14 1998-07-21 Samsung Electron Co Ltd 不揮発性半導体メモリ装置及びその装置の動作モード制御方法
JP2007294968A (ja) * 2007-04-20 2007-11-08 Toshiba Corp 半導体装置
JP2010027097A (ja) * 2008-07-15 2010-02-04 Toshiba Corp Ｎａｎｄ型フラッシュメモリ

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
JPH08273362A (ja) * 1995-03-30 1996-10-18 Nec Ic Microcomput Syst Ltd 半導体記憶装置
US5687114A (en) 1995-10-06 1997-11-11 Agate Semiconductor, Inc. Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell
KR100205007B1 (ko) * 1995-12-04 1999-06-15 윤종용 멀티-워드라인 드라이버를 갖는 반도체 메모리장치
JP3380107B2 (ja) * 1996-03-22 2003-02-24 シャープ株式会社 半導体記憶装置
US5787097A (en) * 1996-07-22 1998-07-28 Micron Technology, Inc. Output data compression scheme for use in testing IC memories
US5815458A (en) * 1996-09-06 1998-09-29 Micron Technology, Inc. System and method for writing data to memory cells so as to enable faster reads of the data using dual wordline drivers
US5898637A (en) * 1997-01-06 1999-04-27 Micron Technology, Inc. System and method for selecting shorted wordlines of an array having dual wordline drivers
US6487116B2 (en) 1997-03-06 2002-11-26 Silicon Storage Technology, Inc. Precision programming of nonvolatile memory cells
US5870335A (en) 1997-03-06 1999-02-09 Agate Semiconductor, Inc. Precision programming of nonvolatile memory cells
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
US6551857B2 (en) 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
IL124863A (en) * 1998-06-11 2004-05-12 Dsp Group Ltd Dual access memory array
US6407961B1 (en) * 1998-06-11 2002-06-18 Dsp Group, Ltd. Dual access memory array
JP3999900B2 (ja) * 1998-09-10 2007-10-31 株式会社東芝 不揮発性半導体メモリ
US6282145B1 (en) 1999-01-14 2001-08-28 Silicon Storage Technology, Inc. Array architecture and operating methods for digital multilevel nonvolatile memory integrated circuit system
TW475267B (en) * 1999-07-13 2002-02-01 Toshiba Corp Semiconductor memory
KR100331563B1 (ko) * 1999-12-10 2002-04-06 윤종용 낸드형 플래쉬 메모리소자 및 그 구동방법
JP4157269B2 (ja) 2000-06-09 2008-10-01 株式会社東芝 半導体記憶装置
US6396742B1 (en) 2000-07-28 2002-05-28 Silicon Storage Technology, Inc. Testing of multilevel semiconductor memory
AU2003255254A1 (en) 2002-08-08 2004-02-25 Glenn J. Leedy Vertical system integration
JP2005100538A (ja) * 2003-09-25 2005-04-14 Toshiba Corp 不揮発性半導体記憶装置及びこれを用いた電子装置
US7110319B2 (en) * 2004-08-27 2006-09-19 Micron Technology, Inc. Memory devices having reduced coupling noise between wordlines
US8358526B2 (en) * 2008-02-28 2013-01-22 Contour Semiconductor, Inc. Diagonal connection storage array
US20090225621A1 (en) * 2008-03-05 2009-09-10 Shepard Daniel R Split decoder storage array and methods of forming the same
CN102376361B (zh) * 2010-08-09 2016-03-02 上海华虹宏力半导体制造有限公司 具有虚拟接地阵列的快闪存储器
CN104145308B (zh) * 2012-02-29 2017-05-31 松下知识产权经营株式会社 非易失性半导体存储装置
KR102242037B1 (ko) * 2014-04-07 2021-04-21 삼성전자주식회사 불 휘발성 메모리 장치
KR102381046B1 (ko) * 2015-10-26 2022-03-31 에스케이하이닉스 주식회사 비휘발성 메모리 장치
US11521697B2 (en) 2019-01-30 2022-12-06 STMicroelectronics International, N.V. Circuit and method for at speed detection of a word line fault condition in a memory circuit
US11393532B2 (en) 2019-04-24 2022-07-19 Stmicroelectronics International N.V. Circuit and method for at speed detection of a word line fault condition in a memory circuit
KR102810859B1 (ko) 2020-09-16 2025-05-20 삼성전자주식회사 로우 디코더를 포함하는 메모리 장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4658377A (en) * 1984-07-26 1987-04-14 Texas Instruments Incorporated Dynamic memory array with segmented bit lines
JPS61110459A (ja) * 1984-11-02 1986-05-28 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ
JPS6386186A (ja) * 1986-09-30 1988-04-16 Toshiba Corp 半導体記憶装置

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10188580A (ja) * 1996-12-14 1998-07-21 Samsung Electron Co Ltd 不揮発性半導体メモリ装置及びその装置の動作モード制御方法
JP2007294968A (ja) * 2007-04-20 2007-11-08 Toshiba Corp 半導体装置
JP2010027097A (ja) * 2008-07-15 2010-02-04 Toshiba Corp Ｎａｎｄ型フラッシュメモリ
US7952930B2 (en) 2008-07-15 2011-05-31 Kabushiki Kaisha Toshiba NAND flash memory
US8233325B2 (en) 2008-07-15 2012-07-31 Kabushiki Kaisha Toshiba NAND flash memory

Also Published As

Publication number Publication date
TW307923B (en:Method) 1997-06-11
US5615163A (en) 1997-03-25
US5517457A (en) 1996-05-14
KR100192630B1 (ko) 1999-06-15
KR950020745A (ko) 1995-07-24

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