JPH0722121B2 - Semiconductor manufacturing method - Google Patents

Semiconductor manufacturing method

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Publication number
JPH0722121B2
JPH0722121B2 JP59200154A JP20015484A JPH0722121B2 JP H0722121 B2 JPH0722121 B2 JP H0722121B2 JP 59200154 A JP59200154 A JP 59200154A JP 20015484 A JP20015484 A JP 20015484A JP H0722121 B2 JPH0722121 B2 JP H0722121B2
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JP
Japan
Prior art keywords
silicon layer
polycrystalline silicon
thin film
semiconductor layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59200154A
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Japanese (ja)
Other versions
JPS6178119A (en
Inventor
久雄 林
隆 野口
健文 大嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
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Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP59200154A priority Critical patent/JPH0722121B2/en
Publication of JPS6178119A publication Critical patent/JPS6178119A/en
Publication of JPH0722121B2 publication Critical patent/JPH0722121B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体の製造方法に関し、特に、薄膜トラン
ジスタを低温プロセスにて製造する際の能動領域となる
薄膜半導体層を形成するのに好適な半導体の製造方法に
関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a semiconductor, and is particularly suitable for forming a thin film semiconductor layer to be an active region when manufacturing a thin film transistor by a low temperature process. The present invention relates to a semiconductor manufacturing method.

〔従来の技術〕 一般に薄膜トランジスタは、石英ガラス等の絶縁基体上
にSi（シリコン）等の半導体薄膜を被着形成し、この薄
膜半導体層に例えばチャンネルが形成される活性領域や
低抵抗のソース領域、ドレイン領域をそれぞれ形成し
て、FET（電界効果型トランジスタ）を構成するように
している。このような薄膜トランジスタにおいては、薄
膜半導体層の上記活性領域の電気的特性がトランジスタ
の特性を左右するため、特性の良い上記活性領域を得る
ことが極めて重要となっている。[Prior Art] Generally, a thin film transistor is formed by depositing a semiconductor thin film such as Si (silicon) on an insulating substrate such as quartz glass, and an active region in which a channel is formed or a low resistance source region is formed in the thin film semiconductor layer. , And a drain region are formed so as to form an FET (field effect transistor). In such a thin film transistor, since the electrical characteristics of the active region of the thin film semiconductor layer influence the characteristics of the transistor, it is extremely important to obtain the active region having good characteristics.

ところで、薄膜トランジスタの基板としては、従来より
高融点の石英ガラスが一般に用いられているが、材料費
が嵩み高価格となるため、石英ガラスよりは低融点の通
常の耐熱ガラス（例えばいわゆるパイレックス等）を基
板に用いることが望まれている。このような比較的低融
点の耐熱ガラス（軟化点が600℃〜800℃程度）を基板に
用いる場合には、薄膜トランジスタの製造工程中の基板
の上限温度を600℃〜800℃程度以下とするような低温プ
ロセスが必要となる。By the way, as a substrate of a thin film transistor, quartz glass having a high melting point has been generally used, but since the material cost is high and the cost is high, a normal heat-resistant glass having a lower melting point than quartz glass (for example, so-called Pyrex etc. ) Is desirable for the substrate. When using such a relatively low melting point heat resistant glass (softening point of about 600 ℃ ~ 800 ℃) for the substrate, the upper limit temperature of the substrate during the manufacturing process of the thin film transistor should be about 600 ℃ ~ 800 ℃ or less. A low temperature process is required.

しかしながら、このような低温プロセスにおいては、特
性の良好な上記活性領域を得ることは困難である。すな
わち、基板上に例えばCVD法（気相成長法）でSiを被着
形成したのみでは、結晶粒径の小さな多結晶シリコン層
が形成され、電気的特性、特に実効移動度μeff、閾値
電圧Vthの点で良好なものが得られない。次に、上記CVD
法等により被着形成された多結晶シリコン層の少なくと
も上記活性領域となる部分に対して局所的にレーザを照
射して溶融固化することにより結晶性を良くし、特性向
上を図る方法も考えられているが、この場合には固化す
る際の種結晶や成長方向のばらつき等により、再現性が
悪く、均質性、歩留り、リーク等の点で問題が残存して
いる。また、赤外線のハロゲンランプ等を用いたランプ
加熱蒸着法も試みられているが、現在のとろは閾値電圧
Vthが高く、実効移動度μeffが小さく、良好な電気的特
性が得られていないのが実状である。この他、MBD（モ
レキュラー・ビーム・デポジション、分子線成長）法に
よる半導体薄膜成長形成の場合には、良好な特性が得ら
れるものの、装置や製造設備に費用が嵩み、製品のコス
トアップの一因となるのみならず、いわゆるスループッ
トが小さく、製造も困難である。However, in such a low temperature process, it is difficult to obtain the active region having good characteristics. That is, a polycrystalline silicon layer with a small crystal grain size is formed only by depositing Si on the substrate by, for example, the CVD method (vapor phase growth method), and the electrical characteristics, particularly the effective mobility μeff and the threshold voltage Vth It is not possible to obtain a good product. Next, the above CVD
It is also possible to improve the characteristics by locally irradiating a laser on at least the portion of the polycrystalline silicon layer deposited by the method to form the active region and melting and solidifying it to improve the characteristics. However, in this case, the reproducibility is poor due to the seed crystal at the time of solidification, variations in the growth direction, and the like, and problems remain in terms of homogeneity, yield, leakage, and the like. In addition, a lamp heating vapor deposition method using an infrared halogen lamp or the like has been attempted, but the current target is the threshold voltage.
In reality, the Vth is high, the effective mobility μeff is small, and good electrical characteristics are not obtained. In addition, in the case of semiconductor thin film growth formation by the MBD (Molecular Beam Deposition, Molecular Beam Growth) method, although good characteristics can be obtained, the cost of equipment and manufacturing equipment increases and the cost of the product increases. Not only is it a cause, but so-called throughput is small and manufacturing is difficult.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

以上述べたように、薄膜トランジスタを低温プロセスに
て製造しようとすると、得られた薄膜半導体層、さらに
は活性領域となる部分の電気的特性が不充分であり、ま
た良好な特性を得るための方法（例えばMBD法）は装置
が高価で製造が困難でスループットが小さく、製品のコ
ストアップの原因となる。As described above, when a thin film transistor is manufactured by a low temperature process, the electrical characteristics of the obtained thin film semiconductor layer, and further the portion which becomes the active region are insufficient, and a method for obtaining good characteristics is also provided. The MBD method, for example, is expensive in equipment, difficult to manufacture, and has low throughput, which causes an increase in product cost.

本発明は、このような従来の実情に鑑み、比較的簡単な
方法で電気的特性の良好な薄膜半導体層を低温プロセス
で形成し得るような半導体の製造方法の提供を目的とす
る。SUMMARY OF THE INVENTION In view of such conventional circumstances, an object of the present invention is to provide a semiconductor manufacturing method capable of forming a thin film semiconductor layer having good electric characteristics by a low temperature process by a relatively simple method.

〔課題を解決するための手段〕[Means for Solving the Problems]

本発明に係る半導体の製造方法は、上述のような目的を
達成するため、600℃〜800℃の間に軟化点を持つ絶縁基
体上に非晶質又は多結晶の半導体層を形成し、該半導体
層にエキシマレーザから出射される短波長レーザ光を照
射して表面部に種結晶となる結晶粒を成長させた後、熱
処理を施して前記結晶粒を種結晶として固相成長を行わ
せ大粒径の結晶粒からなる多結晶半導体層を形成するも
のである。The method for producing a semiconductor according to the present invention, in order to achieve the above object, to form an amorphous or polycrystalline semiconductor layer on an insulating substrate having a softening point between 600 ℃ ~ 800 ℃, After irradiating the semiconductor layer with short-wavelength laser light emitted from an excimer laser to grow crystal grains as a seed crystal on the surface, heat treatment is performed to perform solid phase growth using the crystal grains as a seed crystal. A polycrystalline semiconductor layer made of crystal grains having a grain size is formed.

〔作用〕[Action]

以上のように、半導体層の表面部に成長核あるいは種と
なる粒径の比較的大きな結晶粒（グレイン）の層を形成
した後に熱処理による固相成長を行わせることで、いわ
ゆる低温プロセスにより最終的に粒径のばらつきが少な
く大径の結晶粒より成る特性の良好な多結晶シリコン層
等の半導体層を、石英より低融点の一般の耐熱ガラス板
等の絶縁基体上に形成することができる。As described above, solid phase growth is performed by heat treatment after forming a layer of crystal grains (grains) having a relatively large grain size as growth nuclei or seeds on the surface of the semiconductor layer. It is possible to form a semiconductor layer such as a polycrystalline silicon layer, which has good characteristics and is composed of large-sized crystal grains with little variation in grain size, on an insulating substrate such as a general heat-resistant glass plate having a melting point lower than that of quartz. .

〔実施例〕〔Example〕

以下、本発明の半導体の製造方法を薄膜トランジスタの
製造工程に適用した一実施例について、図面を参照しな
がら説明する。An embodiment in which the semiconductor manufacturing method of the present invention is applied to a thin film transistor manufacturing process will be described below with reference to the drawings.

先ず、第１図において、石英よりも低融点の耐熱ガラス
（例えばいわゆるパイレックス等）の基板１上に膜厚が
1000Å程度のSiO2絶縁膜２を被着形成して成る絶縁基体
上には、多結晶シリコン層３がCVD法（気相成長法）等
により例えば1000Å程度の厚みに被着形成されている。First, in FIG. 1, the film thickness is formed on a substrate 1 of heat-resistant glass (eg, so-called Pyrex) having a melting point lower than that of quartz.
On the insulating substrate formed by depositing the SiO 2 insulating film 2 of about 1000 Å, a polycrystalline silicon layer 3 is deposited by CVD (vapor phase growth method) or the like to a thickness of about 1000 Å, for example.

この多結晶シリコン層３の表面に、エキシマレーザ（Kr
−F,Ar−Ｆ等）から出射される例えば波長が2000Å〜30
00Åの短波長のレーザ光を照射して表面近傍のみをアニ
ール処理する。そして、多結晶シリコン層３の表面近傍
に、第２図に示すように、粒径の比較的な結晶粒である
グレイン５を形成する。The excimer laser (Kr
-F, Ar-F, etc.), for example, the wavelength is 2000 Å ~ 30
Laser light with a short wavelength of 00Å is irradiated to anneal only the vicinity of the surface. Then, in the vicinity of the surface of the polycrystalline silicon layer 3, as shown in FIG. 2, grains 5 which are crystal grains having comparative grain sizes are formed.

なお、多結晶シリコン層３の膜厚が例えば5000Å程度と
比較的厚い場合には、Ar（アルゴン）レーザあるいはレ
ーザ以外のハロゲンランプ等で多結晶シリコン層３を加
熱し、粒径の比較的大きなグレイン５を形成するように
してもよい。このとき、下部の低融点耐熱ガラス基板１
が損傷したり熱による変形を生じないようにすることは
勿論である。また、レーザによるアニール時には、一般
に表面にSiO2膜等を被着形成（いわゆるキャッピング）
している。When the thickness of the polycrystalline silicon layer 3 is relatively thick, for example, about 5000 Å, the polycrystalline silicon layer 3 is heated by an Ar (argon) laser or a halogen lamp other than the laser to have a relatively large grain size. The grain 5 may be formed. At this time, the lower low melting point heat resistant glass substrate 1
Of course, it should not be damaged or deformed by heat. During laser annealing, a SiO 2 film is generally deposited on the surface (so-called capping).
are doing.

次に、イオン注入法により多結晶シリコン層３の表面よ
り例えばSi+（シリコンイオン）を打ち込むことによっ
て、上記粒径の大きくされたグレイン５の層の下部領域
をアモルファス（非晶質）化し、第３図に示すような非
晶質シリコン層６を形成する。これは、イオン注入され
たSi+は、表面から所定の打ち込み深さ、いわゆる投射
飛程RPを中心として統計的な変動幅をもって分布するこ
とより、表面近傍の大粒径のグレイン５の層はアモルフ
ァス化されず、下部領域のみがアモルファス化される。Next, by implanting, for example, Si + (silicon ions) from the surface of the polycrystalline silicon layer 3 by the ion implantation method, the lower region of the grain 5 layer with the increased grain size is made amorphous. An amorphous silicon layer 6 as shown in FIG. 3 is formed. This is because the ion-implanted Si + is distributed with a statistical fluctuation range around a predetermined implantation depth from the surface, the so-called projected range R P , so that the layer of grains 5 of large grain size near the surface is formed. Is not amorphized, but only the lower region is amorphized.

このときのSi+イオン注入条件としては、例れば多結晶
シリコン層３の膜厚が1000Å程度のとき、打ち込みエネ
ルギを50〜60keVとして投射飛程RPを700〜800Åとし、
打ち込みドーズ量を１×1515cm-2程度とする。また、多
結晶シリコン層３の膜厚がさらに厚い場合には、上記打
ち込みエネルギを高めればよい。As the Si + ion implantation conditions at this time, for example, when the thickness of the polycrystalline silicon layer 3 is about 1000 Å, the implantation energy is 50 to 60 keV and the projection range R P is 700 to 800 Å,
The implantation dose is set to about 1 × 15 15 cm -2 . If the polycrystalline silicon layer 3 is thicker, the implantation energy may be increased.

次に、例えば600℃で15時間程度の加熱処理（アニール
処理）をN2（窒素）ガス中で施すことにより、上記大粒
のグレイン５を成長核あるいは種として非晶質シリコン
層６に対していわゆる固相成長を行わせ、第４図に示す
ように、シリコン層７の全体の厚みにわたって大粒径
（例えば粒径が約1000Å程度以上）の結晶粒を成長させ
て多結晶シリコン層７を形成する。このようにして得ら
れた多結晶シリコン層７は、粒径が大きいのみならず、
ばらつきの少ない均質なものとなっており、高特性が得
られることは勿論のこと、再現性が良く、歩留りも少な
い。Next, for example, a heat treatment (annealing treatment) at 600 ° C. for about 15 hours is performed in N 2 (nitrogen) gas, and the large grains 5 are used as growth nuclei or seeds on the amorphous silicon layer 6. So-called solid phase growth is performed, and as shown in FIG. 4, the polycrystalline silicon layer 7 is grown by growing crystal grains having a large grain size (for example, a grain size of about 1000Å or more) over the entire thickness of the silicon layer 7. Form. The polycrystalline silicon layer 7 thus obtained not only has a large grain size,
It is uniform with little variation, and not only high characteristics are obtained, but also reproducibility is good and yield is low.

ところで、一般の薄膜トランジスタの能動領域となる半
導体層、例えば多結晶シリコン層の膜厚は、最小でも15
00Å以上、通常は3000Å以上となっており、上記多結晶
シリコン層７の厚みを予めこの程度の膜厚に形成してお
くことで、第４図の工程が終了した段階の多結晶シリコ
ン層７をそのまま能動領域に用いた通常の薄膜トランジ
スタを構成することも可能である。By the way, the thickness of a semiconductor layer, which is an active region of a general thin film transistor, for example, a polycrystalline silicon layer, is at least 15
The thickness is 00 Å or more, usually 3000 Å or more. By forming the polycrystalline silicon layer 7 to have such a thickness in advance, the polycrystalline silicon layer 7 at the stage when the process of FIG. 4 is completed is completed. It is also possible to form a normal thin film transistor using the above as it is in the active region.

これに対して、本件発明者は、先に、上記能動領域とな
る半導体層の膜厚を1000Å以下としたとき、200Å〜300
Å程度のところで良好な電気的特性、特に、大きな実効
移動度μeffが得られることを見出し、このような膜厚
が数百Å程度の超薄膜シリコン層を能動領域とする薄膜
トランジスタを既に提案している。以下、この超薄膜ト
ランジスタを製造するための工程について説明する。On the other hand, the inventor of the present invention, when the film thickness of the semiconductor layer serving as the active region is set to 1000 Å or less, 200 Å to 300 Å
We found that good electrical characteristics, especially large effective mobility μeff, can be obtained at about Å, and we have already proposed a thin film transistor using such a thin film silicon layer with a thickness of about several hundred Å as the active region. There is. Hereinafter, a process for manufacturing this super thin film transistor will be described.

すなわち、第４図に示す固相成長工程が終了した多結晶
シリコン層７に対し、表面を液温が例えば170℃程度の
燐酸（H3PO4）にてエッチング処理することにより、膜
厚を薄くし、第５図に示すように、膜厚が例えば200Å
〜300Å程度の薄膜多結晶シリコン層７を形成する。な
お、上述した超薄膜トランジスタを形成するための多結
晶シリコン層７の膜厚としては、20Å〜1000Åが好まし
く、より好ましくは100Å〜750Å、さらに好ましくは20
0Å〜500Åである。That is, the film thickness of the polycrystalline silicon layer 7 after the solid phase growth step shown in FIG. 4 is etched by phosphoric acid (H 3 PO 4 ) having a liquid temperature of about 170 ° C. As shown in Fig. 5, reduce the film thickness to 200Å
A thin film polycrystalline silicon layer 7 of about 300 Å is formed. The thickness of the polycrystalline silicon layer 7 for forming the above-mentioned super thin film transistor is preferably 20Å to 1000Å, more preferably 100Å to 750Å, and further preferably 20Å to 750Å.
It is between 0Å and 500Å.

また、上記エッチングによる薄膜化の際のエッチング液
としては、液温が160℃以上の燐酸がエッチングの安定
性、エッチングレート（２〜３Å／分）等の点で優れて
お、数百Å程度の超薄膜を得るための膜厚制御に好適な
ものである。なお、エッチング液となる燐酸の液温のよ
り好ましい範囲は、170℃〜180℃である。In addition, phosphoric acid having a liquid temperature of 160 ° C or higher is excellent as an etching solution for forming a thin film by the above etching, in terms of etching stability, etching rate (2 to 3Å / min), etc. It is suitable for controlling the film thickness to obtain the ultra thin film. The more preferable range of the temperature of phosphoric acid serving as the etching solution is 170 ° C to 180 ° C.

次に、必要に応じて水素化処理を施すことにより、グレ
インバウンダリ（粒界）に生じているトラップを減少さ
せて特性向上を図る。この水素化処理は、例えば炉中に
水素ガスを導入しながら400℃程度でアニール（加熱）
することにより、あるいは水素を含むプラズマSiN（窒
化シリコン）膜を全面に被着形成（いわゆるキャッピン
グ）した状態でアニールすることにより行えばよく、こ
の他、水素プラズマアニール法やこれらを組み合せた方
法で行ってもよい。Next, if necessary, hydrogenation treatment is performed to reduce traps generated at the grain boundaries (grain boundaries) to improve the characteristics. This hydrogenation treatment is, for example, annealing (heating) at about 400 ° C. while introducing hydrogen gas into the furnace.
Or by annealing with a plasma SiN (silicon nitride) film containing hydrogen deposited over the entire surface (so-called capping). In addition to this, a hydrogen plasma annealing method or a combination of these methods may be used. You can go.

なお、この水素化処理は、上記第４図の工程が終了した
段階で行ってもよいが、第５図のような超薄膜とした後
に水素化処理を行うことで最良の特性、例えば実効移動
度μeffが100cm2/Vsec以上、閾値電圧Vthが5V以下のよ
うな極めて優れた特性を得ることも可能となる。This hydrogenation treatment may be carried out at the stage where the process shown in FIG. 4 is finished, but the best characteristics, for example effective transfer, can be obtained by performing the hydrogenation treatment after forming the ultrathin film as shown in FIG. It is also possible to obtain extremely excellent characteristics such that the degree μeff is 100 cm 2 / Vsec or more and the threshold voltage Vth is 5 V or less.

以上のようにして薄膜化された水素化処理の施された第
５図に示す上記超薄膜（膜厚が例えば200Å〜300Å）の
多結晶シリコン層７を用いて薄膜トランジスタを構成す
るには、従来と同様な製造工程に従えばよい。すなわ
ち、第５図の多結晶シリコン層７に対して、必要とする
薄膜トランジスタの能動領域形状を形成するためのパタ
ーンエッチング処理を施した後、第６図に示すように、
ゲート絶縁膜となるSiO2膜11を例えばCVD法（気相成長
法）等により被着形成し、このSiO2膜11上にゲート電極
や配線電極となる低抵抗の不純物ドープ多結晶シリコン
層12をCVD法等により被着形成する。In order to form a thin film transistor by using the above-mentioned ultrathin polycrystalline silicon layer 7 (thickness is, for example, 200Å to 300Å) shown in FIG. The manufacturing process similar to the above may be followed. That is, after subjecting the polycrystalline silicon layer 7 of FIG. 5 to a pattern etching process for forming a required active region shape of a thin film transistor, as shown in FIG.
A SiO 2 film 11 to be a gate insulating film is formed by, for example, a CVD method (vapor phase growth method) or the like, and a low resistance impurity-doped polycrystalline silicon layer 12 to be a gate electrode or a wiring electrode is formed on the SiO 2 film 11. Are deposited by the CVD method or the like.

次に、これらのSiO2膜11および不純物ドープ多結晶シリ
コン層12をパターンエッチングして、第７図に示すよう
に、ゲート絶縁膜11Gおよびゲート電極12Gを形成する。
次に、これらのゲート絶縁膜11Gおよびゲート電極12Gを
拡散マスクとするいわゆるセルフアライン法等により、
多結晶シリコン層７に不純物を拡散し、低抵抗のソース
領域7Sおよびドレイン領域7Dを形成する。これらのソー
ス領域7Sとドレイン領域7Dとの間のゲート下部領域は、
トランジスタ素子の動作中にチャンネル形成されるいわ
ゆる活性領域7Aとなる。さらに、これらの各領域が形成
された多結晶シリコン層７およびゲート電極12G上に絶
縁膜として例えばPSG（燐シリケートガラス）膜13を被
着形成し、上記各ソース領域7Sおよびドレイン領域7Dの
上部のPSG膜13にコンタクト用の窓部14Sおよび14Dをそ
れぞれ開設した後、電極となるAl（アルミニウム）層を
被着形成したパターニングして、ソース電極15Sおよび
ドレイ電極15Dをそれぞれ形成することにより、薄膜ト
ランジスタを製造すればよい。Next, the SiO 2 film 11 and the impurity-doped polycrystalline silicon layer 12 are pattern-etched to form a gate insulating film 11G and a gate electrode 12G as shown in FIG.
Next, by a so-called self-alignment method using these gate insulating film 11G and gate electrode 12G as a diffusion mask,
Impurities are diffused into the polycrystalline silicon layer 7 to form low-resistance source regions 7S and drain regions 7D. The lower region of the gate between these source region 7S and drain region 7D is
This becomes a so-called active region 7A in which a channel is formed during the operation of the transistor element. Further, for example, a PSG (phosphorus silicate glass) film 13 is deposited as an insulating film on the polycrystalline silicon layer 7 and the gate electrode 12G in which these respective regions are formed, and the upper part of each of the source region 7S and the drain region 7D is formed. After opening the contact windows 14S and 14D in the PSG film 13 respectively, the Al (aluminum) layer to be an electrode is deposited and patterned to form the source electrode 15S and the drain electrode 15D, respectively. A thin film transistor may be manufactured.

なお、本発明は上記実施例のみに限定されるものではな
く、例えば、上記第１図の短波長レーザによる表面部の
みの熱処理工程と、第２図のイオン注入によるアモルフ
ァス化（非晶質化）工程との順序を逆としてもよい。ま
た、最初に被着形成する多結晶シリコン層３の代りに、
非晶質シリコン層を被着形成してもよい。The present invention is not limited to the above embodiment, and for example, the heat treatment step of only the surface portion by the short wavelength laser of FIG. 1 and the amorphization (amorphization by the ion implantation) of FIG. ) The order of the steps may be reversed. Further, instead of the polycrystalline silicon layer 3 to be deposited first,
An amorphous silicon layer may be deposited.

〔発明の効果〕〔The invention's effect〕

以上の説明からも明らかなように、多結晶シリコン層等
の半導体層の表面に短波長レーザを照射して表面部にの
み粒径の比較的大きなグレインを有する層を形成してお
き、このグレインを成長核あるいは種として比較的低温
（例えば600℃程度）のアニール処理を施していわゆる
固相成長を行わせることにより、ガラス基板等の絶縁基
体の温度を比較的低温（例えば600℃〜800℃以下）に保
ったまま、粒径が大きく特性の良好な多結晶シリコン層
等の半導体層を得ることができる。したがって、石英に
比べて安価の低融点の耐熱ガラス（例えば軟化点が600
℃〜800℃程度）を基板として用いて、いわゆる低温プ
ロセスにより、均質しで再現性が良く歩留りが良く特性
も良好な多結晶シリコン層等の半導体層を得ることがで
き、さらには、例えば実効移動度μeffが100cm2/V・sec
程度以上で閾値電圧Vthが5V程度以下のような極めて高
い特性の半導体層を得ることも可能となる。As is apparent from the above description, the surface of a semiconductor layer such as a polycrystalline silicon layer is irradiated with a short-wavelength laser to form a layer having a relatively large grain size only on the surface portion. By subjecting the insulating substrate such as a glass substrate to a relatively low temperature (for example, 600 ° C to 800 ° C) by performing so-called solid-phase growth by performing an annealing treatment at a relatively low temperature (for example, about 600 ° C) as a growth nucleus or seed. A semiconductor layer such as a polycrystalline silicon layer having a large grain size and good characteristics can be obtained while keeping the following. Therefore, it is cheaper than quartz and has a low melting point (for example, a softening point of 600
℃ ~ 800 ℃) as a substrate, by a so-called low temperature process, it is possible to obtain a semiconductor layer such as a polycrystalline silicon layer that is homogenous, has good reproducibility, good yield, and good characteristics. Mobility μeff is 100 cm 2 / Vsec
It is also possible to obtain a semiconductor layer having extremely high characteristics such that the threshold voltage Vth is about 5 V or less at about the above level.

【図面の簡単な説明】[Brief description of drawings]

第１図ないし第７図は本発明を薄膜トランジスタの製造
方法に適用した一実施例を示す製造工程に従った概略断
面図である。 １……基板 ２……SiO2絶縁膜 3,7……多結晶シリコン層 ５……グレイン ６……非晶質シリコン層1 to 7 are schematic cross-sectional views according to a manufacturing process showing an embodiment in which the present invention is applied to a method of manufacturing a thin film transistor. 1 ... Substrate 2 ... SiO 2 insulating film 3, 7 ... Polycrystalline silicon layer 5 ... Grain 6 ... Amorphous silicon layer

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭57−134924（ＪＰ，Ａ) 特開 昭57−155726（ＪＰ，Ａ) 特公 昭49−47630（ＪＰ，Ｂ１) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-134924 (JP, A) JP-A-57-155726 (JP, A) JP-B-49-47630 (JP, B1)

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】600℃〜800℃の間に軟化点を持つ絶縁基体
上に非晶質又は多結晶の半導体層を形成し、該半導体層
にエキシマレーザから出射される短波長レーザ光を照射
して表面部に種結晶となる結晶粒を成長させた後、熱処
理を施して前記結晶粒を種結晶として固相成長を行わせ
大粒径の結晶粒からなる多結晶半導体層を形成すること
を特徴とする半導体の製造方法。1. An amorphous or polycrystalline semiconductor layer is formed on an insulating substrate having a softening point between 600 ° C. and 800 ° C., and the semiconductor layer is irradiated with short-wavelength laser light emitted from an excimer laser. And growing a crystal grain to be a seed crystal on the surface portion, and then performing a heat treatment to perform solid phase growth using the crystal grain as a seed crystal to form a polycrystalline semiconductor layer made of large-grain crystal grains. And a method for manufacturing a semiconductor.
JP59200154A 1984-09-25 1984-09-25 Semiconductor manufacturing method Expired - Lifetime JPH0722121B2 (en)

Priority Applications (1)

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JP59200154A JPH0722121B2 (en) 1984-09-25 1984-09-25 Semiconductor manufacturing method

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Application Number Priority Date Filing Date Title
JP59200154A JPH0722121B2 (en) 1984-09-25 1984-09-25 Semiconductor manufacturing method

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JPS6178119A JPS6178119A (en) 1986-04-21
JPH0722121B2 true JPH0722121B2 (en) 1995-03-08

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JPS62266819A (en) * 1986-05-14 1987-11-19 Sony Corp Formation of semiconductor thin film
JPS62287614A (en) * 1986-06-06 1987-12-14 Sony Corp Formation of polycrystalline silicon film
JP2565684B2 (en) * 1986-06-12 1996-12-18 株式会社リコー Method for manufacturing polycrystalline silicon thin film
JPS6321818A (en) * 1986-07-15 1988-01-29 Sony Corp Treating method for semiconductor thin film
JP2695488B2 (en) * 1989-10-09 1997-12-24 キヤノン株式会社 Crystal growth method
DE4114162A1 (en) * 1990-05-02 1991-11-07 Nippon Sheet Glass Co Ltd METHOD FOR PRODUCING A POLYCRYSTALLINE SEMICONDUCTOR FILM
US6008078A (en) 1990-07-24 1999-12-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US5254208A (en) * 1990-07-24 1993-10-19 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
JP2923700B2 (en) 1991-03-27 1999-07-26 株式会社半導体エネルギー研究所 Semiconductor device and manufacturing method thereof
US5372836A (en) * 1992-03-27 1994-12-13 Tokyo Electron Limited Method of forming polycrystalling silicon film in process of manufacturing LCD
SG46344A1 (en) * 1992-11-16 1998-02-20 Tokyo Electron Ltd Method and apparatus for manufacturing a liquid crystal display substrate and apparatus and method for evaluating semiconductor crystals
JP3141909B2 (en) * 1993-05-14 2001-03-07 株式会社半導体エネルギー研究所 Semiconductor device manufacturing method
US6867432B1 (en) 1994-06-09 2005-03-15 Semiconductor Energy Lab Semiconductor device having SiOxNy gate insulating film
TW303526B (en) * 1994-12-27 1997-04-21 Matsushita Electric Ind Co Ltd
KR100269289B1 (en) * 1997-02-19 2000-10-16 윤종용 Method for crystallizing a silicon film
JP2006191125A (en) * 2006-01-27 2006-07-20 Ftl:Kk Manufacturing method for soi wafer

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US3763532A (en) * 1972-06-05 1973-10-09 Dayco Corp Drafting roller construction
JPS57134924A (en) * 1981-02-16 1982-08-20 Toshiba Corp Production of semiconductive single-crystal thin film
JPS57155726A (en) * 1981-03-20 1982-09-25 Fujitsu Ltd Manufacture of semiconductor device

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