TW303526B - - Google Patents

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TW303526B
TW303526B TW084113578A TW84113578A TW303526B TW 303526 B TW303526 B TW 303526B TW 084113578 A TW084113578 A TW 084113578A TW 84113578 A TW84113578 A TW 84113578A TW 303526 B TW303526 B TW 303526B
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Taiwan
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thin film
forming
microcrystalline
layer
polycrystalline
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TW084113578A
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Chinese (zh)
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Matsushita Electric Ind Co Ltd
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Priority claimed from JP6325177A external-priority patent/JPH08181069A/en
Priority claimed from JP7003631A external-priority patent/JPH08195492A/en
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Publication of TW303526B publication Critical patent/TW303526B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B65—CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65B—MACHINES, APPARATUS OR DEVICES FOR, OR METHODS OF, PACKAGING ARTICLES OR MATERIALS; UNPACKING
    • B65B7/00—Closing containers or receptacles after filling
    • B65B7/02—Closing containers or receptacles deformed by, or taking-up shape, of, contents, e.g. bags, sacks
    • B65B7/06—Closing containers or receptacles deformed by, or taking-up shape, of, contents, e.g. bags, sacks by collapsing mouth portion, e.g. to form a single flap
    • B65B7/08—Closing containers or receptacles deformed by, or taking-up shape, of, contents, e.g. bags, sacks by collapsing mouth portion, e.g. to form a single flap and folding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02686—Pulsed laser beam
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/903—Dendrite or web or cage technique
    • Y10S117/904—Laser beam
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/09—Laser anneal

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mechanical Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)

Description

A7 元晶等元 II電程體 導膜製導 半薄等半 膜之 Μ 膜 薄用 Α 薄 及置 R 之 法裝 S 作 方示或製 成顯，所 形晶}其 之液or用 膜於ns使 薄用se及 1 晶使 e 法 域結關ag方 領多有im成 }術關係 {形 1技有，器之 (1之係之感膜 明屬明言傳薄 説所發詳像晶 明明本更Effl結 。 發發 ，，多者 L't 件體之件 308526 【先行技術】 近年，對於液晶罈示裝置，要求更趨於大畫面化，高 精緻化等更形殷切。爲了滿足此種要求，使用於液晶顯示 裝置之薄膜電晶體（TFT)需要更加之高性能化。 現在，使用於液晶顯示裝置之T F T爲靥於非晶質 TFT。另一方面，多結晶矽TFT係其元件性能較非晶 質矽TFT爲優，又，具有在液晶顯示裝置基板上可將驅 動電路形成爲一體等之益處。因此，已逐漸進行多結晶多 T F T之開發。 欲實用化多結晶矽T F T，則形成高品質之多結晶構 造之技術變成不可或缺。若依據比較在高溫形成多結晶薄 膜之技術，其可使用之基板爲被限制於石英基板。與此相 較，可使用低應變點之低廉玻璃基板之低溫（約6 0 0 °C 以下）形成薄膜之技術愈盛行。尤其對於基板之熱損害小 ，將非晶質薄膜加以熔化結晶化而可獲得高品質多結晶薄 膜之準分子雷射退火被視爲最具有厚望者。 茲就習知之多結晶薄膜之形成方法，尤其使用準分子 本紙張尺度適用中國國家標準（CNS > A4规格（210X297公釐） ---------A ^-------tT------^ (請先閩讀背面之注意事項再填寫本頁) 經濟部中央標準局貝工消费合作社印裝 經濟部中央揉準局属工消费合作社印裝 A7 B7 五、發明説明（2 ) 雷射退火時之多結晶矽薄膜之形成方法爲例說明如下。 圇9係表示使用準分子雷射退火之多結晶矽薄膜之形 成工程之模式圖。如圇9所示，將縱横寬度整形爲約爲5 〜1 Omm之剖面形狀之雷射光束對於基板1做相對移動 ，而照射於非晶質矽層3全面。此際，因準分子雷射係靥 於脈衝狀雷射，所以，對於已照射領域局部性地重叠照射 使其不殘留未照射領域。形成爲如此之多結晶矽薄膜5之 中，使用雷射光束之能量密度小之遴緣周邊部所照射之領 域5 a係較其他領域，將變成其結晶性大爲相異者。因此 ，使用此多結晶矽薄膜5形成多數TFT陣列時，各 T F T之裝®特性係依據T F T形成於T F T之那一位置 ，做周期性之變動。 邊參照圖1 0 ( a )〜（C )，說明使用準分子雷射 退火之多結晶矽薄膜之形成方法之習知例。 首先，如圖1 0 (a) 所示，第1步驟之退火，係 對於基板1上之非晶質矽層3 ，照射約2 7 OmJ / ( cm2〉之能量密度之雷射光束1。此結果，形成了含有 平均粒徑爲5 0 nm程度結晶粒之矽層2。 茲就如圖10 (b)所示，第2步驟之退火，係對於 矽層2 ，照射約4 5 OmJ / ( cm2)能量密度之雷射 光束1。其結果，即可獲得具有如圖1 0 ( c )所示結晶 構造之多結晶矽薄膜5。此第2步驟之退火，係可提升在 第1步驟之退火所產生之結晶性之比較不良領域（比周園 其結晶粒徑小之領域）之結晶性，而使多結晶矽薄膜5之 本紙诛尺度適用中國國家揉準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 装· 訂- 經濟部中央標準局貝工消费合作社印製 〇08S26 A7 B7 五、發明説明（3 ) 均匀性變成良好。 在此習知例，進行具有相異能量密度之雷射光束照射 矽層二次之^2步驟退火」。以後，將雷射光束對於基板 做相對性移動，而將欲形成多結晶矽薄膜之領域照射一遍 之過程算做一個步驟。 關於使用上述2步驟退火之多結晶薄膜之形成方法， 係例如刊載其報告於Extended Abstracts of the 1992 International Conference on Solid State Devices and Material B-l-4 ( 1992) P.55-57 ) 0 邊參照圖11 (a)〜（b)，說明使用準分子雷射 退火之多結晶矽薄膜之其他形成方法如下。 在本例，係如圊1 1 (a) 所示，對於加熱至約 4 0 0 °C之基板1上之非晶質矽層2，實施約3 0 OmJ / c m2能量密度之準分子雷射之退火。於基板加熱狀態 ，係與非加熱狀態比較，其凝固速度變小而促進其結晶粒 之成長。又，若是非加熱狀態之退火時，溫度不到熔化點 而沒有熔化之領域，也只將進行基板加熱分置提高其薄膜 溫度，而變成達到熔點之熔化狀態。因此，由於整個雷射 光束照射領域經由熔化結晶化之過程，如圖1 1 ( b )所 示，多結晶矽薄膜之結晶均匀性將變成良好。 雖然也有以非加熱狀態提高雷射光束之能置密度來熔 化整個照射領域之方法，但是，由於發生薄膜之磨蝕頻次 會變高，所以不太使用此方法。 在這種基板加熱狀態，實施準分子雷射退火形成多結 本紙張又度適用中國國家揉準（CNS ) A4说格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 f 經濟部中央樣準局貝工消费合作杜印製 A7 _____B7_^_ 五、發明説明（4 ) 晶薄膜之方法，係例如報告刊載於I · E . D .Μ T e chnical Digest ( 1991 年）從第 5 6 3 頁到第 5 6 6 頁 (I，E，D.M Tech· Digest(1991年） Ρ· 563 — 566) 0 像這樣，使用所獲得之多結晶矽薄膜形成TFT時， 則TFT之移動度之面內不勻，將可抑制在±10%。這 種T F T製造方法，係例如其報告刊載於Extended Abstracts of the 1991 International Conference ο n S o 1 id State Devices and Materials ( 1991)第 6 2 3 頁到第 6 2 5 頁）。 【發明所欲解決之問題】 但是，習知例之方法有如下之問題。 2步驟退火時，於第1步驟之退火係在雷射光束1之 剖面之邊緣周邊部尤其結晶化閾値附近之能量密度之部分 所照射之領域，係與平均結晶粒徑爲約5 0 n m周圍做比 較形成平均結晶粒徑小之結晶領域，所以接著重叠領域照 射時或第2步驟之退火也有了若干之結晶粒徑之擴大或結 晶缺陷降低等。因此將經過非晶質S i之熔化結晶化之多 結晶S丨頜域之結晶性能之差異仍然很大。 又，邊進行基板加熱，欲進行雷射退火時，與周圍做 比較即使其平均結晶粒徑小之結晶領域也會發生熔化結晶 化，但是，在從非晶質變化爲多結晶之情形，與上述平均 結晶粒徑從小結晶狀態變化爲多結晶之情形時，其結晶化 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ----------^ ^-----.—、玎—·-----' (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標率局系工消费合作社印袈 s〇SS26 A7 B7 五、發明説明（5 ) 所需之能纛爲相異，而;所生成之結晶化也會發生差異。 像這樣，若依據上述習知技術，由於多結晶矽薄膜之 結晶性爲沿著基板之面方向不均句’所以，若使用這種多 結晶矽薄膜形成TFT陣列時，具有TFT之裝置特性之 面內不勻不能降低到充分位準之問題。尤其，在液晶顯示 裝置之顯示部形成TFT陣列時，由於移動度之相對性低 之TFT存在，在畫面上出現格子狀之顯示不勻，而發生 顯示品質會降低之不妥情形。 本發明係解決上述問題所爲者，其目的係提供一種形 成儍於結晶性之面內均匀性之多結晶矽薄膜之方法，而提 供製造特性之面內不勻小之薄膜電晶體之方法。 【解決問題之手段】 本發明之多結晶薄膜之形成方法係包含有，包含一部 分將做爲多結晶化所需之結晶核發揮其功能之微結晶之薄 膜形成於絕緣性基板上之製程，與將該薄膜使用雷射退火 進行多結晶化之製程，藉此就可達成上述目的。 某資施形態係，於上述結晶化製程前之上述薄膜，係 包含有：包含上述微結晶層，與接觸於該微結晶層之非晶 質層。 於上述多結晶化製程前之上述薄膜，也可包含：包含 上述微結晶之微結晶層，與堆積於微結晶層上之上述非晶 質厝。 上述多結晶化製程前之上述薄膜，也可包含：非晶質 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂 Λ ! 經濟部中央橾準局員工消费合作社印製 A7 B7 五、發明説明（6 ) 層，與堆稹於該非晶質屠上，而包含上述微結晶之微結晶 層0 上述薄膜也再可包含堆稹於該微結晶層上之其他非晶 質層。 上述微結晶層也可使用CVD法形成。 在較佳實施形態，上述雷射退火，係使用準分子雷射 進行。 在某實施形態，上述雷射退火係，將上述絕綠性基板 邊維持於約2 0 0 °C到6 0 0 °C之溫度範園內進行。 在某資施形態，上述薄膜係，由以矽或鍺做爲主成分 之半導镰材料所形成。 上述微結晶層之微結晶之平均結晶粒徑係2 0 n m以 下之申請專利範圍第1項到第5項任一項之多結晶薄膜之 形成方法。 形成上述薄膜之製程係，也可包含：形成非晶質層之 製程，與使用具有結晶化閾値附近之能置密度之雷射光束 來退火該非晶質層，藉此形成上述微結晶核之製程。 某實施形態，形成上述微結晶層之製程係，包含有： 形成非晶質層之製程，與使用具有結晶化閾値附近之能量 密度之雷射光束來退火該非晶質層，藉此，將非晶質層變 換爲上述微結晶層之製程。 本發明之薄膜電晶體之製造方法，係包含有：包含有 將做爲多結晶化所需之結晶核發揮其功能之微結晶之一部 分之半導體薄膜形成於絕緣性基板上之製程，與將該半導 本紙張尺度適用中國困家梯準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)A7 Element crystal and other element II electrical conductor film guides the semi-thin and half-membrane film. The M film is thinned by the method of A thin and R set. In ns use thin and se and 1 crystal to make e domain close customs ag square leader has more im formation} art relationship {form 1 technology has and implements (1 series of sense film is clearly stated in the plain language and the thin version is like Jing Mingming This is the Effl knot. It is published that, many of them are L't pieces. 308526 [Advanced technology] In recent years, for LCD display devices, the demand for large screens and high refinement has become more ardent. In order to meet this Thin film transistors (TFTs) used in liquid crystal display devices require higher performance. Now, the TFTs used in liquid crystal display devices are amorphous TFTs. On the other hand, polycrystalline silicon TFTs are their components The performance is better than that of amorphous silicon TFT, and it has the advantage that the driving circuit can be integrated on the substrate of the liquid crystal display device. Therefore, the development of polycrystalline and multi-TFT has been gradually carried out. The technique of forming a high-quality polycrystalline structure becomes indispensable. According to the technology of forming polycrystalline thin films at high temperatures, the substrates that can be used are limited to quartz substrates. Compared with this, low-strain point inexpensive glass substrates can be used at low temperatures (approximately 600 ° C) Thin film technology is more prevalent. Especially for substrates with low thermal damage, the excimer laser annealing of an amorphous thin film by melting and crystallization to obtain a high-quality polycrystalline thin film is considered to be the most promising. The method of forming crystalline thin film, especially using the excimer, the paper size is applicable to the Chinese national standard (CNS> A4 specification (210X297 mm) --------- A ^ ------- tT --- --- ^ (Please read the precautions on the back before filling in this page) Printed and printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed and printed by A7 B7 of the Workers and Consumers Cooperative of the Central Kneading and Quarantine Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) The method of forming a polycrystalline silicon film during laser annealing is explained as an example as follows. Fig. 9 is a model diagram showing the formation process of a polycrystalline silicon film using excimer laser annealing. As shown in Fig. 9, the vertical and horizontal widths are shaped as About 5 ~ 1 Omm cross-sectional shape The laser beam moves relative to the substrate 1 and irradiates the entire amorphous silicon layer 3. At this time, the excimer laser is a pulsed laser, so the local irradiation of the irradiated area overlaps locally. It does not leave unirradiated areas. In such a polycrystalline silicon film 5, the area irradiated by the periphery of the edge with a small energy density using a laser beam 5a is more crystalline than other areas. The difference. Therefore, when using this polycrystalline silicon thin film 5 to form a large number of TFT arrays, the characteristics of each TFT device are periodically changed according to the position where the TFT is formed in the TFT. With reference to FIGS. 10 (a) to (C), a conventional example of a method for forming a polycrystalline silicon thin film using excimer laser annealing will be described. First, as shown in FIG. 10 (a), the annealing in the first step is to irradiate the amorphous silicon layer 3 on the substrate 1 with a laser beam 1 having an energy density of about 2 7 OmJ / (cm2>. This As a result, a silicon layer 2 containing crystal grains with an average particle size of about 50 nm is formed. Here, as shown in FIG. 10 (b), the annealing in the second step is for the silicon layer 2 to be irradiated by about 4 5 OmJ / ( cm2) Energy density of the laser beam 1. As a result, a polycrystalline silicon thin film 5 having a crystal structure as shown in FIG. 10 (c) can be obtained. This annealing in the second step can be improved in the first step The crystallinity of annealing is relatively poor (the area with a smaller crystal grain size than Zhouyuan ’s), so that the original scale of polycrystalline silicon film 5 is applicable to China National Standard (CNS) A4 (210X297 Cli) (Please read the precautions on the back before filling in this page) Binding · Order-Printed by Beigong Consumer Cooperative of Central Bureau of Standards of the Ministry of Economic Affairs 〇08S26 A7 B7 V. Description of the invention (3) Uniformity becomes good. Learn here For example, the laser beam with different energy densities is irradiated to the silicon layer twice for annealing in the second step. After that, the laser beam is moved relative to the substrate, and the process of irradiating the area where the polycrystalline silicon thin film is to be formed is counted as one step. The method for forming the polycrystalline thin film annealed using the above two steps is, for example, published Reported in Extended Abstracts of the 1992 International Conference on Solid State Devices and Material Bl-4 (1992) P.55-57) 0, referring to Figure 11 (a) ~ (b), to illustrate the use of excimer laser annealing polycrystalline Other methods of forming the silicon film are as follows. In this example, as shown in 圊 1 1 (a), for the amorphous silicon layer 2 on the substrate 1 heated to about 400 ° C, implement an excimer mine with an energy density of about 300 OmJ / cm2 Shot annealing. In the heated state of the substrate, compared with the non-heated state, the solidification speed is reduced and the growth of the crystal grains is promoted. In addition, in the case of annealing in a non-heated state, the temperature is less than the melting point and there is no melting area, and only the substrate is heated and separated to increase the film temperature, and the molten state reaches the melting point. Therefore, as the entire laser beam irradiation area undergoes the process of melting and crystallization, as shown in FIG. 11 (b), the crystalline uniformity of the polycrystalline silicon thin film will become good. Although there is a method to increase the placement density of the laser beam in a non-heated state to melt the entire irradiation field, the frequency of abrasion of the film becomes higher, so this method is not used very much. In this substrate heating state, the implementation of excimer laser annealing to form multi-junction paper is again applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (please read the precautions on the back before filling this page). f. The Ministry of Economic Affairs, Central Bureau of Standards, Beigong Consumer Co., Ltd. du printed A7 _____ B7 _ ^ _ V. Description of the invention (4) The method of crystal thin film, for example, the report is published in I.E.D.Μ T e chnical Digest (1991) From page 5 6 3 to page 5 6 6 (I, E, DM Tech · Digest (1991) Ρ · 563-566) 0 Like this, when the TFT is formed using the obtained polycrystalline silicon thin film, the Unevenness in the plane of movement will be suppressed to ± 10%. This T F T manufacturing method is, for example, the report published in Extended Abstracts of the 1991 International Conference ο n S o 1 id State Devices and Materials (1991) pp. 6 2 3 to 6 2 5). [Problems to be Solved by the Invention] However, the method of the conventional example has the following problems. During the two-step annealing, the annealing in the first step is the area irradiated on the peripheral edge of the profile of the laser beam 1, especially the part of the energy density near the crystallization threshold, and the average crystal grain size is around 50 nm For comparison, a crystalline area with a small average crystal particle size is formed, so when the overlapping area is irradiated or the annealing in the second step also has some expansion of the crystal particle size or reduction of crystal defects. Therefore, the difference between the crystallization properties of the crystallized S | jaw domain after the melting and crystallization of the amorphous Si is still large. In addition, when the substrate is heated and laser annealing is to be performed, melting and crystallization will occur even in the crystalline area with a small average crystal grain size compared with the surroundings. However, when changing from amorphous to polycrystalline, and When the above-mentioned average crystal grain size changes from a small crystalline state to a polycrystalline state, the size of the crystallized paper is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) ---------- ^ ^- ---.— 、 玎 — · ----- '(Please read the precautions on the back before filling in this page) The Central Standard Rating Bureau of the Ministry of Economic Affairs, Industrial and Consumer Cooperatives Co., Ltd. 轈 s〇SS26 A7 B7 V. Description of invention ( 5) The energy required is different, and the crystals produced will also differ. As such, if the crystallinity of the polycrystalline silicon thin film is uneven along the surface direction of the substrate according to the above-mentioned conventional technology, if the polycrystalline silicon thin film is used to form a TFT array, the device characteristics of the TFT The problem of in-plane unevenness cannot be reduced to a sufficient level. In particular, when a TFT array is formed in the display portion of the liquid crystal display device, due to the presence of TFTs with relatively low mobility, grid-like display unevenness appears on the screen, and the display quality may be impaired. The present invention is to solve the above-mentioned problems, and its object is to provide a method of forming a polycrystalline silicon thin film that is stupid in crystallinity in-plane uniformity, and to provide a method of manufacturing thin-film transistors with small in-plane unevenness in characteristics. [Means for solving the problem] The method for forming a polycrystalline thin film of the present invention includes a process of forming a thin film of microcrystals functioning as crystal nuclei required for polycrystallization on an insulating substrate, and The thin film is laser annealed to perform a polycrystallization process, thereby achieving the above-mentioned object. In a certain aspect, the thin film before the crystallization process includes the microcrystalline layer and an amorphous layer in contact with the microcrystalline layer. The thin film before the polycrystallization process may include a microcrystalline layer including the microcrystals and the amorphous layer deposited on the microcrystalline layer. The above film before the above polycrystallization process may also include: Amorphous This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297mm) (Please read the precautions on the back before filling this page) Order Λ! A7 B7 printed by the Employees ’Consumer Cooperative of the Central Department of Economic Affairs of the Ministry of Economic Affairs 5. The description of the invention (6) layer and piled up on the amorphous slaughter, and the microcrystalline layer containing the above-mentioned microcrystal 0 Other amorphous layers on the microcrystalline layer. The above microcrystalline layer can also be formed using a CVD method. In a preferred embodiment, the laser annealing is performed using excimer laser. In one embodiment, the laser annealing is performed while maintaining the temperature of the green substrate at a temperature range of about 200 ° C to 600 ° C. In a certain form of application, the above-mentioned thin film is formed of a semiconducting material mainly composed of silicon or germanium. The average crystal grain size of the microcrystals of the above microcrystal layer is a method for forming a polycrystalline thin film according to any one of the first to fifth patent application ranges of less than 20 nm. The process of forming the above-mentioned thin film may also include: a process of forming an amorphous layer, and a process of forming the microcrystalline nucleus by annealing the amorphous layer with a laser beam having an energy density near the crystallization threshold . In one embodiment, the process for forming the microcrystalline layer includes: a process for forming an amorphous layer, and annealing the amorphous layer with a laser beam having an energy density near the crystallization threshold value, thereby The crystalline layer is transformed into the above-mentioned microcrystalline layer process. The manufacturing method of the thin film transistor of the present invention includes: a process of forming a semiconductor thin film on an insulating substrate that includes a part of micro crystals that function as crystal nuclei required for polycrystallization on an insulating substrate, and the process The size of the semi-conducting paper is applicable to the China Aided Standard (CNS) A4 (210X297mm) (please read the precautions on the back before filling this page)

經濟部中央橾準局貝工消费合作社印製 A7 __B7____ 五、發明説明（7 ) 體薄膜使用雷射退火加以多結晶化，藉此，形成多結晶半 導體薄膜之製程，與在該多結晶半導體薄膜中，形成源極 頜域，汲極領域，及通道頜域之製程，藉其來達成上述目 的° 於某實施形態，係在上述多結晶化製程前之上述半導 體薄膜，係包含有：包含上述微結晶之微結晶半導體層， 與接觸於該微結晶半導髏層之非晶質半導體層。 【發明之實施形態】 茲參照圖面說明本發明之多結晶薄膜之形成方法如下 在下述之實施例，係尤其對於非晶質矽層實施雷射準 分子雷射光束之退火，藉其形成多結晶矽薄膜。按，本申 請說明書，將包含平均粒徑爲2 0 nm以下結晶粒之層（ 薄膜）稱爲「微結晶層（薄膜）」。微結晶層係被認爲在 非晶質部分之中處於分散了微結晶之狀態。與此相較，將 具有平均粒徑超過2 0 nm結晶粒之層（薄膜）爲「多結 晶餍（薄膜）」。一般，多結晶薄膜係結晶粒互相接觸， 藉此，變成形成結晶粒界之狀態。 (實施例1 ) 邊參照圚1 (a)及（b)，說明本發明之多結晶薄 膜之製造方法之第1實施例說明如下。 覆蓋了做爲防止玻璃中雜質之擴散所用之緩衝層 s i 0 2膜（沒有圖示）之玻璃基板（CORN I NG CO製 本紙張尺度速用中國國家橾準（CNS ) A4規格（210X297公釐） ~ ' --- (請先閲讀背面之注意事項再填寫本頁)Printed by the Ministry of Economic Affairs, Central Bureau of Precision Industry, Beigong Consumer Cooperative A7 __B7____ 5. Description of the invention (7) The bulk film is laser-annealed to be polycrystallized, thereby forming a polycrystalline semiconductor film, and the process of forming the polycrystalline semiconductor film In the process of forming the source jaw domain, the drain domain, and the channel jaw domain, to achieve the above purpose. In an embodiment, the semiconductor thin film before the polycrystallization process includes: including the above A microcrystalline microcrystalline semiconductor layer and an amorphous semiconductor layer in contact with the microcrystalline semiconductor layer. [Embodiment of the invention] The method of forming the polycrystalline thin film of the present invention is described below with reference to the drawings. In the following embodiments, the laser excimer laser beam is annealed especially for an amorphous silicon layer, by which the formation of multiple Crystalline silicon film. According to this manual, the layer (thin film) containing crystal grains with an average particle diameter of less than 20 nm is called "microcrystalline layer (thin film)". The microcrystalline layer system is considered to be in a state where microcrystals are dispersed in the amorphous portion. In contrast to this, the layer (thin film) having crystal grains having an average particle diameter exceeding 20 nm is referred to as "multi-junction crystal (thin film)". In general, the polycrystalline thin film is such that the crystal grains are in contact with each other, whereby the crystal grain boundaries are formed. (Embodiment 1) The first embodiment of the method for manufacturing a polycrystalline thin film of the present invention will be described below with reference to Qi 1 (a) and (b). A glass substrate covered with a buffer layer si 0 2 film (not shown) used to prevent the diffusion of impurities in the glass (CORN I NG CO made paper-scale speed-use China National Standards (CNS) A4 specification (210X297 mm) ~ '--- (Please read the notes on the back before filling this page)

A7 B7 經濟部中央搮準局貝工消費合作社印製 五、發明説明（8 ) 7059玻璃）1上，例如，將矽甲烷（SiH4)與氫 (H2)做爲原料氣體所使用之電漿CVD法，堆稹膜厚 5 nm之微結晶矽層2 °此時之堆積條件，係S i H4/ (SiH4+H2)比爲位於〇· 01〜〇_ 5%之範圍 ，壓力爲0. 4〜2Torr，電力密度爲0. 1〜 0 . 5 W / c m 2 ，基板溫度爲15 0〜3 0 0 °C。從 成膜之產置（throughput)之觀點，微結晶矽餍2之厚度 係位於約1〜1Onm之範圍內較佳。像這樣，藉選擇上 述條件，雖然可獲得包含微結晶矽層2，但是，若 S i Η 4 / ( S i Η 4 + Η 2 )比爲5 %以上時，則不能 獲得微結晶矽層，而形成通常之非晶質矽層。又，替代上 述氣體，即使使用S i H4/S i F4混合氣體，也可獲得 微結晶矽層2。欲獲得微結晶矽層2之其他方法，係堆稹 非晶質矽層之後，也可以使用具有結晶化閾値附近能置密 度之雷射光東來退火非晶質矽層。 接著，由以矽烷做爲原料氣體使用之電漿CVD法， 將膜厚5 0 nm之非晶質矽層3堆積於微結晶矽層2上。 非晶質矽層3之厚度爲位於3 0〜2 0 0 nm之範園內較 佳。若非晶質矽層3具有超過2 0 0 nm厚度時，由雷射 光束退火而恐有不能充分熔化到非晶質矽層3下面之虞。 接著，使用公知之光學成像法（photolithography) 及蝕刻技術加工非晶質矽層3及微結晶矽層2而形成島 狀構造。圖1 (a)係表示單一之島狀檐造，但是資際上 ，係多數ft狀構造排列於同一基板上。各島狀構造之大小 = | 彳-- (請先閱讀背面之注意事項再填寫本頁) 言 本紙張尺度適用中國國家梂牟（CNS ) A4规格（210X297公釐）-n 經濟部中央棣準局貝工消費合作社印製 A7 B7 五、發明説明（9 ) ，係例如爲 2 0//Π1Χ2 0"m。 接著，如圇1 ( a )以模式所示，將雷射光束4照射 爲島狀構造。照射係使用分步重複（step and reapeat) 法進行。本實施例之雷射光束照射係使用波長3 Ο 8 nm ，脈衝幅4 5毫微（nano)秒，能量密度2 0 0〜5 Ο 〇 m J / cm2之準分子雷射光束實施。 照射此雷射光束4之非晶質矽層3係使用微結晶矽層 2中之微結晶做爲種子（s e e d )而成長結晶粒。其結 果如圖1 ( b )以模式性地表示，可獲得到基板全面分布 均勻之大小結晶粒（粒徑：約2 0 0〜3 0 0 nm。 (實施例2 ) 邊參照圖2 (a)及（b)，說明本發明之多結晶薄 膜之製造方法之第2實施例如下。在覆盖有爲了防止玻璃 中雜質之擴散所需之緩衝層之S i 〇2膜（沒有圇示）之 玻璃基板（CORNING CO，製7 0 5 9玻璃）1上，例如 ，使用矽乙烷（S i 2H6)做爲原料之電漿CVD法，堆 稹膜厚8 Q nm之非晶質矽層3 °堆積時之基板溫度係例 如設定爲4 5 0 °C °非晶質矽層3之厚度係，與上述同樣 之理由，位於3 0〜2 0 0 nm較佳。 接著’基板溫度上升到4 8 0 °C，持續，將矽烷做爲 原料使用由CVD法，將膜厚5 nm之微結晶矽層2堆稹 於非晶質砂層3之上。微結晶较層2之厚度係位於1〜 1 0 nm之範園內較佳。 本紙張ΛΑ適用中國國家橾準（CNS >A4胁（21GX297公慶) ' -12 - (請先閲讀背面之注意事項再填寫本頁) 、π A7 _B7_^_ 五、發明说明（10 ) 接著，使用公知之光學成像法及蝕刻技術加工非晶質 矽層3及微結晶矽層2，以形成島狀之構造。在圖2 (a )係雖然表示單一之島狀構造，但是，實際上爲多數之島 狀構造排列於同一基板上。各島狀構造之大小係，例如， 爲 4 0//mX4 〇jumo 接著，如圇2 (a)以模式性地表示，將雷射光束4 照射成島狀構造。照射係與實施例1相同條件下進行。 於照射此雷射光束4之非晶質矽層3，係將微結晶矽 層2之微結晶做爲種子結晶成長結晶粒。其結果，如圖2 (b )以模式方式表示，可獏得基板全面分布均勻大小之 結晶粒（約2 0 0〜3 0 0 nm)之多結晶矽薄膜5。 本實施例之非晶質矽層3之厚度係較實施例1之非晶 質矽層3之厚度3 0 nm爲厚。一般，若非晶質矽層3厚 時，由雷射退火之結晶成長係從非晶質矽厝3之表面進行 之可能性爲强。因而，在本實施例，係將做爲種子結晶發 揮功能之微結晶矽層2配®成與非晶質矽層3表面接觸。 經濟部中央棣率局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) (實施例3 ) 邊參照圖3 (a)及（b)，說明本發明之多結晶薄 膜之製造方法之第3實施例如下。 在覆蓋有爲了防止玻璃中雜質之擴散所需之緩衝層之 S i 〇2膜（沒有圖示）之玻璃基板（CORNING C0，製 7059玻璃）1上，例如，使用矽甲烷（SiH4)做 爲原料之電漿CVD法，堆稹膜厚2 0 nm之非晶質矽層 - 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） ，0 -丄J - 經濟部中央標準局貝工消费合作社印製 A7 ____B7_^_________ 五、發明説明（11 ) 3。堆積時之基板溫度係例如設定爲3 0 0 °C。非晶質矽 層3之厚度係，位於30〜200nm較佳。 接著，例如將矽甲烷（S iH4)與氟化矽（S i F4 )做爲原料氣體使用之電漿CVD法，堆積膜厚5 nm之 微結晶矽層2 .。基板溫度係設定爲3 0 0°C。微結晶矽層 2之厚度係位於1〜1 0 nm範圍內較佳》 將基板溫度定爲2 7 0 °C，持績地將矽烷做爲原料使 用之CVD法，將膜厚5 nm之非結晶質矽層6堆稹於微 結晶矽層2之上。微結晶矽層2之厚度係位於1〜 10nm之範圍內較佳。 接著，使用公知之光學成像法及蝕刻技術加工非晶質 矽層3及微結晶矽層2，以形成島狀之構造。在圖3 (a )係雖然表示單一之島狀構造，但是，實際上爲多數之島 狀構造排列於同一基板上》各島狀構造之大小係，例如， 爲 20emx20；am。 接著，如圖3 ( a )以模式性地表示，將雷射光束4 照射成島狀構造。照射係與實施例1相同條件下進行。 於照射此雷射光束4之非晶質矽層3及6，係將微結 晶矽層2做爲種子結晶而在上下成長結晶粒。其結果，如 圖3 ( b )以模式方式表示，可獲得基板全面分布均勻大 小之結晶粒（約2 0 0〜3 0 0 nm)之多結晶矽薄膜5 〇 在本實施例，係將非晶質矽層3之厚度與非結晶質矽 層6之厚度成爲相等，但是，也可以相異。 本紙張又度適用中國國家橾準（CNS ) A4規格（210X297公釐） f^訂 \~ ^ ( (請先閲讀背面之注意事項再填寫本頁) -14 - 翅濟部中夬棟準局貝工消費合作社印製 3〇^526 at B7 五、發明説明（12 ) 在上述實施例1〜實施例3，係將微結晶矽餍2及非 晶質矽層3形成圖樣（patterning)之後，資施多結晶化 之雷射退火，但是也可以實施雷射退火之後形成圖樣爲島 狀。按，若將微結晶矽層2及非晶質矽層3形成圓樣之後 ，實施多結晶化之雷射退火時，則在島狀構造之端緣部分 ，由於端緣清洗之影響而結晶性可能發生劣化。此種結晶 性劣化之端緣部分（例如，寬度1 程度之端緣部分） 係，也可使用蝕刻做選擇性之去除。 (實施例4 ) 邊參照圖4 ( a )至（c )說明本發明之多結晶薄膜 之製造方法之第4實施例如下》在本實施例係使用準分子 雷射（XeCl雷射，波長：308nm)之退火製程， 形成多結晶矽薄膜》 首先，在基板1上堆積非晶質矽層3之後，如圖（a )所示，實施第1退火製程（微結晶化製程）。此退火係 將準分子雷射光束4照射於非晶質矽層3進行。準分子雷 射光束4之能量密度係，調整爲在雷射光束中央部具有結 晶化閾值附近（約1 60mJ/cm2)之能量密度。具 有結晶化閾值附近之能量密度雷射光束之照射，係在非晶 質矽層3中形成多數微結晶。因此，於非晶質矽層3由雷 射光束4所照射領域之中，由雷射光束4端邊周邊部所照 射之部分，係以非晶質狀態不會微結晶化，而維持起始狀 態。而在已照射脈衝狀雷射光束4之領域，部分重叠下一 本紙張尺度遑用中國國家標準（CNS ) A4规格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂A7 B7 Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economy V. Description of Invention (8) 7059 Glass) 1, for example, plasma CVD using silane (SiH4) and hydrogen (H2) as raw material gases Method, the microcrystalline silicon layer with a stack thickness of 5 nm and a thickness of 2 nm at 2 ° at this time is based on the Si H4 / (SiH4 + H2) ratio in the range of 0.01 to _5% and the pressure is 0.4. ~ 2Torr, power density is 0.1 ~ 0.5 W / cm 2, substrate temperature is 15 0 ~ 3 0 0 ° C. From the viewpoint of film formation throughput, the thickness of the microcrystalline silicon carbide 2 is preferably in the range of about 1 to 10 nm. In this way, by selecting the above conditions, although the microcrystalline silicon layer 2 can be obtained, if the Si H 4 / (S i H 4 + H 2) ratio is 5% or more, the microcrystalline silicon layer cannot be obtained. And the usual amorphous silicon layer is formed. In addition, instead of the above-mentioned gas, even if a mixed gas of SiH4 / SiF4 is used, the microcrystalline silicon layer 2 can be obtained. For other methods of obtaining the microcrystalline silicon layer 2, after stacking the amorphous silicon layer, it is also possible to anneal the amorphous silicon layer using laser light with a density close to the crystallization threshold. Next, an amorphous silicon layer 3 with a thickness of 50 nm is deposited on the microcrystalline silicon layer 2 by a plasma CVD method using silane as a source gas. The thickness of the amorphous silicon layer 3 is preferably within a range of 30 to 200 nm. If the amorphous silicon layer 3 has a thickness exceeding 200 nm, it may be annealed by the laser beam and may not be sufficiently melted under the amorphous silicon layer 3. Next, the amorphous silicon layer 3 and the microcrystalline silicon layer 2 are processed using known photolithography and etching techniques to form an island-like structure. Figure 1 (a) shows a single island-like eaves structure, but in terms of resources, most ft-shaped structures are arranged on the same substrate. The size of each island-shaped structure = | 彳-(please read the precautions on the back before filling in this page) The paper size is applicable to the Chinese national moumu (CNS) A4 specification (210X297 mm) -n Ministry of Economic Affairs Central Standard A7 B7 printed by the Bureau Cooperative Consumer Cooperative V. Description of the invention (9), for example, 20 // Π1Χ2 0 " m. Next, as shown in FIG. 1 (a), the laser beam 4 is irradiated into an island-like structure. The irradiation system is performed using a step and reapeat method. The laser beam irradiation in this embodiment is implemented using an excimer laser beam with a wavelength of 3 Ο 8 nm, a pulse amplitude of 45 nanoseconds, and an energy density of 2 0 0 ~ 5 〇 0 m J / cm2. The amorphous silicon layer 3 irradiated with the laser beam 4 uses the crystallites in the microcrystalline silicon layer 2 as seeds (se e d) to grow crystal grains. The results are schematically shown in FIG. 1 (b), and crystal grains of a size uniformly distributed throughout the substrate (particle size: about 200 to 300 nm) can be obtained. (Example 2) Referring to FIG. 2 (a ) And (b), the second embodiment of the method for manufacturing a polycrystalline thin film of the present invention is as follows. The S i 〇2 film (not shown) covered with a buffer layer required to prevent the diffusion of impurities in glass On a glass substrate (CORNING CO, made of 7 0 5 9 glass) 1, for example, a plasma CVD method using silicon dioxide (S i 2H6) as a raw material, an amorphous silicon layer with a thickness of 8 Q nm is stacked 3 ° The substrate temperature at the time of stacking is set to, for example, 4 5 0 ° C ° The thickness of the amorphous silicon layer 3 is the same reason as above, it is preferably located at 30 to 200 nm. Then the substrate temperature rises to 4 At 80 ° C, using silane as raw material, the microcrystalline silicon layer 2 with a thickness of 5 nm is stacked on the amorphous sand layer 3 by the CVD method. The thickness of the microcrystalline layer 2 is located at 1 ~ 1 0 nm is better in the fan garden. This paper ΛΑ is suitable for China National Standard (CNS & A4) (21GX297 Gongqing) '-12-(Please read the notes on the back first (Fill in this page), π A7 _B7 _ ^ _ V. Description of the invention (10) Next, the amorphous silicon layer 3 and the microcrystalline silicon layer 2 are processed using known optical imaging methods and etching techniques to form an island-like structure. Although Fig. 2 (a) shows a single island-like structure, in fact, most island-like structures are arranged on the same substrate. The size of each island-like structure is, for example, 40 // mX4. As shown in Fig. 2 (a), the laser beam 4 is irradiated into an island-like structure in a model. The irradiation is performed under the same conditions as in Example 1. The amorphous silicon layer 3 irradiated with the laser beam 4 is The microcrystals of the microcrystalline silicon layer 2 are used as seed crystals to grow crystal grains. As a result, as shown in FIG. 2 (b) in a mode, tapers can obtain crystal grains with a uniform size (approximately 2 0 0 ~ 3 0 0 nm) polycrystalline silicon film 5. The thickness of the amorphous silicon layer 3 in this embodiment is thicker than the thickness 30 nm of the amorphous silicon layer 3 in embodiment 1. Generally, if the amorphous silicon layer 3 is thick At this time, there is a strong possibility that the crystal growth by laser annealing proceeds from the surface of the amorphous silicon alloy 3. Therefore, In this embodiment, the microcrystalline silicon layer 2 functioning as a seed crystal is matched with the surface of the amorphous silicon layer 3. Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Affairs of the Ministry of Economic Affairs (please read the back page first (Notes to fill out this page) (Example 3) With reference to Figure 3 (a) and (b), the third embodiment of the method for manufacturing a polycrystalline thin film of the present invention is as follows. On the glass substrate (CORNING C0, made by 7059 glass) 1 of the Si0 2 film (not shown) of the buffer layer required for diffusion, for example, the plasma CVD method using silicon methane (SiH4) as the raw material, stacking Amorphous silicon layer with a thickness of 20 nm-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 mm), 0-丄 J-Printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 ____ B7_ ^ _________ 5. Description of the invention (11) 3. The substrate temperature during stacking is set to 300 ° C, for example. The thickness of the amorphous silicon layer 3 is preferably between 30 and 200 nm. Next, for example, a plasma CVD method using silane methane (S iH4) and fluorinated silicon (S i F4) as raw material gases, a microcrystalline silicon layer with a thickness of 5 nm is deposited 2. The substrate temperature is set to 300 ° C. The thickness of the microcrystalline silicon layer 2 is preferably in the range of 1 to 10 nm. The substrate temperature is set at 270 ° C, and the CVD method using silane as the raw material is adopted. The thickness of the film is 5 nm. The crystalline silicon layer 6 is piled on the microcrystalline silicon layer 2. The thickness of the microcrystalline silicon layer 2 is preferably in the range of 1-10 nm. Next, the amorphous silicon layer 3 and the microcrystalline silicon layer 2 are processed using known optical imaging methods and etching techniques to form an island-like structure. Although Fig. 3 (a) shows a single island-like structure, in fact, most island-like structures are arranged on the same substrate. The size of each island-like structure is, for example, 20emx20; am. Next, as shown schematically in FIG. 3 (a), the laser beam 4 is irradiated into an island structure. The irradiation was performed under the same conditions as in Example 1. The amorphous silicon layers 3 and 6 irradiated with the laser beam 4 use the microcrystalline silicon layer 2 as a seed crystal to grow crystal grains up and down. As a result, as shown in FIG. 3 (b) in a mode, a polycrystalline silicon thin film 50 with crystal particles (about 200 to 300 nm) uniformly distributed throughout the substrate can be obtained. In this embodiment, it is not necessary to The thickness of the crystalline silicon layer 3 and the thickness of the amorphous silicon layer 6 are equal, but they may be different. This paper is also applicable to China National Standard (CNS) A4 (210X297mm) f ^ subscribe \ ~ ^ (Please read the precautions on the back and then fill out this page) -14-Zhongjidong Prefectural Bureau Printed by Beigong Consumer Cooperatives 3 ^ 526 at B7 5. Description of the invention (12) In the above Examples 1 to 3, after patterning the microcrystalline silicon fertilizer 2 and the amorphous silicon layer 3, Multi-crystallized laser annealing is applied, but it can also be formed after laser annealing to form an island-like pattern. Press, if the microcrystalline silicon layer 2 and the amorphous silicon layer 3 are formed into round samples, then perform polycrystallization During laser annealing, at the edge of the island structure, the crystallinity may be degraded due to the cleaning of the edge. The edge of the degraded crystallinity (for example, the edge of about 1 width) is Etching can also be used for selective removal. (Embodiment 4) The fourth embodiment of the method for manufacturing a polycrystalline thin film of the present invention will be described with reference to FIGS. 4 (a) to (c). Molecular laser (XeCl laser, wavelength: 308nm) annealing process to form Polycrystalline silicon film "First, after depositing the amorphous silicon layer 3 on the substrate 1, as shown in (a), the first annealing process (microcrystallization process) is carried out. This annealing system will excimer laser beam 4 Irradiation is performed on the amorphous silicon layer 3. The energy density of the excimer laser beam 4 is adjusted to have an energy density near the crystallization threshold (approximately 1 60 mJ / cm2) in the center of the laser beam. It has a crystallization threshold The energy density of the laser beam is formed by forming many microcrystals in the amorphous silicon layer 3. Therefore, in the area where the amorphous silicon layer 3 is irradiated by the laser beam 4, the end of the laser beam 4 The part irradiated by the peripheral part will not be crystallized in an amorphous state, and maintain the initial state. In the field where the pulsed laser beam 4 has been irradiated, the next paper scale is partially overlapped. (CNS) A4 specification (210X297mm) (Please read the precautions on the back before filling this page)

C 經濟部中央揉準局貝工消費合作社印裝 A7 __B7___ 五、發明説明（13 ) 脈衝狀之雷射光束4而依序反復照射，就可形成微結晶矽 層2。 茲如圖4(b)所示，實施第2退火製程。此退火係 使用雷射光束斷面之中央部具有約4 0 0 m J / cm 2能童 密度之準分子雷射光束實施。由第2道退火，就可從微結 晶矽層2形成多結晶矽薄膜4。此時，由具有準分子雷射 光束之結晶化閾值能量附近及其以下之能量密度部分，所 照射之微結晶矽層2領域，仍維持微結晶狀態面不發生變 化。而經具有超此值以上能量密度之部分所照射之微結晶 矽層2領域，係留下在第2道退火製程所形成之微結晶骨 格而成長爲多結晶化。 此係因隨著從非晶質，微結晶，而多結晶進行到結晶 化’其熔點將變髙，而雷射光之吸收係數具有變小之傾向 ’所以’若一旦從非晶質變化到微結晶或多結晶時，就需 要熔化或結晶性變化所需之多餘能量所致。因此，第1道 退火及第2道退火時之任何情況，將不生成結晶性發生變 動之領域，而可提升結晶均勻性。 (實施例5 ) 茲邊參照圖5(a)到（c)，說明本發明之多結晶 薄膜之製造方法之第5資施例如下。本實施例，也使用·準 分子雷射（XeCl雷射，波長：308nm)之退火製 程’形成多結晶矽薄膜》 首先，在基板1上堆積非晶質矽層3之後，如圖5 ( 本紙張尺度適用中國國家標準（CNS )八4規格（2丨0父297公釐） (請先閱讀背面之注意事項再填寫本頁) 裝. 訂 -16 - 經濟部中央標準局貝工消費合作社印製 A7 B7 五、發明説明（14 ) a)所示，實施第1道退火製程（微結晶化製程）。此退 火係，如圖5 ( a )所示，對於已經照射脈衝狀雷射光束 4之領域局部地重叠下一脈衝狀之雷射光束4而依序反復 進行照射。在雷射光束剖面中央部，因具有結晶化閾值程 度之約1 6 OmJ / cm2之能量密度，形成包含由第1 道退火之微結晶之微結晶矽層2。 接著，如圖5 (b)所示，使用雷射光束剖面面中央 部具有約4 0 〇m J / cm2能量密度之準分子雷射光束實 施第2道退火。此退火係將基板1溫度使用加熱器等之基 板加熱手段7以保持在約2 0 0〜6 0 0 °C之狀態下•將 準分子雷射光束4照射於非晶質矽層3進行。由第2道退 火，就可從微結晶矽層2形成多結晶矽薄膜4。於第2道 退火時，因微結晶矽層2與基板1之溫度差較不加熱基板 之情形相較會變小，所以，從微結晶矽層2到基板1之熱 流動會減少。其結果，因凝固（冷卻）速度會變慢，所以 ，較不加熱基板之情況相較，其結晶粒徑會擴大。又，凝 固時所生成之結晶應變也會減少，所以，可形成高品質且 基扳面內均勻性良好之多結晶矽薄膜。 在上述實施例1〜5，係做爲多結晶化之薄膜材料， 使用了矽，但是，本發明也可適用於其他半導體材料，例 如’鍺’矽，鍺合金等。又’做爲非晶質薄膜之堆稹方法 ，使用了電漿CVD法與熱CVD法，但是，也可使用其 他薄膜堆稹法，例如，E CR— CVD法，遙控CVD法 ，或噴猫（spatter)法等。 本紙張尺度逋用中國國家橾準（CNS > A4規格（210X297公釐〉 '—' -17 - I (裝 _ ^訂- - C (請先閲讀背面之注意事項再填寫本頁) A7 __B7_ 五、發明説明（I5 ) 又，基板也替代Corning公司製之7 0 5 9玻璃基 板•也可以使用其他玻璃基板，石英基板，藍賫石基板等 絕緣性基板。做爲雷射使用了準分子雷射，但是，使用其 他雷射，例如YAG雷射也可獲得同樣之效果。 (實施例6 ) 茲參照圖6(a)到（d)，說明本實施例之TFT 製造方法之實施例如下。 首先，爲了防止玻璃中雜質之擴散所需覆蓋了緩衝層 S i 0 2膜（沒有圖示）之玻璃基板（Corning 公司製 7059玻璃）基板1上，例如，將矽甲烷（S iH4) 與氫（H2)做爲原料氣體使用之電漿CVD法，堆稹膜 厚5 nm之微結晶矽層2。微結晶矽層2之厚度係位於1 〜10nm範圍內較佳β 接著，由使用矽烷做爲原料氣體之電漿C VD法，將 膜厚5 0 nm之非晶質矽層3堆積於微結晶矽層2上。非 晶質矽層3之厚度係位於3 0〜2 0 0 nm範圍內較佳。 經濟部中央棣準局貝工消費合作社印製 ---------A袈-- (請先閲讀背面之注意事項再填寫本頁) 接著，使用公知之光學成像法及蝕刻技術加工非晶質 矽層3及微結晶矽層2，而形成島狀構造。在圖6 (a) ，係表示單一島狀構造，但是，實際上爲在同一基板上排 列多數之島狀構造。各島狀構造之大小係例如爲2 0以m X 2 0 // m。 接著，如圚6 ( a )以模式方式所示’將雷射光束4 照射於島狀構造。照射係採用分步重複（step and repe- -本紙張尺度適用中國國家橾準（CNS ) A4規格（210X297公釐〉 -18 - 經濟部中央揉準局負工消费合作社印製 A7 B7 五、發明説明（16 ) at)法進行。本實施例之照射係使用波長308nm，脈 衝寬度4 5微毫秒（nano second)，能量密度2 〇 〇〜 5 0 〇m J / c m2之準分子雷射光束實施。 於照射此雷射光束4之非晶質矽層3，係將微結晶矽 層2之微結晶做爲種子結晶成長其結晶粒。其結果，如圖 6 ( b )所示，在基板1之全面可獲得分布有均勻大小之 結晶粒（約200〜300nm)之多結晶矽薄膜5。 接著，如圖6 (c)所示’使用AP — CVD法將由 S i 〇2所成之閘絕緣膜8堆積於全面。在此閘絕緣膜8 上使用噴濺法堆積了鉻（C r )膜之後，使用光學成像法 及蝕刻技術，將鉻膜形成圖樣’來形成閘電極9。 將閘電極9做爲注入光罩，對於多結晶矽薄膜5注入 雜質離子，藉此如圖6 ( d )所示，在閘電極9於自行整 合位置形成源極領域1〇及汲極領域11。雜質離子之注 入係，例如，可使用不進行質量分離之離子摻質（ iondoping)法實施。或，也可使用桶型離子摻質法。爲 了雜質之活性化，在注入後之某一階段，需要進行3 0 0 °C到6 0 0 °C之熱處理。C Printed by the Beigong Consumer Cooperative of the Central Bureau of Economic Development of the Ministry of Economic Affairs A7 __B7___ V. Description of the invention (13) The pulsed laser beam 4 is sequentially irradiated repeatedly to form the microcrystalline silicon layer 2. As shown in FIG. 4 (b), the second annealing process is performed. This annealing is carried out using an excimer laser beam with an energy density of about 400 mJ / cm 2 in the central part of the laser beam cross section. By annealing in the second pass, a polycrystalline silicon thin film 4 can be formed from the microcrystalline silicon layer 2. At this time, the area of the microcrystalline silicon layer 2 irradiated by the energy density portion near and below the crystallization threshold energy of the excimer laser beam remains unchanged in the microcrystalline state. The area of the microcrystalline silicon layer 2 irradiated with a portion having an energy density above this value is left as a microcrystalline skeleton formed in the second annealing process to grow into polycrystalline. This is because with the transition from amorphous to microcrystalline, and polycrystalline to crystallization, 'the melting point will become high, and the absorption coefficient of laser light has a tendency to become small'. Therefore, if it changes from amorphous to microcrystalline When crystallizing or polycrystallizing, it requires excessive energy required for melting or crystallinity change. Therefore, in any case during the first annealing and the second annealing, the area where the crystallinity changes is not generated, and the crystal uniformity can be improved. (Embodiment 5) With reference to Figs. 5 (a) to (c), the fifth embodiment of the method for manufacturing a polycrystalline thin film of the present invention will be described below. In this embodiment, the annealing process of the excimer laser (XeCl laser, wavelength: 308nm) is also used to form the polycrystalline silicon thin film. First, after the amorphous silicon layer 3 is deposited on the substrate 1, as shown in FIG. 5 (this The paper size is in accordance with the Chinese National Standard (CNS) 84 specifications (297mm for 2 ~ 0 fathers) (please read the precautions on the back before filling out this page). Binding-16-Printed by Beigong Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs System A7 B7 V. Description of the invention (14) a) As shown in a), the first annealing process (microcrystallization process) is carried out. In this annealing system, as shown in FIG. 5 (a), the area where the pulsed laser beam 4 has been irradiated is partially overlapped with the next pulsed laser beam 4 and the irradiation is repeated in sequence. At the center of the laser beam profile, a microcrystalline silicon layer 2 containing microcrystals annealed by the first pass is formed due to an energy density of about 16 OmJ / cm2 of the crystallization threshold level. Next, as shown in FIG. 5 (b), the second annealing is performed using an excimer laser beam having an energy density of about 400 mJ / cm2 in the center of the laser beam cross-section. In this annealing, the temperature of the substrate 1 is maintained by using a substrate heating means 7 such as a heater at a temperature of about 200 to 600 ° C. The excimer laser beam 4 is irradiated to the amorphous silicon layer 3. By annealing in the second pass, a polycrystalline silicon thin film 4 can be formed from the microcrystalline silicon layer 2. During annealing in the second pass, since the temperature difference between the microcrystalline silicon layer 2 and the substrate 1 is smaller than when the substrate is not heated, the heat flow from the microcrystalline silicon layer 2 to the substrate 1 is reduced. As a result, since the solidification (cooling) speed becomes slower, the crystal grain size will increase as compared to the case where the substrate is not heated. In addition, the crystal strain generated during solidification is also reduced. Therefore, a high-quality polycrystalline silicon thin film with good uniformity in the substrate surface can be formed. In the above embodiments 1 to 5, silicon is used as the polycrystalline thin film material, but the present invention can also be applied to other semiconductor materials, such as 'germanium' silicon, germanium alloys, and the like. Also, as a method for stacking amorphous thin films, plasma CVD and thermal CVD are used, but other thin film stacking methods can also be used, for example, E CR-CVD, remote CVD, or cat spraying (Spatter) method etc. This paper uses the Chinese National Standard (CNS> A4 specifications (210X297mm)> '—' -17-I (installed _ ^ ordered--C (please read the precautions on the back and fill in this page) A7 __B7_ V. Description of the invention (I5) In addition, the substrate also replaces the 7 0 5 9 glass substrate manufactured by Corning Co., Ltd. • Other glass substrates, quartz substrates, blue sapphire substrates and other insulating substrates can also be used. The excimer is used as the laser Laser, however, the same effect can be obtained by using other lasers such as YAG laser. (Embodiment 6) The following describes the implementation example of the TFT manufacturing method of this embodiment with reference to FIGS. 6 (a) to (d). First, in order to prevent the diffusion of impurities in the glass, a glass substrate (7059 glass manufactured by Corning Corporation) that covers the buffer layer S i 0 2 film (not shown) is required on the substrate 1, for example, a silicon methane (S iH4) and Plasma CVD method using hydrogen (H2) as raw material gas, stacking microcrystalline silicon layer 2 with a film thickness of 5 nm. The thickness of microcrystalline silicon layer 2 is in the range of 1 to 10 nm, preferably β. Then, by using silane Plasma C VD method as the raw material gas, the amorphous silicon with a thickness of 50 nm Layer 3 is stacked on the microcrystalline silicon layer 2. The thickness of the amorphous silicon layer 3 is preferably in the range of 30 to 200 nm. Printed by the Beigong Consumer Cooperative of the Central Bureau of Economics of the Ministry of Economic Affairs ----- ---- A 袈-(Please read the precautions on the back before filling in this page) Then, use the well-known optical imaging method and etching technology to process the amorphous silicon layer 3 and the microcrystalline silicon layer 2 to form an island shape 6 (a), it shows a single island-like structure, but in fact it is an island-like structure in which a large number of island-like structures are arranged on the same substrate. The size of each island-like structure is, for example, 2 0 to m X 2 0 // m. Next, as shown in mode 6 (a), the laser beam 4 is irradiated to the island-like structure as shown in the model mode. The irradiation system adopts step and repe--This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm> -18-Printed by the Ministry of Economic Affairs Central Bureau of Accreditation and Consumer Cooperatives A7 B7 V. Invention description (16) at) method. The irradiation in this example uses a wavelength of 308 nm and a pulse width of 4 5 Excimer laser beams with an energy density of 200 to 500 mJ / cm2 are implemented in nanoseconds. The amorphous silicon layer 3 that emits this laser beam 4 uses the microcrystal of the microcrystalline silicon layer 2 as a seed crystal to grow its crystal grains. As a result, as shown in FIG. 6 (b), the entire surface of the substrate 1 A polycrystalline silicon thin film 5 with uniformly sized crystal grains (approximately 200 to 300 nm) can be obtained. Next, as shown in FIG. 6 (c), a gate insulating film 8 made of Si 〇2 is formed using AP-CVD method Stacked in full. After a chromium (Cr) film is deposited on the gate insulating film 8 by a sputtering method, the chromium film is patterned using optical imaging and etching techniques to form the gate electrode 9. Using the gate electrode 9 as an implantation mask, impurity ions are implanted into the polycrystalline silicon thin film 5, thereby forming the source region 10 and the drain region 11 at the self-integrated position of the gate electrode 9 as shown in FIG. 6 (d). . The injection system of impurity ions can be implemented by, for example, ion doping without mass separation. Or, the barrel ion doping method can also be used. In order to activate the impurities, heat treatment at 300 ° C to 600 ° C is required at a certain stage after implantation.

接著，將由S i 02所成之層間絕緣膜1 2使用AP 一 CVD法堆積之後，在層間絕緣膜1 2中形成到達源極 領域1 0及汲極領域1 1之接觸孔1 3。將鋁（A 1 )膜 使用噴濺法堆稹之後，使用光學成像法及蝕刻技術將鋁膜 形成圖樣，而形成源極電極1 4及汲極電極1 5。源極電 極14及汲極電極15係分別經由接觸孔以電氣方式接觸 本紙張尺度逋用中國國家揉準（CNS ) A4规格（210X297公釐） ~ -19 - ---------f 袈-----Ί^- —-----{: (請先閱讀背面之注意事項再填寫本頁) 秘 526 at B7 五、發明説明（17 ) 於源極領域10及汲極領域11。 像這樣，即可獲得具有如圖6 ( d )所示構造之 TFT。此後，較佳爲在氫環境中退火TFT，藉此，將 位於多結晶矽薄膜5中之結晶粒界之懸掛鏈（dangling bond)使用氫加以端接（terminate)。此時，T F T之 場效移動度之面內不勻將可抑制在4 %以下。 (實施例7 ) 茲參照圖7(a)到（d)，說明本實施例之其他 T F T製造方法之實施例如下。 爲了防止玻璃中雜質物之擴散所需覆蓋了緩衝層 S i 0 2膜（沒有圖示）之玻璃基板（Corning公司製 7 0 5 9玻璃）基板1上，例如，將矽乙烷（S i2He) 做爲原料氣體使用之電漿CVD法，堆稹膜厚8 0 nm之 微結晶矽層3。堆稹時之基板溫度係例如設定爲4 5 0°C 。非晶質矽層3之膜厚爲位於3 0〜2 0 0 nm之範圍內 較佳。 經濟部中央樣準局貝工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 接著，將基板溫度上升到4 8 0°C，持績地由使用矽 烷做爲原料氣體之電漿CVD法，將膜厚5 nm之微結晶 質矽層2堆積於非晶質矽層3上。微結晶矽層2之厚度係 位於1〜1 0 nm之範圍內較佳》 . 接著，使用公知之光學成像法及蝕刻技術加工非晶質 矽層3及微結晶矽層2，而形成島狀構造。在圇7 (a) ，係表示單一島狀構造，但是，實際上爲在多數島狀構造 本紙張尺度逋用中國國家橾準（CNS ) A4規格（210X297公釐） _ 20 - 經濟部中央揉準扃貝工消费合作社印製 A7 B7 五、發明説明（IS ) 排列於周一基板上。各島狀構造之大小係例如爲2 0 # m X 2 0 仁 m。 接著，如圇7 ( a )以模式方式所示將雷射光束4照 射於島狀構造。照射係與實施例1時之相同條件下實施。 照射此雷射光束4之非晶質矽層3係將微結晶矽層2 之微結晶層2之微結晶做爲種子結晶成長結晶粒。其結果 ，在基板全面可獲得分布均匀大小結晶粒（約2 0 0〜 30Onm)之多結晶矽膜5» 接著，如圖7 (c)所示，使用AP — CVD法將由 S i 02所成之閘絕緣膜8堆積於全面。在此閘絕緣膜8 上使用噴濺法堆積了鉻（C r )膜之後，使用光學成像法 及蝕刻技術，將鉻膜形成圖樣，來形成閘電極9。 將閘電極9做爲注入光罩，對於多結晶矽薄膜5注入 雜質離子，藉此如圖6 ( d )所示，在閘電極9於自行整 合位置形成源極領域10及汲極領域11。 接著，將由S i 02所成之層間絕緣膜1 2使用AP -CVD法堆積之後，在層間絕緣膜12中形成到達源極 領域1 0及汲極領域1 1之接觸孔1 3。將鋁（A 1 )膜 使用噴濺法準稹於膜層間絕緣膜1 2之後，使用光學成像 法及蝕刻技術將鋁膜形成圖樣，而形成源極電極1 4及汲 極電極1 5。源極電極1 4及汲極電極15係分別經由接 觸孔以電氣方式接觸於源極領域10及汲極領域11。 像這樣，即可獲得具有如圖7 ( d )所示構造之 TFT。此後，較佳爲在氫環境中退火TFT，藉此，將 本紙張尺度適用中國國家橾率（CNS ) A4规格（210X297公釐] ~ -21 - (請先閲讀背面之注意事項再填寫本頁)Next, after the interlayer insulating film 12 made of Si 02 is deposited using the AP-CVD method, contact holes 13 reaching the source region 10 and the drain region 11 are formed in the interlayer insulating film 12. After depositing the aluminum (A 1) film by sputtering, the aluminum film is patterned using optical imaging and etching techniques to form the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are electrically contacted with the paper through the contact hole. The Chinese National Standard (CNS) A4 specification (210X297mm) ~ -19---------- f 袈 ----- Ί ^-—----- {: (Please read the precautions on the back before filling in this page) Secret 526 at B7 V. Description of the invention (17) In the source field 10 and the drain Area 11. In this way, a TFT having the structure shown in FIG. 6 (d) can be obtained. After that, it is preferable to anneal the TFT in a hydrogen environment, whereby the dangling bond of the crystal grain boundary in the polycrystalline silicon thin film 5 is terminated with hydrogen. At this time, the in-plane unevenness of the field effect mobility of T F T will be suppressed below 4%. (Embodiment 7) With reference to Figs. 7 (a) to (d), another embodiment of the TFT manufacturing method of this embodiment will be described below. In order to prevent the diffusion of impurities in the glass, a glass substrate (7 0 5 9 glass manufactured by Corning Corporation) covered with a buffer layer S i 0 2 film (not shown) is required. For example, silicon dioxide (S i2He ) Plasma CVD method used as raw material gas, stacking microcrystalline silicon layer 3 with a thickness of 80 nm. The substrate temperature at the time of stacking is set to 4 5 0 ° C, for example. The thickness of the amorphous silicon layer 3 is preferably in the range of 30 to 200 nm. Printed by the Beigong Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page). Then, increase the substrate temperature to 4 8 0 ° C, and continue to use silane as the raw material gas. The slurry CVD method deposits a microcrystalline silicon layer 2 with a thickness of 5 nm on the amorphous silicon layer 3. The thickness of the microcrystalline silicon layer 2 is preferably in the range of 1 to 10 nm. Next, the amorphous silicon layer 3 and the microcrystalline silicon layer 2 are processed using known optical imaging methods and etching techniques to form islands. structure. On the 7th (a), it means a single island structure, but in fact, in most island structures, this paper scale uses the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 20-Ministry of Economic Affairs A7 B7 printed by the quasi-Pei Gong consumer cooperative. V. The description of the invention (IS) is arranged on the substrate on Monday. The size of each island-like structure is, for example, 2 0 # m X 2 0 ren m. Next, as shown in Fig. 7 (a), the laser beam 4 is irradiated on the island-like structure as shown in a pattern. The irradiation was carried out under the same conditions as in Example 1. The amorphous silicon layer 3 irradiated with the laser beam 4 uses the microcrystals of the microcrystalline layer 2 of the microcrystalline silicon layer 2 as seed crystals to grow crystal grains. As a result, a polycrystalline silicon film 5 with uniformly distributed crystal grains (approximately 200 0 to 30 Onm) can be obtained on the entire substrate 5 »Next, as shown in FIG. 7 (c), using the AP-CVD method will be formed by Si 02 The gate insulating film 8 is accumulated all over. After a chromium (Cr) film is deposited on the gate insulating film 8 using a sputtering method, the chromium film is patterned using an optical imaging method and an etching technique to form the gate electrode 9. The gate electrode 9 is used as an implantation mask, and impurity ions are implanted into the polycrystalline silicon thin film 5, thereby forming the source region 10 and the drain region 11 at the self-integrating position of the gate electrode 9 as shown in FIG. 6 (d). Next, after the interlayer insulating film 12 made of Si 02 is deposited using the AP-CVD method, contact holes 13 reaching the source region 10 and the drain region 11 are formed in the interlayer insulating film 12. After the aluminum (A 1) film is quasi-etched on the interlayer insulating film 12 using the sputtering method, the aluminum film is patterned using optical imaging and etching techniques to form the source electrode 14 and the drain electrode 15. The source electrode 14 and the drain electrode 15 are in electrical contact with the source area 10 and the drain area 11 via contact holes, respectively. In this way, a TFT having the structure shown in FIG. 7 (d) can be obtained. After that, it is better to anneal the TFT in a hydrogen environment, thereby adapting this paper standard to the China National Atomic Rate (CNS) A4 specification (210X297mm) ~ -21-(please read the precautions on the back before filling this page )

趣涛部中夬樣率局員工所費合作社印製 A7 B7 五、發明説明（19 ) 位於多結晶矽薄膜5中之結晶粒界之懸掛鏈（dangling bond)使用氫加以端接（terminate)。此時，T F T之 場效移動度之面內不勻將可抑制在4 %以下。 (實施例8 ) 茲參照圖8(a)到（d)，說明本實施例之其他 T F T製造方法之實施例如下。 爲了防止玻璃中雜質之擴散所需覆蓋了緩衝層 S i 0 2膜（沒有圖示）之玻璃基板（Corning 公司製 70 5 9玻璃）基板1上，例如，將矽甲烷（S i H4) 做爲原料氣體使用之電漿CVD法，堆積膜厚2 0 nm之 非晶質矽層3。堆稹時之基板溫度係例如設定爲3 0 0 °C 。非晶質矽層3之膜厚爲位於3 0〜2 0 0 nm之範圍內 較佳。 接著，由使用矽甲烷（s i 04 )與氟化矽（ s i F4)做爲原料氣體之電漿CVD法，堆積膜厚Printed by the cooperative of the staff of the Central Sample Bureau of the Fun Tao Department. A7 B7 V. Description of the invention (19) The dangling bond of the crystal grain boundary in the polycrystalline silicon thin film 5 is terminated with hydrogen. At this time, the in-plane unevenness of the field effect mobility of T F T will be suppressed below 4%. (Embodiment 8) With reference to Figs. 8 (a) to (d), another embodiment of the TFT manufacturing method of this embodiment will be described below. In order to prevent the diffusion of impurities in the glass, a glass substrate (70 5 9 glass manufactured by Corning) covered with a buffer layer S i 0 2 film (not shown) is required. For example, silicon methane (S i H4) is used The plasma CVD method used for the source gas deposits an amorphous silicon layer 3 with a thickness of 20 nm. The substrate temperature during stacking is set to 300 ° C, for example. The thickness of the amorphous silicon layer 3 is preferably in the range of 30 to 200 nm. Next, the plasma CVD method using silane methane (s i 04) and silicon fluoride (s i F4) as the raw material gas, the film thickness is deposited

5 nm之微結晶質矽層2。微基板溫度爲設定於3 0 0 °C °微結晶矽層2之厚度係位於1〜1 〇 nm之範圍內較佳 〇 將基板溫度定爲2 7 0°C，持續，使用以矽烷做爲原 料氣體之CVD法’將膜厚2 0 nm之非結晶質砂層6堆 積於微結晶矽層2上。微結晶矽層2之厚度係位於1〜 l〇nm範圔內較佳。 接著，使用公知之光學成像法及蝕刻技術加工非晶質 本紙張尺度適用中國國家梂準（CNS ) A4规格（210X：297公釐） {二-----—iT~--^-----f I (請先閱讀背面之注意事項再填寫本頁) -22 - 經濟部中央標準局貝工消费合作社印製 A7 B7 五、發明説明（2〇 ) 矽層3及微結晶矽層2，而形成島狀構造。在圖3 (a) ，係表示單一島狀構造，但是，實際上爲在多數島狀構造 排列於周一基板上。各島狀構造之大小係例如爲2 0 X 2 0 v m。 接著如圖3 ( a )以模式方式所示，將雷射光束4照 射於島狀構造。照射係與實施例1時之相同條件下實施。 照射此雷射光束4之非晶質矽層3及6 *係將微結晶 矽層2之做爲種子結晶成長結晶粒。其結果，在基板全面 可獲得分布均勻大小結晶粒（約2 0 0〜3 0 0 nm)之 多結晶矽膜5。 在本實施例，係將非晶質矽層3之厚度與非結晶質矽 層6之厚度成爲相等，但是，亦可相異。 接著，如圖8 (c)所示，使用AP — CVD法將由 S i 02所成之閘絕緣膜8堆稹於全面。在此閘絕緣膜8 上使用噴濺法堆積了鉻（C r )膜之後，使用光學成像法 及蝕刻技術，將鉻膜形成圖樣，來形成閘電極9 » 將閘電極9做爲注入光罩，對於多結晶矽薄膜5注入 雜質離子，藉此如圖8 所示，在閘電極9於自行整合位 置形成源極領域10及汲極領域11» 接著，將由S i 02所成之層間絕緣膜1 2使用AP 一 C VD法堆積之後，在層間絕緣膜1 2中形成到達源極 領域1 0及汲極領域1 1之接觸孔1 3。將鋁（A 1 )膜 使用噴濺法堆積之後，使用光刻及触刻技術將鋁膜形成圖 樣，而形成源極電極1 4及汲極電極1 5。源極電極1 4 本紙張尺度適用中國國家橾準（CNS ) A4规格（210 X 297公釐） -----I---C，衣-----:—••訂. (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消费合作社印11 30SS26 a? B7 五、發明説明（21 ) 及汲極電極15係分別經由接觸孔以電氣方式接觸於源極 領域1 0及汲極領域1 1。 像這樣，即可獲得具有如圖8 ( d )所示構造之 TFT。此後，較佳爲在氫環境中退火TFT，藉此，將 位於多結晶矽薄膜5中之結晶粒界之懸掛鏈（dangling bond)使用氫加以端接（terminate)。此時，TFT之 場效移動度之面內不勻將可抑制在4〜5 %以下。 上述資施例6〜8係，做爲多結晶化之構造，使用了 矽，但是，本發明也可適用於其他半導體材料，例如，鍺 ，矽，鍺合金等。又，做爲非晶質薄膜之堆稹方法，雖然 使用了電漿CVD法與熱CVD法，但是，也可使用 ECR-CVD法，遙控CVD法，或噴濺法等。 又，基板也可替代Corning公司製之7 0 5 9玻璃 基板，而也可使用其他玻璃基板，石英基板，藍寶石基板 等之絕緣性板。 做爲雷射雖然使用了準分子雷射，但是，使用其他雷 射，例如，VAG雷射也可獲得同樣之效果。 做爲閘電極9，源極電極1 4及汲極電極1 5之材料 ’係除了 Cr ，A1 ，Ta ，Mo ，Ti等金屬之外，也 可使用矽化物，或高濃度地摻雜雜質之多結晶矽，5 nm microcrystalline silicon layer 2. The temperature of the micro-substrate is set at 300 ° C °. The thickness of the microcrystalline silicon layer 2 is in the range of 1 ~ 100nm. It is preferable to set the temperature of the substrate to 270 ° C. Continuously, use silane as the The raw material gas CVD method 'deposits an amorphous sand layer 6 with a thickness of 20 nm on the microcrystalline silicon layer 2. The thickness of the microcrystalline silicon layer 2 is preferably within a range of 1 to 10 nm. Next, use the well-known optical imaging method and etching technology to process amorphous paper. The size of the paper is applicable to the Chinese National Standard (CNS) A4 specification (210X: 297 mm) {二 ------- iT ~-^- --- f I (please read the precautions on the back before filling in this page) -22-A7 B7 printed by the Beigong Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (2〇) Silicon layer 3 and microcrystalline silicon layer 2. An island structure is formed. In Fig. 3 (a), it shows a single island-like structure, but in fact, most island-like structures are arranged on the Monday substrate. The size of each island-like structure is, for example, 20 X 2 0 v m. Next, as shown in the mode of Fig. 3 (a), the laser beam 4 is irradiated to the island-like structure. The irradiation was carried out under the same conditions as in Example 1. The amorphous silicon layers 3 and 6 irradiated with the laser beam 4 use the microcrystalline silicon layer 2 as seeds to grow crystal grains. As a result, a polycrystalline silicon film 5 with uniformly distributed crystal grains (about 200 to 300 nm) can be obtained over the entire substrate. In this embodiment, the thickness of the amorphous silicon layer 3 and the thickness of the amorphous silicon layer 6 are made equal, but they may be different. Next, as shown in FIG. 8 (c), the gate insulating film 8 made of Si02 is stacked on the entire surface using the AP-CVD method. After depositing a chromium (C r) film on the gate insulating film 8 by sputtering, the chromium film is patterned using optical imaging and etching techniques to form the gate electrode 9 »The gate electrode 9 is used as an injection mask , The impurity ions are implanted into the polycrystalline silicon thin film 5, thereby forming the source region 10 and the drain region 11 at the gate electrode 9 at the self-integrating position as shown in FIG. 8 Next, an interlayer insulating film formed by Si 02 1 2 After being deposited by the AP-C VD method, contact holes 13 reaching the source region 10 and the drain region 11 are formed in the interlayer insulating film 12. After depositing the aluminum (A 1) film by the sputtering method, the aluminum film is patterned using photolithography and lithography techniques to form the source electrode 14 and the drain electrode 15. Source electrode 1 4 This paper scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) ----- I --- C, clothing -----:-•• order. (Please Read the precautions on the back first and then fill out this page) Printed by the Ministry of Economic Affairs Central Bureau of Industry and Commerce Beigong Consumer Cooperatives 11 30SS26 a? B7 V. Description of the invention (21) and the drain electrode 15 are electrically contacted with the source through the contact hole The pole field 10 and the drain field 11. In this way, a TFT having the structure shown in FIG. 8 (d) can be obtained. After that, it is preferable to anneal the TFT in a hydrogen environment, whereby the dangling bond of the crystal grain boundary in the polycrystalline silicon thin film 5 is terminated with hydrogen. At this time, the in-plane unevenness of the field effect mobility of the TFT will be suppressed to below 4 ~ 5%. The above examples 6 to 8 are made of polycrystalline structure and use silicon. However, the present invention can also be applied to other semiconductor materials such as germanium, silicon, and germanium alloys. In addition, as the stacking method of the amorphous thin film, although the plasma CVD method and the thermal CVD method are used, the ECR-CVD method, the remote control CVD method, or the sputtering method can also be used. In addition, the substrate may replace the 7 0 5 9 glass substrate manufactured by Corning Corporation, and other glass substrates, quartz substrates, sapphire substrates and other insulating plates may also be used. Although an excimer laser is used as the laser, the same effect can be obtained by using other lasers, for example, VAG laser. As the material of the gate electrode 9, the source electrode 14 and the drain electrode 15, in addition to metals such as Cr, A1, Ta, Mo, Ti, silicides, or high concentrations of impurities Polycrystalline silicon,

SiGe合金，I TO等之透明導電材料等。Transparent conductive materials such as SiGe alloy, I TO, etc.

又，爲了提升電晶體之0 F F特性，也可在多結晶矽 膜中設L D D (Lightly Doped Drain )構造。又’也可 將導電型相異之T F T形成於同一基板上，構成CMO S 本紙張尺度逋用中國國家標準（CNS ) A4规格（210X 297公釐） I-------A ^-----,—.訂—:-----( (請先閱讀背面之注意事項再填寫本頁) -24 - 經濟部中央梂準局ec工消费合作社印装 A7 B7 五、發明説明（22 ) 電路。 【發明之效果】 如以上，若依據本發明，其平均結晶粒徑爲約2 0 n m以下之微結晶薄膜使用雷射光束之退火，而形成爲平 均粒徑爲約2 0 nm以上之多結晶薄膜，基板面內之結晶 均匀性。並且，若加熱基板時，可獲得結晶粒徑之擴大， 結晶應變之降低所需之高品質之多結晶薄膜。又，可控制 使用多結晶薄膜所製作之裝置基板內之不勻。 六.圖式之簡單說明 圖1 (a)及（b)_表示本發明之多結晶薄膜形成 方法之第1實施例之製程剖面圖。 圖2 ( a )及（b )係表示本發明之多結晶薄膜形成 方法之第2實施例之製程剖面圖。 ffl3 ( a )及（b )係表示本發明之多結晶薄膜形成 方法之第3實施例之製程剖面圇。 圚4 ( a )係表示本發明之多結晶薄膜形成方法之第 4實施例之第1退火之圇，（b)係第1實施例形成方法 之第2步驟之退火之圖，（c)係所形成多結晶矽薄膜之 部分剖面圖。 圖5 ( a )係表示本發明之多結晶薄膜形成方法之第 5實施例之第1退火之圖，（b)係第1實施例形成方法 之第2步驟之退火之圖，（c)係所形成多結晶矽薄膜之 本紙張尺度適用中國國家榡準（CNS ) A4規格（2丨0X297公釐） (請先閲讀背面之注意Ϋ項再填寫本頁) ’衣· -訂 -25 - 經濟部中央揉率局貝工消费合作社印製 A7 B7 五、發明説明（23 ) 部分剖面圖。 圖6係從（a )到（d )係，表示本發明之薄膜電晶 體之製造方法實施例之製程剖面圖。 圖7係從（a )到（d )係，表示本發明之薄膜電晶 體之製造方法其他實施例之製程剖面圖。 圖8係從（a )到（d )係，表示本發明之薄膜電晶 體之製造方法其他另外實施例之製程剖面圖。 圖9係表示使用準分子雷射退火之多結晶矽薄膜形成 製程之模式圚。 圖10(a)係表示習知例之第1道退火之圖，（b )係表示第2道退火之圖，（c )係所形成多結晶矽薄膜 之部分剖面圖。 圖1 1 ( a )係表示其他習知例之第1道退火之圖， (b) 係所形成之多結晶矽薄膜之部分剖面圖。 【符號之說明】 1 準分子雷射光束，2 非晶質矽層，3 微結晶 矽層’ 4 多結晶矽薄膜，4a 結晶性發生變動之領域 ’5 基板，6 基板加熱手段。 本紙張尺度遑用中國國家榇準（CNS ) A4規格（210x297公釐） f .衣— (請先閱讀背面之注意事項再填寫本頁) --訂 ~ 26 -In addition, in order to improve the 0 F F characteristic of the transistor, an L D D (Lightly Doped Drain) structure may be provided in the polycrystalline silicon film. Also, TFTs with different conductivity types can be formed on the same substrate to form CMO S. This paper standard uses the Chinese National Standard (CNS) A4 specification (210X 297mm) I ------- A ^- ----, —. 定 —: ----- ((Please read the precautions on the back before filling out this page) -24-A7 B7 printed by the Central Bureau of Economic Affairs of the Ministry of Economic Affairs ec industrial consumer cooperatives V. Description of invention (22) Circuit. [Effects of the Invention] As described above, according to the present invention, a microcrystalline thin film having an average crystal particle size of approximately 20 nm or less is annealed with a laser beam to form an average particle size of approximately 20. For polycrystalline films above nm, the crystal uniformity within the substrate surface. Also, if the substrate is heated, a high-quality polycrystalline film required for the enlargement of the crystal grain size and the reduction of the crystal strain can be obtained. Unevenness in the device substrate produced by the crystalline thin film. 6. Brief description of the drawings. FIG. 1 (a) and (b) _ represent a process cross-sectional view of the first embodiment of the method for forming a polycrystalline thin film of the present invention. FIG. 2 (a) and (b) show the preparation of the second embodiment of the method for forming a polycrystalline thin film of the present invention Cross-sectional view. Ffl3 (a) and (b) are process cross-sectional views of the third embodiment of the method for forming a polycrystalline thin film of the present invention. Si 4 (a) is a fourth implementation of the method for forming a polycrystalline thin film of the present invention Example of the first annealing, (b) is a diagram of the second step of the annealing method of the first embodiment, (c) is a partial cross-sectional view of the polycrystalline silicon thin film formed. Figure 5 (a) shows the present The first annealing diagram of the fifth embodiment of the inventive polycrystalline thin film forming method, (b) is the annealing diagram of the second step of the forming method of the first embodiment, (c) is the basis of the polycrystalline silicon thin film formed The paper scale is applicable to China National Standard (CNS) A4 (2 丨 0X297mm) (please read the note Ϋ on the back and then fill in this page) 'Clothing-Order-25 Printed by the cooperative A7 B7 V. Description of the invention (23) Partial cross-sectional view. Figure 6 is from (a) to (d), showing the process cross-sectional view of the embodiment of the manufacturing method of the thin film transistor of the present invention. Figure 7 is from (A) to (d) represent other embodiments of the manufacturing method of the thin film transistor of the present invention Process cross-sectional view. Figure 8 is from (a) to (d), which shows the process cross-sectional view of another embodiment of the method for manufacturing the thin film transistor of the present invention. Figure 9 shows the polycrystalline silicon using excimer laser annealing The mode of the film formation process. Figure 10 (a) is a diagram showing the first annealing in the conventional example, (b) is a diagram showing the second annealing, (c) is a partial cross-section of the polycrystalline silicon thin film formed Fig. 1 1 (a) is a diagram showing the first annealing in other conventional examples, and (b) is a partial cross-sectional view of a polycrystalline silicon thin film formed. [Description of Symbols] 1 Excimer laser beam, 2 Amorphous silicon layer, 3 Microcrystalline silicon layer ’4 Polycrystalline silicon thin film, 4a Crystallinity change area’ 5 substrates, 6 substrate heating means. This paper uses the Chinese National Standard (CNS) A4 specification (210x297mm) f. Clothing — (Please read the precautions on the back before filling this page) --Subscribe ~ 26-

Claims (1)

驟 8 ·如申請專利範團第i項之顯示面的製造方法，其 中含第1顔料粒子的溶液及含第2顏料粒子的溶液含有分 散劑。 9 .如申請專利範圍第1項之顯示面的製造方法，其 中該基板的全面形成胺基矽烷膜，含第1顔料粒子的溶液 不含附著力調整劑’含第2顏料粒子的溶液含有微粒子氧 化矽。 經濟部中央標準局員工消費合作社印裝 ， 及。，顔 ’中 ，及的 法液鋁法 2 法液 法形形 方溶化方第 方溶 方圖圚 造的氧造含 造的 造料體 製子子製，。製子 製顏光 的粒粒的劑鋁的粒 的 1 螢 面料微面整化面料 面第 2 示顔或示調氧示顔 示與第 顯 l i 顯力子顯 2 * 顯別及 之第 S 之著粒之第%之分 1 項含 I 項附微項含量項有第 I-- i >~I 含 或 1 及重 1 具 成 第膜 L 第不 i 第液 ο 第尙形 圍矽有圍液 S 圍溶 5 圍，上 範化含範溶一範的 ~ 範後置 利氧液利的i利子%利成位 專成溶專子 L 專粒量專形.的 請形的請粒有請料重請形應 申面子申料含申顔 1 申圖對 如全粒如顔液如 1 爲如料形 .板料.1溶·第度\食：福纖 ο 基顏 1 第的 2 有濃，y^K2'vrt 1該2 1含子1含料.-rl第顏。 中第 中粒 中顔 於 2 驟 其含 其料 其的 係第步 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家揉準（CNS ) A4说格（2】〇Χ297公釐） 8 A8 B8 C8 D8 六、申請專利範圍 第8 4 1 1 3 5 7 8號專利申請案 中文申請專利範圍修正本 民國8 6年J月修正 1 . 一種多結晶薄膜之形成方法，其特徵爲包含；將 包含做爲多結晶化所需之結晶核發揮功能之微結晶之一部 分薄膜形成於絕緣性基板上之製程，與將該薄膜使用退火 加以多結晶化之製程。 2 .如申請專利範園第1項之多結晶薄膜之形成方法 ，其中，在上述多結晶化製程前之上述薄膜，係包含有包 含上述微結晶之微結晶層，與接觸於該微結晶層之非晶質 層。 3.如申請專利範圍第1項之多結晶薄膜之形成方法 ，其中，在上述多結晶化製程前之上述薄膜，係包含有包 含上述微結晶之微結晶層，與堆稹於該微結晶層上之上述 非質晶靨。 4 .如申請專利範圍第1項之多結晶薄膜之形成方法 ，其中，在上述多結晶化製程前之上述薄膜，係包含有非 晶質層，與堆積於該非晶質上，包含上述微結晶之微結晶 層0 5 如申請專利範圍第4項之多結晶薄膜之形成方法 ，其中，上述薄膜，係再包含有將堆稹於該微結晶層上之 其他非晶質層。 6 _如申請專利範圔第2項之多結晶薄膜之形成方法 ，其中，上述微結晶屠係使用CVD法形成。 本紙張尺度逋用中國國家揉率（CNS >A4現格（210x297公瘦） (請先閣讀背面之注意事項再填寫本頁) 訂 線 經濟部中央標準局員工消费合作社印裝 經濟部中央梯準扃貝工消费合作社印装 A8 B8 C8 D8六、申請專利範園 7. 如申請專利範圍第1項之多結晶薄膜之形成方法 ，其中，上述雷射退火，係使用準分子雷射實施。 8. 如申請專利範圍第1項之多結晶薄膜之形成方法 ，其中，上述雷射退火，係將上述絕緣性基板邊維持於約 2 0 0 °C到6 0 0 °C範園內之溫度實施。 9. 如申請專利範圍第1項之多結晶薄膜之形成方法 ，其中，上述薄膜係，由矽或鍺做爲主成分之半導體材料 所形成。 1 0 .如申請·專利範困第1項至第5項任一項之多結 晶薄膜之形成方法，其中，上述微結晶厝之微結晶之平均 結晶粒徑爲2 0 nm以下。 1 1 .如申請專利範園第1項之多結晶薄膜之形成方 法，其中，形成上述薄膜之製程，係包含使用具有結晶化 閩値附近能置密度之雷射光束來退火該非晶質層，藉此， 形成上述微結晶核之製程。 1 2 .如申請專利範圍第2項之多結晶薄膜之形成方 法，其中，形成上述微結晶層之製程，係包含形成非晶質 層之製程，使用具有結晶化閾値附近之能量密度之雷射光 束來退火該非晶質層，藉此，將非晶質層轉換爲上述微結 晶層之製程。 1 3 . —種薄膜電晶體之製造方法，其特徵係包含： 將包含做爲多結晶化所需之結晶核發揮功能之微結晶之一 部分半導體薄膜形成於絕緣性基板上之製程，與將該半導 體薄膜由雷射退火加以多結晶化，藉此，來形成多結晶半 (請先閱讀背面之注意事項再填寫本頁) •^ 訂 線- 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨0X297公釐） A8 B8 C8 D8 六、申請專利範圍 導雔膜之製程，與在該多結晶半導體薄膜中，形成源極領 域，汲極領域，及通道領域之製程。 1 4 ·如申請專利範圍第1 3項之薄膜電晶體之製造 方法，其中，上述多結晶化製程之前上述半導體薄膜，係 包含：包含上述微結晶之微結晶半導體層，與接觸於該微 結晶半導體層之非晶質半導體層。 1 5 .如申請專利範圍第1項之多結晶薄膜之形成方 法，其中，上述微結晶半導體層之微結晶之平均粒徑爲 2 0 n m以下。 (請先閲讀背面之注意事項再填寫本頁) .裝. 訂 線_ 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家橾準（CNS > A4洗格（210X297公釐）Step 8. A method for manufacturing a display surface according to item i of the patent application group, wherein the solution containing the first pigment particles and the solution containing the second pigment particles contain a dispersant. 9. A method for manufacturing a display surface as claimed in item 1 of the patent application, wherein the substrate is formed with an amine silane film in its entirety, and the solution containing the first pigment particles does not contain an adhesion modifier 'and the solution containing the second pigment particles contains fine particles Silicon oxide. Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs, and. , Yan's, and the method of liquid aluminum method 2 method liquid method shape square melt square Fang Fang Fang Fang Tuqi oxygen produced by the production of the material contained in the production system of the child ,. The preparation of the granules for the production of Yanguang's granules 1 of the aluminum particles of the fluorescent fabric micro-faced surface, the second appearance or the adjusted oxygen, the appearance of the display, the second display, the first display, the second display, the second display, and the second display. The sub-% of the granulation 1 item contains I item with micro-item content items are items I--i > ~ I contains or 1 and weighs 1 with a film L No. i No. liquid ο Silicone There are 5 liquids in the surrounding liquid S, and the standardization contains a range of the standard solution ~ the post-positioning of the oxygen solution, the profit rate, the profit rate, the special solution, the special solution, the special particle amount, the special shape. If the grain is available, please re-form the application form and apply for the face. The application form contains Shen Yan 1 and the application plan is like the whole grain, such as Yan Ye, such as 1 is as expected. Sheet material. 1 dissolve · first degree \ food: Fu Yan ο base Yan 1 The 2 is strong, y ^ K2'vrt 1 The 2 1 Contains 1 Contains.-rl 第 yan. In the second step of the middle and middle grains, it is the first step (please read the precautions on the back and then fill out this page). This paper size is applicable to China National Standard (CNS) A4 (2). Χ297mm) 8 A8 B8 C8 D8 VI. Patent application No. 8 4 1 1 3 5 7 8 Patent application No. 8 Chinese application Patent scope amendment The Republic of China 1986 June amendment 1. A method of forming a polycrystalline film, It is characterized by a process of forming a part of a thin film containing microcrystals functioning as crystal nuclei required for polycrystallization on an insulating substrate, and a process of polycrystallizing the thin film using annealing. 2. The method for forming a polycrystalline thin film according to item 1 of the patent application park, wherein the thin film before the polycrystallization process includes a microcrystalline layer including the microcrystalline, and the microcrystalline layer in contact with the microcrystalline layer Of the amorphous layer. 3. The method for forming a polycrystalline thin film as claimed in item 1 of the patent scope, wherein the thin film before the polycrystallization process includes a microcrystalline layer containing the above microcrystals and stacked on the microcrystalline layer On the above-mentioned amorphous crystal. 4. The method for forming a polycrystalline thin film as claimed in item 1 of the patent scope, wherein the thin film before the polycrystallization process includes an amorphous layer, and the amorphous layer deposited on the amorphous layer contains the microcrystalline The microcrystalline layer 0 5 is a method for forming a polycrystalline thin film according to item 4 of the patent application, wherein the thin film further includes other amorphous layers stacked on the microcrystalline layer. 6 _ The method for forming a polycrystalline thin film as claimed in item 2 of the patent application, wherein the above microcrystalline sludge is formed by CVD method. This paper uses the Chinese national rubbing rate (CNS> A4) (210x297 male thin) (please read the precautions on the back first and then fill out this page). Threading Ministry of Economy Central Standards Bureau Employee Consumer Cooperative Printed by the Ministry of Economy Central Printed and printed A8, B8, C8, D8 by the Tien Pui Pongong Consumer Cooperatives 6. Patent application park 7. The method for forming a polycrystalline film as described in item 1 of the patent application, in which the above laser annealing is implemented using an excimer laser 8. The method for forming a polycrystalline thin film as claimed in item 1 of the patent scope, wherein the above-mentioned laser annealing maintains the edge of the above-mentioned insulating substrate within a range of about 200 ° C to 600 ° C Temperature implementation 9. The method of forming a polycrystalline thin film as described in item 1 of the patent application scope, in which the above-mentioned thin film is formed of a semiconductor material containing silicon or germanium as the main component. The method for forming a polycrystalline thin film according to any one of items 1 to 5, wherein the average crystal grain size of the microcrystals of the above microcrystals is 20 nm or less. Crystalline film formation method, Among them, the process of forming the above-mentioned thin film includes the process of forming the microcrystalline core by annealing the amorphous layer with a laser beam having a density capable of crystallizing near the Min. 1 2. Item 2 is a method of forming a polycrystalline thin film, wherein the process of forming the above-mentioned microcrystalline layer includes a process of forming an amorphous layer, and the amorphous layer is annealed using a laser beam having an energy density near the crystallization threshold, In this way, the process of converting the amorphous layer into the above-mentioned microcrystalline layer. 1 3. A method for manufacturing a thin film transistor, characterized in that it includes: a microstructure that functions as a crystal nucleus required for polycrystallization The process of forming a part of the semiconductor film on an insulating substrate, and polycrystallizing the semiconductor film by laser annealing to form a polycrystalline half (please read the precautions on the back before filling this page) • ^ Threading-This paper scale is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) A8 B8 C8 D8 6. The process of applying patent scope for the guide film, In this polycrystalline semiconductor thin film, the process of forming the source field, the drain field, and the channel field is formed. 1 4 · A method for manufacturing a thin film transistor as claimed in item 13 of the patent scope, wherein the above polycrystallization process The above semiconductor thin film includes: a microcrystalline semiconductor layer including the above microcrystal, and an amorphous semiconductor layer in contact with the microcrystalline semiconductor layer. 1 5. A method for forming a polycrystalline thin film as described in item 1 of the patent scope, Among them, the average particle size of the microcrystals of the above microcrystalline semiconductor layer is below 20 nm. (Please read the precautions on the back before filling out this page). Packing. Threading _ Printed by the Staff Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs The paper scale is applicable to the Chinese National Standard (CNS > A4 wash grid (210X297mm)
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