JPH07183481A - Solid-state image sensing device - Google Patents
Solid-state image sensing deviceInfo
- Publication number
- JPH07183481A JPH07183481A JP5323582A JP32358293A JPH07183481A JP H07183481 A JPH07183481 A JP H07183481A JP 5323582 A JP5323582 A JP 5323582A JP 32358293 A JP32358293 A JP 32358293A JP H07183481 A JPH07183481 A JP H07183481A
- Authority
- JP
- Japan
- Prior art keywords
- type
- region
- conductivity type
- transfer gate
- type well
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007547 defect Effects 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000006243 chemical reaction Methods 0.000 claims abstract description 10
- 239000000969 carrier Substances 0.000 claims abstract description 6
- 238000003384 imaging method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、固体撮像装置に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device.
【0002】[0002]
【従来の技術】従来、CCD型の固体撮像装置は、図3
に示す構造を有していた。図3において1はN型シリコ
ン基板で、2はP型ウェル、3は光電変換素子のN型領
域で4−1,4−2はP+ 型チャネルストッパ、5は信
号転送部(CCD垂直レジスタ)のN型埋め込み層、8
はCCDの転送ゲート電極である。実効的な光電変換領
域は、N型領域3、P+ 型領域(4−1,4−2)及び
P型ウェル2内でN型領域周辺の活性領域である。そし
てN型シリコン基板1はP型ウェル2に対して逆バイア
スされている。よってN型シリコン基板1とP型ウェル
2との間に形成される空乏層領域で発生した負電荷は、
N型シリコン基板へ排出される。2. Description of the Related Art Conventionally, a CCD type solid-state image pickup device is shown in FIG.
It had the structure shown in. In FIG. 3, 1 is an N-type silicon substrate, 2 is a P-type well, 3 is an N-type region of a photoelectric conversion element, 4-1 and 4-2 are P + -type channel stoppers, and 5 is a signal transfer unit (CCD vertical register). ) N-type buried layer, 8
Is a transfer gate electrode of the CCD. The effective photoelectric conversion region is the N-type region 3, the P + -type regions (4-1, 4-2) and the active region around the N-type region in the P-type well 2. The N-type silicon substrate 1 is reverse biased with respect to the P-type well 2. Therefore, the negative charge generated in the depletion layer region formed between the N-type silicon substrate 1 and the P-type well 2 is
It is discharged to the N-type silicon substrate.
【0003】[0003]
【発明が解決しようとする課題】このような従来の構造
では、例えば図3に示す様な光が入射した時、活性領域
外(P型ウェル2のうち固体撮像装置の動作時に空乏化
されない領域)下部で光電変換により発生した電荷の一
部が、拡散によりN型埋め込み層5に入り、スミアを発
生するという問題点があった。In such a conventional structure, when light such as that shown in FIG. 3 is incident, for example, a region outside the active region (a region of the P-type well 2 that is not depleted during the operation of the solid-state imaging device). ) There is a problem that a part of the charges generated by photoelectric conversion in the lower portion enters the N-type buried layer 5 by diffusion and causes smear.
【0004】本発明の目的は、CCDの駆動安定性を損
なう事なく、スミアを抑制した固体撮像装置を提供する
ことにある。It is an object of the present invention to provide a solid-state image pickup device in which smear is suppressed without impairing the driving stability of CCD.
【0005】[0005]
【課題を解決するための手段】本発明は、第1導電型半
導体基板の表面部に設けられた第2導電型ウェルと、前
記第2導電型ウェルの表面部に選択的に形成された第1
導電型領域を含む光電変換素子を複数列状に配置した感
光部と、前記第2導電型ウェルの表面部に前記第1導電
型領域と離れ前記感光部と平行に形成された第1導電型
埋め込みチャネル層および前記第1導電型埋め込みチャ
ネル層表面にゲート絶縁膜を介して配置された複数の転
送ゲート電極を含むCCD垂直レジスタと、前記光電変
換素子から信号電荷を読み出して前記CCD垂直レジス
タに供給するトランスファゲートとを有する固体撮像装
置において、前記第2導電型ウェルの前記第1導電型領
域、第1導電型埋め込みチャネル層またはトランスファ
ゲートの下方で駆動時に空乏化されない領域にキャリア
が再結合する欠陥層が設けられているというものであ
る。According to the present invention, there is provided a second conductivity type well provided on a surface part of a first conductivity type semiconductor substrate, and a second conductivity type well selectively formed on the surface part of the second conductivity type well. 1
A photosensitive part in which photoelectric conversion elements including conductive type regions are arranged in a plurality of rows, and a first conductive type formed on the surface of the second conductive type well apart from the first conductive type region and in parallel with the photosensitive part. A CCD vertical register including a buried channel layer and a plurality of transfer gate electrodes arranged on the surface of the first conductivity type buried channel layer via a gate insulating film, and a signal charge is read from the photoelectric conversion element to the CCD vertical register. In a solid-state imaging device having a transfer gate for supplying carriers, carriers recombine in the first conductivity type region of the second conductivity type well, the first conductivity type buried channel layer, or a region below the transfer gate that is not depleted during driving. That is, a defective layer is provided.
【0006】[0006]
【作用】欠陥層が電子−正孔対の再結合領域として働く
ため、活性領域外で発生した電子、正孔のトランスファ
ゲート領域及び第1導電型埋め込み領域への流入を防ぐ
事ができその結果としてスミアを低減できる。Since the defect layer functions as a recombination region of electron-hole pairs, it is possible to prevent electrons and holes generated outside the active region from flowing into the transfer gate region and the first conductivity type buried region. As a result, smear can be reduced.
【0007】[0007]
【実施例】図1は本発明の一実施例のCCD型固体撮像
装置の模式的断面図である。1 is a schematic sectional view of a CCD type solid-state image pickup device according to an embodiment of the present invention.
【0008】この実施例は、不純物濃度2×1014/c
m3 のN型シリコン基板1の表面部に設けられた深さ2
〜3μm、不純物濃度1×1015〜1×1016/cm3
のP型ウェル2と、P型ウェル2の表面部に選択的に形
成されたN型領域3(厚さ0.5〜1.0μm、不純物
濃度2×1016/cm3 )、を含む光電変換素子を複数
列状に配置した感光部と、P型ウェル2の表面部にN型
領域と離れ前述の感光部と平行に形成されたN型埋め込
みチャネル層5(深さ0.2〜0.3μm、不純物濃度
1×1017/cm3 )およびN型埋め込みチャネル層表
面5のゲート絶縁膜7を介して配置された複数の転送ゲ
ート電極8(紙面と垂直方向にこのような転送ゲート電
極が複数配置)を含むCCD垂直レジスタと、前述の光
電変換素子から信号電荷を読み出して前述のCCD垂直
レジスタに供給するトランスファゲート(トランスファ
ゲート領域6とその上の転送ゲート電極8の張出し部)
とを有する固体撮像装置において、P型ウェル2のN型
領域3、N型埋め込みチャネル層5またはトランスファ
ゲート領域6の下方で駆動時に空乏化されない領域にキ
ャリアが再結合する欠陥層9が設けられているというも
のである。In this embodiment, the impurity concentration is 2 × 10 14 / c.
Depth 2 provided on the surface of the m 3 N-type silicon substrate 1
-3 μm, impurity concentration 1 × 10 15 -1 × 10 16 / cm 3
Of the P-type well 2 and the N-type region 3 (thickness 0.5 to 1.0 μm, impurity concentration 2 × 10 16 / cm 3 ) selectively formed on the surface of the P-type well 2. A photosensitive portion in which the conversion elements are arranged in a plurality of rows and an N-type buried channel layer 5 (depth 0.2 to 0) formed in parallel with the photosensitive portion apart from the N-type region on the surface portion of the P-type well 2. .3 μm, impurity concentration 1 × 10 17 / cm 3 ) and a plurality of transfer gate electrodes 8 (such a transfer gate electrode in a direction perpendicular to the plane of the drawing) that is arranged via the gate insulating film 7 on the surface 5 of the N-type buried channel layer. And a transfer gate (a transfer gate region 6 and an overhanging portion of the transfer gate electrode 8 on the transfer gate region 6) that reads out signal charges from the photoelectric conversion element and supplies the signal charges to the CCD vertical register.
In the solid-state imaging device having the above, a defect layer 9 in which carriers recombine is provided below the N-type region 3, the N-type buried channel layer 5 or the transfer gate region 6 of the P-type well 2 in a region that is not depleted during driving. It is that.
【0009】N型領域3上のP+ 型チャネルストッパ4
−2の厚さは0.1〜0.2μm、不純物濃度は1×1
018/cm3 である。A P + type channel stopper 4 on the N type region 3
-2 has a thickness of 0.1 to 0.2 μm and an impurity concentration of 1 × 1
It is 0 18 / cm 3 .
【0010】次に、欠陥層9の形成方法について述べ
る。Next, a method of forming the defect layer 9 will be described.
【0011】図2に示すように、N型領域3,N型埋め
込みチャネル層5等の形成終了後にレジスト膜10を形
成してそれとマスクにしてSiイオンを650keVで
少なくとも1×1013/cm2 打込み、800℃以下の
温度でアニールする。Siイオンを注入された部分は多
結晶シリコン領域または非晶質シリコン領域として残
る。こうして形成された欠陥層(P型ウェル領域2の表
面から約1μmの深さの位置にできる)には多数の再結
合中心が存在する。As shown in FIG. 2, a resist film 10 is formed after the formation of the N-type region 3 and the N-type buried channel layer 5 and the like, and using this as a mask, Si ions are at least 1 × 10 13 / cm 2 at 650 keV. Implantation and annealing at a temperature of 800 ° C. or less. The portion implanted with Si ions remains as a polycrystalline silicon region or an amorphous silicon region. A large number of recombination centers are present in the defect layer thus formed (which can be located at a depth of about 1 μm from the surface of the P-type well region 2).
【0012】Si以外にアルゴンなどの不活性イオンな
どSi中で不活性な原子または分子のイオン注入を行な
うことによっても欠陥層を形成することができる。な
お、本実施例では、N型シリコン基板1とP型ウェル基
板2との間に印加される逆バイアス電圧は約8ボルト、
転送ゲート電極に加わる電圧のパルス高は約9ボルトで
ある。The defect layer can also be formed by implanting atoms or molecules that are inactive in Si such as inactive ions such as argon in addition to Si. In this embodiment, the reverse bias voltage applied between the N-type silicon substrate 1 and the P-type well substrate 2 is about 8 V,
The pulse height of the voltage applied to the transfer gate electrode is about 9 volts.
【0013】また、実施例ではPウェル型固体撮像装置
について述べたが、P型基板を用いたNウェル型固体撮
像装置においても同様な効果が得られる事は明白であ
る。Further, although the P-well type solid-state image pickup device has been described in the embodiment, it is obvious that the same effect can be obtained also in the N-well type solid-state image pickup device using the P-type substrate.
【0014】[0014]
【発明の効果】以上のように本発明によれば、固体撮像
装置のウェル領域のうち活性領域外の場所に欠陥層を設
けることによりスミアを抑制する事ができ、画質を一層
改善する事ができる効果がある。As described above, according to the present invention, the smear can be suppressed by providing the defect layer at a position outside the active region in the well region of the solid-state image pickup device, and the image quality can be further improved. There is an effect that can be done.
【図1】本発明の一実施例を示す断面図である。FIG. 1 is a sectional view showing an embodiment of the present invention.
【図2】一実施例における欠陥層の形成方法の説明のた
めの断面図である。FIG. 2 is a cross-sectional view for explaining a method of forming a defect layer in an example.
【図3】従来例を示す断面図である。FIG. 3 is a cross-sectional view showing a conventional example.
1 N型シリコン基板 2 P型ウェル 3 N型領域 4−1,4−2 P+ チャネルストッパ 5 N型埋め込みチャネル 6 トランスファゲート領域 7 ゲート絶縁膜 8 転送ゲート電極 9 欠陥層 10 レジスト膜1 N-type silicon substrate 2 P-type well 3 N-type region 4-1, 4-2 P + channel stopper 5 N-type buried channel 6 transfer gate region 7 gate insulating film 8 transfer gate electrode 9 defect layer 10 resist film
Claims (2)
れた第2導電型ウェルと、前記第2導電型ウェルの表面
部に選択的に形成された第1導電型領域を含む光電変換
素子を複数列状に配置した感光部と、前記第2導電型ウ
ェルの表面部に前記第1導電型領域と離れ前記感光部と
平行に形成された第1導電型埋め込みチャネル層および
前記第1導電型埋め込みチャネル層表面にゲート絶縁膜
を介して配置された複数の転送ゲート電極を含むCCD
垂直レジスタと、前記光電変換素子から信号電荷を読み
出して前記CCD垂直レジスタに供給するトランスファ
ゲートとを有する固体撮像装置において、前記第2導電
型ウェルの前記第1導電型領域、第1導電型埋め込みチ
ャネル層またはトランスファゲートの下方で駆動時に空
乏化されない領域にキャリアが再結合する欠陥層が設け
られていること特徴とする固体撮像装置。1. A photoelectric conversion including a second conductivity type well provided on a surface part of a first conductivity type semiconductor substrate and a first conductivity type region selectively formed on a surface part of the second conductivity type well. A photosensitive portion in which elements are arranged in a plurality of rows; a first conductive type buried channel layer formed in parallel with the photosensitive portion on the surface portion of the second conductive type well apart from the first conductive type region; CCD including a plurality of transfer gate electrodes arranged on the surface of a conductive type buried channel layer via a gate insulating film
In a solid-state imaging device having a vertical register and a transfer gate for reading signal charges from the photoelectric conversion element and supplying the signal charges to the CCD vertical register, the first conductivity type region and the first conductivity type buried in the second conductivity type well. A solid-state imaging device comprising a defect layer in which carriers are recombined in a region which is not depleted during driving under a channel layer or a transfer gate.
請求項1記載の固体撮像装置。2. The solid-state imaging device according to claim 1, wherein the defect layer is an amorphous layer or a polycrystalline layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5323582A JP2906961B2 (en) | 1993-12-22 | 1993-12-22 | Solid-state imaging device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5323582A JP2906961B2 (en) | 1993-12-22 | 1993-12-22 | Solid-state imaging device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07183481A true JPH07183481A (en) | 1995-07-21 |
JP2906961B2 JP2906961B2 (en) | 1999-06-21 |
Family
ID=18156322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5323582A Expired - Lifetime JP2906961B2 (en) | 1993-12-22 | 1993-12-22 | Solid-state imaging device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2906961B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117319824A (en) * | 2023-08-31 | 2023-12-29 | 北京空间机电研究所 | Low-noise large-full-well TDI-CMOS image sensor reading circuit |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51128221A (en) * | 1975-05-01 | 1976-11-09 | Sony Corp | Solid state image pickup device |
JPS59113662A (en) * | 1982-12-20 | 1984-06-30 | Sanyo Electric Co Ltd | Solid state image pickup element |
JPH02105572A (en) * | 1988-10-14 | 1990-04-18 | Nec Corp | Solid state image pickup device |
-
1993
- 1993-12-22 JP JP5323582A patent/JP2906961B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51128221A (en) * | 1975-05-01 | 1976-11-09 | Sony Corp | Solid state image pickup device |
JPS59113662A (en) * | 1982-12-20 | 1984-06-30 | Sanyo Electric Co Ltd | Solid state image pickup element |
JPH02105572A (en) * | 1988-10-14 | 1990-04-18 | Nec Corp | Solid state image pickup device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN117319824A (en) * | 2023-08-31 | 2023-12-29 | 北京空间机电研究所 | Low-noise large-full-well TDI-CMOS image sensor reading circuit |
Also Published As
Publication number | Publication date |
---|---|
JP2906961B2 (en) | 1999-06-21 |
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