JP2641416B2 - Photoelectric conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device for storing carriers generated by light incidence and reading out a signal based on the stored carriers.

[0002]

2. Description of the Related Art In recent years, research on photoelectric conversion devices, particularly solid-state imaging devices, has been actively conducted with the progress of semiconductor technology, and some of them have begun to be put into practical use. These solid-state imaging devices can be broadly classified into two types: CCD type and MOS type. The CCD type imaging device forms a potential well under the MOS capacitor electrode, accumulates the charge generated by the incidence of light in this well, and sequentially moves these potential wells by a pulse applied to the electrode during reading. The principle is that the accumulated electric charges are transferred to the output amplifier and read. Some CCD imaging devices use a pn junction diode structure for the light receiving unit and a CCD structure for the transfer unit.
On the other hand, the MOS type imaging device has a pn
The charge generated by the incidence of light is accumulated in each of the photodiodes formed of junctions, and at the time of reading, the accumulated charges are read out to the output amplifier section by sequentially turning on MOS switching transistors connected to the respective photodiodes. That principle is used.

The CCD type image pickup device has a relatively simple structure, and from the viewpoint of noise that can be generated, only the capacitance value of the charge detector composed of the floating diffusion in the final stage contributes to random noise. This is a relatively low-noise imaging device, and is capable of low-illuminance imaging. However, MOS-type amplifiers are used on-chip as output amplifiers due to process restrictions for manufacturing CCD-type imaging devices, and 1 / f noise that is easily visible on the image from the interface between silicon and the SiO ₂ film I do. Therefore, although the noise is low, there is a limit in its performance. Also,
If the density is increased by increasing the number of cells to achieve higher resolution, the maximum amount of charge that can be stored in one potential well decreases, and the dynamic range cannot be obtained.
In the future, it will be a big problem in increasing the resolution of the solid-state imaging device. In addition, since the CCD type image pickup device transfers the accumulated charge while sequentially moving the potential well, even if one of the cells has a defect, the charge transfer is stopped there, or an extreme In addition, there is a disadvantage that the production yield is not improved.

On the other hand, the MOS type imaging device is slightly more complicated in structure than a CCD type imaging device, especially a frame transfer type device, but can be configured to have a large storage capacity, It has the advantage of having a wide range. Even if one of the cells has a defect, the XY address system does not affect other cells due to the defect, which is advantageous in terms of manufacturing yield. However, in this MOS type imaging device, since a wiring capacitance is connected to each photodiode at the time of signal reading, an extremely large signal voltage drop occurs, the output voltage is reduced, and the wiring capacitance is large, resulting in random noise. Drawbacks, and fixed pattern noise due to variations in the parasitic capacitance of each photodiode and MOS switching transistor for horizontal scanning, etc., making low-illuminance imaging difficult compared to CCD-type imaging devices. have.

[0005] Further, in the future improvement of the resolution of the imaging device, the size of each cell is reduced, and the accumulated charge is reduced. On the other hand, the wiring capacitance determined by the chip size does not decrease so much even if the line width is reduced. For this reason, the MOS type image pickup device is disadvantageous in terms of S / N.

[0006] The CCD type and MOS type imaging devices have the advantages and disadvantages described above, but are gradually approaching the level of practical use. However, it can be said that there is an essentially large problem in further increasing the resolution required in the future. In contrast, regarding solid-state imaging devices,
Japanese Patent Application Laid-Open No. 56-150878, “Semiconductor imaging device”,
JP-A-56-157073, “Semiconductor imaging device”,
A new system has been proposed in Japanese Patent Application Laid-Open No. Sho 56-165473, entitled "Semiconductor Imaging Device". CCD-type and MOS-type imaging devices accumulate charges generated by light incidence on a main electrode (for example, the source of a MOS transistor).
In the method proposed here, a charge generated by light incidence is transferred to a control electrode (for example, a base of a bipolar transistor, a SIT (static induction transistor) or a MOS transistor).
It is based on a new idea of controlling the flowing current by the charge generated by light accumulated in the gate of a transistor). That is, CCD type, M
The OS type reads out the stored charge itself to the outside, whereas the method proposed here reads out the stored charge after amplifying the charge by the amplification function of each cell. From another point of view, a low impedance output is read out by impedance conversion.
Therefore, the method proposed here has a high output, a wide dynamic range, and low noise, and non-destructive reading is possible because carriers (charges) excited by an optical signal are accumulated in the control electrode. Has several advantages. Furthermore, it can be said that this method has a possibility for a higher resolution in the future.

[0007]

However, this system is basically an XY address system, and the element structure described in the above-mentioned publication discloses that each cell of a conventional MOS type imaging device has a bipolar transistor, The basic configuration is a composite of amplification elements such as SIT transistors.
Therefore, it has a relatively complicated structure and has a possibility of high resolution, but there is a limit to high resolution as it is.

An object of the present invention is to provide a new photoelectric conversion device which has an amplifying function in each cell but has a very simple structure, and which can sufficiently cope with future high resolution.

[0009]

An object of the present invention is to provide a semiconductor device having a base region made of a semiconductor of a first conductivity type, and an emitter and a collector region made of a semiconductor of a second conductivity type different from the first conductivity type. A photoelectric conversion device comprising a transistor capable of accumulating carriers generated by receiving light energy in the base region, performing an accumulation operation, a read operation, and a refresh operation, wherein an impurity concentration of the base region is higher than a light incident surface. When the impurity concentration at the light incident surface is N _AS and the impurity concentration at the interface with the collector region is N _Ai , N _AS / N _Ai >
The photoelectric conversion device is characterized in that the base region has an impurity concentration profile that satisfies the relationship of 3.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIGS. 1 to 3 are diagrams illustrating the basic structure and operation of a photosensor cell constituting a photoelectric conversion device according to an embodiment of the present invention. 1 is a plan view of an optical sensor cell, FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG. 1, and FIG. 3 is an equivalent circuit thereof. In addition, the same numbers are given to the parts common to FIGS. 1 to 3 in each part.

FIG. 1 shows a plan view of the arrangement arrangement method. However, in order to increase the horizontal resolution, it is needless to say that the arrangement can also be performed by a pixel shift method (interpolation arrangement method). As shown in FIGS. 1 and 2, this optical sensor cell is formed on an n-type or n ⁺ -type silicon substrate 1 doped with impurities such as phosphorus (P), antimony (Sb), and arsenic (As). A passivation film 2 usually composed of a PSG film or the like; an insulating oxide film 3 made of a silicon oxide film (SiO ₂ ); SiO ₂ or Si ₃ N ₄ for electrically insulating a neighboring optical sensor cell; Isolation region 4 composed of an insulating film or a polysilicon film made of, for example, n having a low impurity concentration formed by an epitaxial technique or the like.
^A region 5; a p region 6 serving as a base of a bipolar transistor doped with an impurity such as boron (B) by using, for example, an impurity diffusion technique or an ion implantation technique; formed by an impurity diffusion technique, an ion implantation technique, or the like. N ⁺ region 7 serving as an emitter of the bipolar transistor; for example, aluminum (A)
1) a wiring 8 formed of a conductive material such as Al-Si, Al-Cu-Si; an electrode 9 for applying a pulse to the floating p region 6 through the insulating film 3; a wiring 10 thereof An n ⁺ region 1 having a high impurity concentration formed by an impurity diffusion technique or the like to make ohmic contact with the back surface of the substrate 1;
1; an electrode 12 made of a conductive material such as aluminum for giving a potential of a substrate, that is, giving a collector potential of a bipolar transistor;

Reference numeral 19 in FIG. 1 denotes a contact portion for connecting the n ⁺ region 7 and the wiring 8. Alternate portions of the wiring 8 and the wiring 10 are so-called two-layer wirings, and are insulating regions formed of an insulating material such as SiO ₂ .
Each is insulated from each other. That is, it has a metal two-layer wiring structure.

The capacitor Cox13 of the equivalent circuit of FIG. 3 has a MOS structure of the electrode 9, the insulating film 3 and the p region 6, and the bipolar transistor 14 has an n ⁺ region 7 as an emitter, a p region 6 as a base, and an impurity. It is composed of an n ⁻ region 5 having a low concentration and n or n ⁺ region 1 as a collector. As is apparent from these drawings, the p region 6 is a floating region.

In the second equivalent circuit of FIG. 3, a bipolar transistor 14 is connected to a base-emitter junction capacitance Cbe1.
5. Base-emitter pn junction diode Dbe1
6, the junction capacitance Cbc17 of the base and the collector,
This is expressed using a collector pn junction diode Dbc18. Here, as an equivalent circuit diagram, p
n-junction diode Dbe16 and pn-junction diode D
Symbols indicating two differently oriented current sources to be written in parallel with bc18 have been omitted.

The basic operation of the optical sensor cell will be described below with reference to FIGS. The basic operation of this optical sensor cell is
It consists of a charge accumulation operation by light incidence, a read operation, and a refresh operation. First, the charge storage operation will be described. In the charge storage operation, for example, the emitter is grounded through the wiring 8 and the collector is biased to a positive potential through the wiring 12. The base is assumed to be in a negative potential, that is, in a reverse bias state with respect to the emitter 7, by applying a positive pulse voltage to the capacitor Cox13 through the wiring 10 in advance. The operation of applying a pulse to the Cox 13 to bias the base 6 to a negative potential will be described in detail later in the description of the refresh operation.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 2, electron-hole pairs are generated in the semiconductor. Among them, electrons flow toward the n-region 1 because the n-region 1 is biased to a positive potential, but holes are accumulated more and more in the p-region 6. Due to the accumulation of the holes in the p region, the potential of the p region 6 gradually changes toward the positive potential.

In FIGS. 1 and 2, the lower surface of the light receiving surface of each sensor cell is almost entirely occupied by the p region, and is partially n ⁺ region 7.
It has become. Of course, the electron hole pair concentration excited by light is greater near the surface. Therefore, many electron-hole pairs are also excited by light in the p region 6. If the photoexcited electrons in the p region flow out of the p region 6 immediately without recombination and are absorbed in the n region, the holes excited in the p region 6 are accumulated as they are. The p region 6 is changed in the positive potential direction. When the impurity concentration in p region 6 is uniform, electrons excited by light flow by diffusion to the pn ^- junction between p region 6 and n ^- region 5, and then join the n ^- region. Is absorbed by the n-collector region 1 due to the drift caused by the strong electric field. Of course, the electrons in the p region 6 may travel only by diffusion. However, if the p-type impurity concentration is reduced from the surface to the inside, the difference in impurity concentration may cause the difference in impurity concentration. An electric field Ed from inside to the surface in the base, Occurs. Here, W _B is the depth from the light incident side surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, N _AS surface impurity concentration of the p base region 6, N _Ai
Is the impurity concentration at the interface between the p region 6 and the n ⁻ high resistance region 5.

[0018] Here, if N _AS / N _Ai> 3, electrons travel in the p region 6 becomes as performed by drift rather than diffusion. That is, in order to effectively operate carriers excited by light in the p region 6 as a signal,
It is desirable that the impurity concentration of the p region 6 decreases from the light incident side surface toward the inside. When the p region 6 is formed by diffusion, the impurity concentration decreases toward the inside as compared with the light incident side surface.

A part below the light receiving surface of the sensor cell is occupied by the n ⁺ region 7. Normally, the depth of the n ⁺ region 7 is 0.
Since it is designed to be about 2 to 0.3 μm or less, the amount of light absorbed in the n ⁺ region 7 is not so large from the beginning, so there is no problem. However, for light on the short wavelength side, particularly for blue light, the presence of the n ⁺ region 7 causes a decrease in sensitivity. The impurity concentration of n ⁺ region 7 is usually 1 × 1
It is designed to be about ²⁰ cm ^-3 or more. The diffusion distance of holes in n ⁺ region 7 doped with such a high concentration of impurity is about 0.15 to 0.2 μm. Therefore, the pouring hole which is photoexcited in the n ⁺ region 7 to enable the p region 6, n ⁺ region 7 may be desirable that the impurity concentration toward the interior has a structure to decrease from the light incident surface. If the impurity concentration distribution in the n ⁺ region 7 is as described above, a strong drift electric field is generated from the light incident side surface toward the inside, and the holes photo-excited in the n ⁺ region 7 are immediately shifted to the p region 6 by the drift. Flow into If the impurity concentration of each of the n ⁺ region 7 and the p region 6 is configured to decrease from the light incident side surface toward the inside, the n ⁺ region 7 and the p region existing on the light incident side surface side of the sensor cell. All the carriers photo-excited at 6 work effectively as optical signals. When this n ⁺ region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film doped with As or P at a high concentration, it is possible to obtain an n ⁺ region having a desirable impurity gradient as described above. It is.

Eventually, the base potential changes to the emitter potential due to the accumulation of holes, and in this case, changes to the ground potential and is clipped there. More specifically, the base-emitter is deeply biased in the forward direction, and is clipped at a voltage at which holes accumulated in the base start to flow out to the emitter. That is, the saturation potential of the photosensor cell in this case is substantially given by the potential difference between the bias potential when the p region 6 is initially biased to the negative potential and the ground potential. In the case where the n ⁺ region 7 is not grounded and the charge generated by the light input is stored in a floating state, the p region 6 can store the charge to approximately the same potential as the n region 1.

The above is a qualitative outline of the charge storage operation. The following is a slightly more specific and quantitative description. The spectral sensitivity distribution of this optical sensor cell is given by the following equation. λ S (λ) = {· exp (−αx) × {1-exp (−αy)} · T 1.24 [A / W] where λ is the wavelength of light [μm] and α is silicon The light extinction coefficient [μm ⁻¹ ], x in the crystal is “deadlay” which causes recombination loss at the semiconductor surface and does not contribute to sensitivity.
r ”(dead area) thickness [μm], y is the thickness of the epitaxial layer [μm], and T is the transmittance, that is, it is effectively incident on the semiconductor in consideration of the reflection of the incident light amount. The photocurrent Ip is calculated using the spectral sensitivity S (λ) and the irradiance Ee (λ) of the photosensor cell according to the following equation.

[0022] Here, the irradiance Ee (λ) [μW · cm ⁻² · nm ⁻¹ ] is given by the following equation.

[0023] However E _V illuminance of the light receiving surface of the sensor [Lux], P (lambda)
Is the spectral distribution of light incident on the light receiving surface of the sensor, V
(Λ) is the relative luminous efficiency of the human eye.

Using these equations, for an optical sensor cell having an epitaxially thick layer of 4 μm, the A light source (2854
° K), and when the illuminance of the light receiving surface of the sensor is 1 [Lux], a photocurrent of about 280 nA / cm ^-2 flows. It is about 8 × 10 ¹² / cm ² · sec.

At this time, the potential Vp generated by the accumulation of holes excited by light in the base is Vp = Vp
It is given by Q / C. Q is the amount of charge stored in the holes, and C is the junction capacitance obtained by adding Cbe15 and Cbc17. Now, the impurity concentration of the n ⁺ region 7 is set to 10 ²⁰ cm ⁻³ ,
The impurity concentration of 5 × 10 ¹⁶ cm ^-3 in the p region 6, n ^- region 5
Impurity concentration of 10 ¹³ cm ⁻³ , and the area of n ⁺ region 7 is 16
μm ² , the area of the p region 6 is 64 μm ² , and the thickness of the n ⁻ region 5 is 3 μm, the junction capacitance is about 0.014 pF, while the number of holes accumulated in the p region 6 is ,
The accumulation time is 1/60 sec, the effective light receiving area, that is, the area obtained by subtracting the areas of the electrodes 8 and 9 from the area of the p region 6 is 5
If it is about 6 μm ^2, it will be 1.7 × 10 ⁴ . Therefore, the potential Vp generated by light incidence is about 190 mV.

It should be noted here that when the resolution is increased and the cell size is reduced, the amount of light incident on one photosensor cell decreases, and the accumulated charge amount Q
Both decrease, but as the cell size decreases, the junction capacitance also decreases in proportion to the cell size, so that the potential Vp generated by light incidence is substantially constant. This is because the optical sensor cell according to the present invention has a very simple structure as shown in FIGS. 1 to 3 and has a possibility that an effective light receiving surface can be extremely large.

One of the reasons why the photoelectric conversion device of the present invention is more advantageous than the case of the interline type CCD is heretofore. If an attempt is made to secure the charge amount, the area of the transfer portion becomes relatively large, and the effective light receiving surface is reduced. Therefore, the sensitivity, that is, the voltage generated by light incidence is reduced. Also,
In the case of the interline type CCD image pickup device, the saturation voltage is limited by the size of the transfer section and decreases steadily. The saturation voltage is determined by the bias voltage when the p region 6 is biased to a negative potential, and a large saturation voltage can be secured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above to the outside will now be described. In the read operation state, the emitter and the wiring 8 are in a floating state, and the collector is maintained at the positive potential Vcc. FIG. 4 shows an equivalent circuit. Also here, pn
Junction diode Dbe16 and pn junction diode Db
Symbols indicating two differently oriented current sources to be written in parallel with c18 have been omitted.

[0029] Now, before irradiating light, the potential at the time of biasing the base 6 at a negative potential and -V _B, when the storage voltage generated by light irradiation and V _P, the base potential, -V _B
+ Has become V _P become potential. When a positive voltage is applied to V _R for reading the electrode 9 through the wiring 10 in this state, the capacitance by the positive potential V _R oxide capacitance Cox13 and the base-emitter junction capacitance Cbe15, base-collector junction capacitance Cbc7 Divided, voltage on base If the following condition is satisfied, the base potential becomes the accumulated voltage _VP itself generated by light irradiation. When the base potential is biased in the positive direction with respect to the emitter potential in this way, electrons are injected from the emitter into the base, and the collector potential is positive. To reach. The current flowing at this time is given by the following equation.

[0030] Where A _j is the junction area between the base and the emitter, q is the unit charge (1.6 × 10 ⁻¹⁹ coulomb), D _n is the electron diffusion constant in the base, and n _Pe is the minority carrier at the emitter end of the p base. Electron concentration as, W _B is base width, N _Ae is the acceptor concentration in the base of the emitter single, N _Ac is acceptor concentration, k is the Boltzmann constant at the base of the collector end, T is the absolute temperature,
V _e is the emitter potential.

The current is such that the emitter potential V _e is the base potential, that is, the accumulated voltage V generated by light irradiation here.
It is evident from the above equation that the current flows until it becomes equal to _P. Temporal variation of this time the emitter potential V _e is calculated by the following equation. Here, the wiring capacitance Cs is the capacitance 21 of the wiring 8 connected to the emitter.

FIG. 5 shows an example of a temporal change of the emitter potential calculated by using the above equation. According to FIG. 5, it takes about one second for the emitter potential to be equal to the base potential. This is not due to the fact that the emitter potential V _e does not flow is close happens when too much current to the V _P. Therefore, means for solving this, when applying a positive voltage V _R to the electrode 9 above, A method is conceivable in which the following conditions are added and the base potential is additionally biased in the forward direction by V _Bias . The current flowing at this time is given by the following equation.

[0033] 6, when the V _Bias = 0.6V, after a certain time, return the V _R which has been applied to the electrode 9 to zero volts,
For storing the voltage V _P at the time when the current flowing is stopped,
It shows the relationship between the read voltage, that is, the emitter potential. In FIG. 6, however, a constant value which depends on the read time due to the bias voltage component is always added to the read voltage, but a value obtained by subtracting the getter is plotted. Electrode 9
When the positive voltage V _R applied to is returned to zero volts, Since the voltage is added to the base potential, a base potential, before applying a positive voltage V _R state, i.e., -V _B
And the current is stopped because the emitter is reverse-biased. Taking According to FIG. 6 100 ns about more read time (i.e., time the application of the V _R to the electrode 9), the reserved voltage V _P and the read voltage linearity is ensured over a range of about four orders of magnitude, faster Is possible to read. In FIG. 6, the 45 ° line is a result when a sufficient time is taken for reading. In the above calculation example, the capacitance Cs of the wiring 8 is 4 pF, which is 0.014 pF of the junction capacitance of Cbe + Cbc. Figure that despite even about 300-fold compared large, accumulated voltage V _P generated in the p region 6 is not subject to any attenuation, and that the effect of the bias voltage, which is read out very fast and 6 shows. This is because the amplifying function of the photosensor cell according to the above configuration, that is, the charge amplifying function is effectively working.

On the other hand, in the conventional MOS type imaging device, the accumulated voltage V _P is Cj · V _P / (Cj + Cs) (where Cj is the MOS type imaging device) due to the influence of the wiring capacitance Cs in such a reading process. Pn junction capacitance of the light receiving portion), and the read voltage value of the second digit is lowered. For this reason, in the MOS imaging device, fixed pattern noise due to variation in parasitic capacitance of the switching MOS transistor for reading out to the outside or random noise generated due to large wiring capacitance, that is, output capacitance, is large, and the S / N ratio can be obtained. However, the optical sensor cell having the configuration shown in FIG. 1, FIG. 2, and FIG.
The accumulated voltage itself generated in the p region 6 is read out to the outside, and since this voltage is considerably large, the fixed pattern noise and the random noise due to the output capacitance are relatively small, and the S / N ratio is very good. It is possible to get a signal.

It has been previously shown that when the bias voltage V _Bias is set to 0.6 V, linearity of about four digits can be obtained in a high-speed reading time of about 100 nsec. FIG. 7 shows the result of calculating the relationship of V _Bias in more detail.

In FIG. 7, the horizontal axis represents the bias voltage V _Bias
The vertical axis indicates the read time. The parameters show the time dependence of the read voltage to 80%, 90%, 95%, and 98% of 1 mV when the storage voltage is 1 mV. As shown in FIG. 6, at an accumulation voltage of 1 mV, 80%, 90%, 95%,
At 98%, it is clear that the higher the accumulated voltage, the better the value.

According to FIG. 7, when the bias voltage V _Bias is 0.6 V, the read voltage becomes 80% of the storage voltage when the read time is 0.12 μs, and when the read voltage becomes 90% it is 0.2%.
It can be seen that 7 μs, 95% is 0.54 μs, and 98% is 1.4 μs. Further, it is shown that higher-speed reading is possible if the bias voltage V _Bias is set to be larger than 0.6 V. As described above, when the read time and the required linearity are determined from the overall design of the imaging device, the required bias voltage V _Bias can be determined by using the graph of FIG.

Another advantage of the photosensor cell according to the above configuration is that the holes accumulated in the p region 6 can be read nondestructively since the recombination probability of electrons and holes in the p region 6 is extremely small. is there. That is, when returning the voltage V _R which has been applied to the electrode 9 during the readout to zero volts, the potential of the p region 6 becomes reverse biased before the application of the voltage V _R, the reserved voltage V _P generated by light irradiation As long as the light is not newly irradiated, it is stored as it is. This means that when the photosensor cell according to the above configuration is configured as a photoelectric conversion device, a new function can be provided in terms of system operation.

The time to hold the accumulated voltage V _P to the p region 6 is extremely long, the maximum holding time is rather limited by thermally dark current generated in the depletion layer of the junction. That is, the photosensor cell is saturated by the thermally generated dark current. However, in the optical sensor cell according to the above configuration, the region where the depletion layer extends is the n ⁻ region 5 that is a low impurity concentration region, and the n ⁻ region 5 is about 10 ¹² cm ⁻³ to 10 ¹⁴ cm ^−3. Since the impurity concentration is extremely low, the crystallinity is good, and the number of electron-hole pairs thermally generated is small as compared with MOS-type and CCD-type image pickup devices. For this reason, the dark current is smaller than other conventional devices. That is, the photosensor cell according to the above configuration has a structure with essentially low dark current noise.

Next, the operation of refreshing the charge stored in p region 6 will be described. In the photosensor cell according to the above configuration, as described above, the charge accumulated in the p region 6 does not disappear in the read operation. Therefore, in order to input new optical information, a refresh operation for extinguishing previously accumulated electric charges is required. At the same time, it is necessary to charge the potential of the floating p region 6 to a predetermined negative voltage.

In the photosensor cell having the above structure, the refresh operation is performed by applying a positive voltage to the electrode 9 through the wiring 10 as in the read operation. At this time, the emitter is grounded through the wiring 8. The collector is an electrode 12
To ground or positive potential. FIG. 8 shows an equivalent circuit of the refresh operation. However, an example in which the collector side is grounded is shown.

In this state, when a voltage of the positive voltage V _RH is applied to the electrode 9, the oxide film capacitance Cox 1 is applied to the base 22.
3, the base-emitter junction capacitance Cbe15,
By dividing the collector junction capacitance Cbc17, Is instantaneously applied as in the previous read operation. With this voltage, the base-emitter junction diode Dbe16 and the base-collector junction diode Dbc18 are forward-biased and in a conducting state, current starts to flow, and the base potential gradually decreases.

At this time, a change in the potential V of the base in a floating state is approximately expressed by the following equation. i ₁ is a current flowing through the diode Dbc, and i ₂ is a current flowing through the diode Dbe. _Ab is the base area, A _e
Is the emitter area, D _P is the diffusion coefficient of holes in the collector, p _ne is the hole concentration in the thermal equilibrium state in the collector, Lp is the mean free path of holes in the collector, and n _pe is the electron concentration in the thermal equilibrium state in the base. It is. At i ₂ , the current due to hole injection from the base side to the emitter is negligible since the impurity concentration of the emitter is sufficiently higher than the impurity concentration of the base.

The above equation is an approximation of the step junction, which deviates from the step junction in an actual device, and is strict because it has a thin base and a complicated concentration distribution. However, the refresh operation can be explained with a considerable approximation. Of the current i ₁ flowing between the base and the collector in the above equation, q · D _P · p _ne / Lp indicates a current due to a hole, that is, a component in which the hole flows from the base to the collector side. In the photosensor cell according to the above configuration, the impurity concentration of the collector is designed to be slightly lower than that of a normal bipolar transistor so that the current due to the hole easily flows.

FIG. 9 shows an example of the time dependency of the base potential calculated using this equation. The abscissa indicates the lapse of time from the moment when the refresh voltage V _RH is applied to the electrode 9, that is, the refresh time, and the ordinate indicates the base potential. In addition, the initial potential of the base is used as a parameter. The initial potential of the base is a potential indicated by the base in a floating state at the moment when the refresh voltage V _RH is applied, and is determined by V _RH , Cox, Cbe, Cbc, and electric charges accumulated in the base.

Referring to FIG. 9, the base potential always drops after a certain period of time according to one straight line on the semilogarithmic graph regardless of the initial potential. FIG. 10 shows experimental values of the base potential change with respect to the refresh time. Compared with the calculation example shown in FIG. 9, the test device used in this experiment has a considerably large dimension, so that the absolute value does not match the calculation example. It has been proved that the value changes linearly with. This experimental example shows a value when both the collector and the emitter are grounded.

Now, assuming that the maximum value of the accumulated voltage V _P due to light irradiation is 0.4 [V] and the voltage V applied to the base by the refresh voltage V _RH is 0.4 [V], as shown in FIG. The maximum value of the initial base potential is 0.8 [V],
After 10 ^-15 [sec] after the application of the refresh voltage, the base potential starts to fall in a straight line after 10 ^-5 [sec] when no light is applied, that is, when the initial base potential is 0.4 [V]. Coincides with the potential change at the time.

There are two ways in which a positive voltage is applied to the p region 6 through the MOS capacitor Cox for a certain period of time, and when the positive voltage is removed, the p region 6 is charged to a negative potential. One is an operation in which holes having a positive charge flow out of the p region 6 into the n region 1 which is mainly in the ground state, whereby negative charges are accumulated. In order for holes from the p region 6 to flow unilaterally to the n region 1 and to prevent electrons in the n region 1 from flowing into the p region 6 too much, the impurity density of the p region 6 is changed to the impurity density of the n region 1. It should be higher.
On the other hand, electrons from the n ⁺ region 7 and the n region 1 flow into the p region 6 and recombine with holes, thereby forming the p region 6.
The operation of accumulating negative charges can also be performed. In this case, the impurity density of n region 1 is higher than that of p region 6. p
The operation of accumulating negative charges by holes flowing out of the region 6 is much faster than the operation of accumulating negative charges by electrons flowing into the base of the p region 6 and recombining with holes. However, according to the experiments so far, it has been confirmed that the refresh operation in which electrons flow into the p region 6 shows a sufficiently fast time response to the operation of the photoelectric conversion device.

[0049] When side by side a number of photosensor cell of the above structure in the XY direction in the photoelectric conversion device, in each sensor cell by the image, storing the voltage V _P is in the above example 0
Although it fluctuates between 0.4 [V], a constant voltage of about 0.3 [V] remains in the base of all sensor cells at 10 ^-5 [sec] after application of the refresh voltage V _RH. , change in storage voltage V _P by the image it can be seen that disappear all. That is, in the photoelectric conversion device using the optical sensor cells according to the above configuration, a complete refresh mode in which the base potential of all the sensor cells is brought to zero volt by the refresh operation (in this case, 10 [sec] is required in the example of FIG. 9), constant voltage to the base potential is is not two of the remaining ones transient refresh mode fluctuation component disappears by the reserved voltage V _P of the present (in the example of FIG. 9 this time, 10 [μsec] and 1
0 [sec] refresh pulse). In the above example,
The voltage V applied to the base by the refresh voltage V _RH
Although the _A and 0.4 V, the voltage V _A 0.6
[V], the transient refresh mode is
According to FIG. 9, it occurs at 1 [nsec], and refreshing can be performed very fast. The selection between operation in the complete refresh mode and operation in the transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

If the voltage remaining on the base in this transient refresh mode is V _K , the refresh voltage V _RH
Is applied, the transient state at the moment when V _RH is returned to zero volt, Is added to the base, the base potential after the refresh operation by the refresh pulse is And the base is in a reverse bias state with respect to the emitter.

Although it has been described above that in the accumulation operation for accumulating carriers excited by light, the base is operated in the reverse bias state in the accumulation state. The two operations of going are performed at the same time.

FIG. 11 shows the base potential after the refresh operation with respect to the refresh voltage V _RH . Shows the experimental value of the change in. The value of Cox is taken as a parameter from 5 pF to 100 pF. The circles are experimental values, and the solid line is It shows the calculated value calculated from the above. At this time, V _K =
0.52 V, and Cbc + Cbe = 4 pF. However, the prog capacity of the observation oscilloscope is 13pF
Are connected in parallel to Cbc + Cbe. Like this
The calculated value and the experimental value completely match, and the refresh operation has been experimentally confirmed.

In the above refresh operation, FIG.
As described above, an example in which the collector is grounded has been described, but it is also possible to perform the operation with the collector at a positive potential. At this time, even if the refresh pulse is applied to the base-collector junction diode Dbc18,
If the positive potential applied to the collector is higher than the potential applied to the base by this refresh pulse, the current will flow through only the base-emitter junction diode Dbe16 since the non-conductive state is maintained. Therefore, although the base potential decreases more slowly, basically, the operation exactly the same as that described above is performed.

That is, the relationship between the refresh time and the base potential in FIG. 9 is such that the diagonal straight line when the base potential decreases in FIG. 9 shifts to the right side, that is, the direction requiring more time. Therefore, if the same refresh voltage V _RH as when the collector is grounded is used, it takes time to refresh. However, if the refresh voltage V _RH is slightly increased, a high-speed refresh operation can be performed as in the case where the collector is grounded. It is possible.

The above is the description of the basic operation of the photosensor cell according to the above configuration, which includes the charge accumulation operation, the read operation, and the refresh operation due to the incidence of light. As explained above,
The basic structure of the optical sensor cell according to the above configuration is disclosed in Japanese Patent Application Laid-Open Nos. 56-150878 and 56-15
It has a very simple structure as compared with Japanese Patent Application Laid-Open No. 7073 and Japanese Patent Application Laid-Open No. 56-165473, and can sufficiently cope with high resolution in the future. The advantages of output, wide dynamic range, non-destructive readout, etc. are preserved as they are.

Next, a configuration example of a photoelectric conversion device in which the photosensor cells according to the configuration described above are arranged two-dimensionally will be described with reference to the drawings. FIG. 12 shows a circuit configuration diagram of a photoelectric conversion device in which basic photosensor cell structures are two-dimensionally arranged in 3 × 3.

The basic photosensor cell 30 (the collector of the bipolar transistor is shown to be connected to the substrate and the substrate electrode at this time) surrounded by the dotted line already described, and a horizontal pulse for applying a read pulse and a refresh pulse. Lines 31, 31 ', 31 ", vertical shift register 32 for generating read pulses, vertical shift register 32 and horizontal lines 31, 31', 31"
Between the buffer MOS transistors 33, 33 ', 3
A terminal 34 for applying a pulse to the 3 "gate, buffer MOS transistors 35, 35 ', 35" for applying a refresh pulse, a terminal 36 for applying a pulse to the gate thereof, and a refresh pulse are applied. 37, vertical lines 38, 38 ', 38 "for reading an accumulated voltage from the basic photosensor cell 30, a horizontal shift register 39 for generating a pulse for selecting each vertical line, and opening and closing each vertical line. MOS transistors 40, 40 ', and 40 "for output, an output line 41 for reading the accumulated voltage to the amplifier section,
M for refreshing the charge stored in the output line
OS transistor 42, terminal 43 for applying a refresh pulse to MOS transistor 42, bipolar for amplifying an output signal, MOS, FET, J-FE
T, a transistor 44, a load resistor 45, a terminal 46 for connecting the transistor to a power supply, an output terminal 47 of the transistor, and vertical lines 40, 4 in a read operation.
MOS transistors 48, 48 ', 48 "for refreshing the electric charges stored in 0', 40" and M
This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gates of the OS transistors 48, 48 ', 48 ".

The operation of this photoelectric conversion device will be described with reference to the pulse timing charts shown in FIGS. In FIG. 13, a section 61 corresponds to a refresh operation, a section 62 corresponds to an accumulation operation, and a section 63 corresponds to a read operation. At time t ₁ , the substrate potential, that is, the collector potential 64 of the photosensor cell portion is maintained at the ground potential or the positive potential, but FIG. 13 shows the substrate potential maintained at the ground potential. Regardless of the ground potential or the positive potential, as described above, only the time required for refresh differs, and the basic operation does not change. The potential 65 of the terminal 49 is high, the MOS transistors 48, 48 ', 48 "are kept conductive, and each photosensor cell is grounded through the vertical lines 38, 38', 38". Further, a voltage that causes the buffer MOS transistor to conduct as shown by a waveform 66 is applied to the terminal 36, and the buffer MOS transistors 35, 35 ', and 35 ″ for all-screen batch refresh are in a conductive state. When a pulse is applied to 37 as shown by waveform 67, a voltage is applied to the base of each photosensor cell through horizontal lines 31, 31 ', 31 ", and as described above, the refresh operation is started, and the data is stored before that. The charged charges are refreshed according to the complete refresh mode or the transient refresh mode. Whether to enter the complete refresh mode or the transient refresh mode is determined by the pulse width of the waveform 67.

At time t ₂ , as described above, the base of the transistor of each photosensor cell is in a reverse bias state with respect to the emitter, and proceeds to the next accumulation section 62. In this refresh period 61, as shown in the figure, all other applied pulses are kept in a low state.

In the accumulation operation section 62, the substrate voltage,
That is, the collector potential waveform 64 of the transistor is set to a positive potential. As a result, the electrons out of the electron-hole pairs generated by the light irradiation can quickly flow toward the collector. However, keeping the collector potential at a positive potential is not an essential condition since imaging is performed with the base in a reverse bias state with respect to the emitter, that is, a negative potential. There is no change in the typical accumulation operation.

In the accumulation operation state, the potential 65 of the gate terminal 49 of the MOS transistors 48, 48 ', 48 "
Are kept high as in the refresh section, and each M
The OS transistor is kept conductive. Therefore, the emitter of each photosensor cell is connected to the vertical line 38, 38 ', 3
8 ". Holes are accumulated in the base due to strong light irradiation, and when the base is saturated, that is, when the base potential is in a forward bias state with respect to the emitter potential (ground potential), The hole is a vertical line 38,
38 ', 38 ", where the base potential change stops and is clipped. Thus, the emitters of the vertically adjacent photosensor cells are commonly connected by vertical lines 38, 38', 38". Even
When the vertical lines 38, 38 ', 38 "are grounded in this way, no blooming phenomenon occurs.

A method for avoiding the blooming phenomenon is as follows.
Even if the OS transistors 48, 48 ', 48 "are turned off and the vertical lines 38, 38', 38" are in a floating state, the substrate potential, that is, the collector potential 64 is kept at a slightly negative potential, and When the base potential changes in the positive potential direction due to the accumulation, it can also be achieved by flowing out toward the collector side before the emitter.

[0063] Following the accumulation section 62, the read section 63 from time t _3. At time t _3, MOS transistors 48, 48 ', the potential 65 of the gate terminal 49 of the 48 "to low, and the horizontal lines 31, 31', 3
1 "buffer MOS transistors 33, 33 ', 3
The potential 68 of the 3 ″ gate terminal is set to high, and the respective MOS transistors are turned on. However, the timing of setting the potential 68 of the gate terminal 34 to high is not an indispensable condition that it is time t ₃ . Any time earlier than that is fine.

At time t ₄ , the output of the vertical shift register 32 connected to the horizontal line 31 has the waveform 6
At this time, since the MOS transistor 33 is in a conductive state, reading of each of the three photosensor cells connected to the horizontal line 31 is performed. This read operation is as described above,
The signal voltage generated by the signal charge stored in the base region of each photosensor cell is directly applied to the vertical lines 38, 3
8 ', 38 ". At this time, the pulse width of the pulse voltage from the vertical shift register 32 is, as shown in FIG. The pulse voltage is adjusted so as to apply a forward bias to the emitter by V _Bias as described above.

Next, at time t ₅ , among the outputs of the horizontal shift register 39, only the output to the gate of the MOS transistor 40 connected to the vertical line 38 has the waveform 7
0, the MOS transistor 40 becomes conductive, and the output signal is output through the output line 41.
The current enters the output transistor 44, is amplified, and is output from the output terminal 47. After the signal in this manner is read, since the output line 41 is left signal charge due to wiring capacitance, at time t _6, MOS transistor 42
A pulse is applied to the gate terminal 43 as shown in the pulse waveform 71, the MOS transistor 42 is turned on, the output line 41 is grounded, and the remaining signal charges are refreshed. Similarly, the switching MOS transistors 40 'and 40 "are sequentially turned on to read the signal outputs of the vertical lines 38' and 38". After reading the signals from the photosensor cells for one line arranged horizontally in this manner, the vertical lines 38, 38 ', and 38 "have the signal charges caused by the wiring capacitance thereof as in the case of the output line 41. , Each vertical line 38, 3
MOS transistors 48, 4 connected to 8 ', 38 "
8 ', 48 "is made high at its gate terminal 49 as shown by the waveform 65 to make it conductive, and this residual signal charge is refreshed.

Next, at time t ₈ , of the outputs of the vertical shift register 32, the output connected to the horizontal line 31 ′ becomes high as shown by a waveform 69 ′, and the output of each photosensor cell connected to the horizontal line 31 ′ The voltage is read out to each of the vertical lines 38, 38 ', 38 ". Thereafter, the signal is read out from the output terminal 47 by the same operation as before.

In the above description, an application field in which the storage section 62 and the read section 63 are clearly separated, for example, an operation state applied to a still video in which research and development has been actively conducted recently. However, the present invention can be applied to an application field in which the operation in the accumulation section 62 and the operation in the read section 63 are simultaneously performed like a television camera by changing the pulse timing in FIG. However, the refresh at this time requires a refresh function for each line, not a full screen batch refresh. For example, after the signals of the photosensor cells connected to the horizontal line 31 is read, MOS transistors 48, 48 for erasing charges remaining in the vertical line at time t ₇ ', but to conduct 48 " At this time, a refresh pulse is applied to the horizontal line 31.
That is, at time t ₇ in waveform 69, time t
_{As in the case of 4} , this can be achieved by using a vertical shift register configured to generate pulses having different pulse voltages and pulse widths. In addition to the double pulse operation, a second vertical shift register similar to the left side is provided on the right side instead of the device for applying the batch refresh pulse provided on the right side of FIG. 12, and the timing is provided on the left side. It is also possible to achieve this by operating while shifting the vertical register.

At this time, in the storage state as described above, the degree of freedom of the operation of suppressing blooming by operating the respective potentials of the emitter and the collector of each photosensor cell is reduced. However, as described in the description of the basic operation, in the reading state, the configuration is such that high-speed reading can be performed only when a bias voltage of V _Bias is applied to the base. Therefore, as can be seen from the graph of FIG. _Bias
Due to the saturation of each photosensor cell when is not applied, the amount of signal charge flowing out to the vertical lines 28, 28 ', 28 "is very small, and the blooming phenomenon is not a problem at all.

Also, the photoelectric conversion device according to this configuration example can obtain extremely excellent characteristics with respect to the smear phenomenon. The smear phenomenon is a problem that occurs in an operation and a structure in a CCD type imaging device, particularly, in a frame transfer type, in which electric charge is transferred in a place where light is irradiated.
In the interline type, there is a problem that occurs because carriers generated in a deep part of the semiconductor due to long-wavelength light are accumulated in the charge transfer portion.

Further, in the MOS type imaging device, there is a problem that carriers generated in the deep part of the semiconductor due to long-wavelength light are accumulated on the drain side of the switching MOS transistor grounded to each optical sensor cell. On the other hand, in the photoelectric conversion device according to this configuration example, there is no smear phenomenon that occurs in operation and structure, and no phenomenon that carriers generated in the deep part of the semiconductor due to long-wavelength light are accumulated at all. However, among the electrons and holes generated relatively near the surface of the emitter of the photosensor cell, there is a concern about the development that electrons are accumulated, but this is because the emitter is grounded in the accumulation operation state during the batch refresh operation. Therefore, electrons are not accumulated, and no smear phenomenon occurs. In the case of a line refresh operation applied to a normal television camera, the vertical line is grounded and refreshed before reading the accumulated voltage to the vertical line during the horizontal blanking period. The electrons accumulated during one horizontal scanning period flow out, so that the smear phenomenon hardly occurs. As described above, in the photoelectric conversion device according to the present configuration example, smear development is substantially negligible due to its structure and operation, which is one of the great advantages of the photoelectric conversion device according to this configuration example. One.

Although the operation of suppressing the blooming phenomenon by operating the potentials of the emitter and the collector in the accumulation operation state has been described above, it is also possible to control the γ characteristic by utilizing this. That is, during the accumulation operation, the potential of the emitter or the collector is temporarily set to a certain negative potential, and the holes accumulated in the base more than the number of carriers giving the negative potential out of the carriers accumulated in the base are changed to the emitter or the collector. The operation of flowing to the collector side is performed. As a result, the relationship between the storage voltage and the incident light amount shows the characteristic of γ = 1 of the silicon crystal when the incident light amount is small, and shows the characteristic that γ is smaller than 1 when the incident light amount is large. That is, γ =
It is possible to have a characteristic of 0.45. If the above operation is performed once in the middle of the accumulation operation, a one-fold line approximation is obtained. If the negative potential applied to the emitter or the collector is appropriately changed twice, a two-fold line type γ characteristic can be provided.

In the above configuration example, the silicon substrate is used as a common collector. However, a structure may be adopted in which a buried n ⁺ region is provided as in a normal bipolar transistor, and the collector is divided for each line. In addition, a clock pulse for driving the vertical shift register 32 and the horizontal shift register 39 is required for the actual operation in addition to the pulse timing shown in FIG.

FIG. 15 shows an equivalent circuit relating to the output signal. The capacitance C _V 80 is the wiring capacitance of the vertical lines 38, 38 ', 38 ", and the capacitance C _H 81 is the wiring capacitance of the output line 41. The equivalent circuit on the right side of FIG. And M for switching
The OS transistors 40, 40 ', and 40 "are conducting, and the resistance value in the conducting state is indicated by a resistor _RM 82. The amplifying transistor 44 is connected to a resistor re 83.
And an equivalent circuit using the current source 84. The MOS transistor 42 for refreshing the charge accumulation caused by the wiring capacitance of the output line 41 is non-conductive in the read state and has a high impedance, so that it is omitted in the equivalent circuit on the right.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually configured. For example, the capacitance C _V 80 is about 4 pF, and the capacitance C _H 81
Is about 4 pF, the resistance R of the MOS transistor in a conductive state.
FIG. 16 shows an example in which the output signal waveform observed at the output terminal 47 is calculated with _M 82 being about 3 KΩ and the current amplification factor β of the bipolar transistor 44 being about 100.

In FIG. 16, the horizontal axis is a switching MOS.
The vertical axis represents the time [μs] from the moment when the transistors 40, 40 ′, 40 ″ are turned on, and the vertical axis represents the vertical lines 38, 38 ′, 3
An output voltage [V] appearing at the output terminal 47 when a signal charge is read out from each photosensor cell and a voltage of 1 volt is applied to an 8 ″ wiring capacitance C _V 80 is shown.

The output signal waveform 85 has a load resistance R _E 45 of 1
0KΩ, 86 is a load resistor R _E 45 5KΩ, 87 are those when the load resistor R _E 45 is 2K ohms, the peak value in either the, 0.5V about by the capacitance division of the C _V 80 and C _H 81 It has become. Of course, the larger the load resistor R _E 45 attenuation is small, has a desired output waveform. The rise time is as fast as about 20 nsec for the above parameter values. Switching MOS transistors 40, 40 ', by decreasing the resistance R _M in the conductive state of 40 ", and,
Higher-speed reading is also possible by reducing the wiring capacitances C _V and C _H.

In the photoelectric conversion device using the photosensor cell according to the above configuration, since the voltage appearing at the output is large due to the amplification function of each photosensor cell, the amplification amplifier in the last stage is considerably more compared with the MOS type imaging device. Simple things are fine. In the above example, an example in which a single-stage bipolar transistor is used has been described. However, it is of course possible to use another method such as a two-stage structure. When a bipolar transistor is used as in this example, the problem of 1 / f noise that is easily noticeable on an image generated from the MOS transistor of the last stage amplifier in the CCD imaging device does not occur in the photoelectric conversion device of this configuration example. It is possible to obtain an image having an extremely good S / N ratio.

As described above, in the photoelectric conversion device using the photosensor cell according to the above configuration, the final stage amplification amplifier may be very simple, so that only one final stage amplification amplifier is provided. Instead of the type as in the configuration example shown in FIG. 12, it is also possible to provide a configuration in which a plurality of amplification amplifiers are provided and one screen is divided into a plurality of sections and read out.

FIG. 17 shows an example of the divisional reading method.
The configuration example shown in FIG. 17 is an example in which the horizontal direction is divided into three and three final-stage amplifiers are installed. The basic operation is shown in FIG.
It is almost as that described with reference to the timing diagram of a configuration example and FIG. 13 the same, in the configuration example of FIG. 17,
Three equivalent horizontal shift registers 100, 101, 10
2 and a terminal 1 for applying these starting pulses.
When the start pulse is input to the third row, the first row, the (n + 1) th row,
The outputs of the sensor cells connected to the (2n + 1) -th column (n is an integer and the number of horizontal picture elements is 3n in this configuration example) are read simultaneously. At the next point in time, the second, (n + 2) th, and (2n + 2) th columns are read.

According to this configuration example, when the reading time for one horizontal line is fixed, the scanning frequency in the horizontal direction is reduced by a factor of 1 / compared to the system with one final stage amplifier. A high-speed analog-to-digital converter is not required for applications where the horizontal shift register can be simplified, and the output signal from the photoelectric conversion device is subjected to analog-to-digital conversion and signal processing. This is a great advantage of the division readout method.

In the configuration example shown in FIG. 17, three equivalent horizontal shift registers are provided, but a similar function can be provided by only one horizontal register. FIG. 18 shows a configuration example in this case. Configuration example of FIG. 18, the horizontal switching M among the configuration example shown in FIG. 17
Only an intermediate portion between the OS transistor and the final stage amplifier is shown, and other portions are omitted because they are the same as the configuration example of FIG.

In this configuration example, the output from one horizontal shift register 104 is output to the first column, the (n + 1) th column, and (2n)
+1) It is connected to the gates of the switching MOS transistors in the column, and these lines are read simultaneously. At the next time, the second column, the (n + 2) th column, the (2n +
2) The column is read.

According to this configuration example, each switching MO
Although the number of wirings to the gate of the S transistor is increased, only one horizontal shift register can operate. 17 and 18 show an example in which three output amplifiers are provided, but the number of output amplifiers may be increased according to the purpose.

In each of the configuration examples shown in FIGS. 17 and 18, the start pulse and the clock pulse of the horizontal shift register and the vertical shift register are omitted, but these are provided in the same chip as the other refresh pulses. Clock pulse generator or a clock pulse generator provided on another chip.

In this divisional readout system, when horizontal line batch or full screen batch refresh is performed, the n-th column and (n
+1) The accumulation time is slightly different between the photosensor cells in the column, and this causes a slight discontinuity in the dark current component and the signal component, which may be attached to the eyes on the image. Is slight, and there is no practical problem. Also, even if this exceeds the permissible limit, using an external circuit to correct it will generate a sine wave, subtract it from the dark current component, and multiply and divide this by the signal component. This is easily possible by using the conventional correction technique performed by

When a color image is taken by using such a photoelectric conversion device, a stripe filter, a mosaic filter, or the like may be formed on a chip on the photoelectric conversion device, or a separately prepared color filter may be attached. A color signal can be obtained by matching.

As an example, when the R, G, and B stripe filters are used, in the photoelectric conversion device using the photosensor cell according to the above configuration, the R, G, and B signals are respectively output from separate final-stage amplifiers. It is possible to get. An example of this configuration is shown in FIG. FIG. 19 also shows FIG.
Like FIG. 8, only around the horizontal register is shown.
Others are the same as FIG. 12 and FIG.
Color filter, the second row is a G color filter,
The third row is provided with a color filter such as a B color filter, and the fourth row is provided with an R color filter. As shown in FIG. 19, each vertical line of the first column, the fourth column, the seventh column,... Is connected to an output line 110, which takes out an R signal. Each of the vertical lines in the second, fifth, eighth,... Columns is connected to an output line 111, which takes out a G signal. Similarly, the vertical lines in the third, sixth, ninth,... Columns are connected to the output line 112 to extract the B signal. The output lines 110, 111, 112 are respectively connected to on-chip refresh-like MOS transistors and final stage amplifiers, for example, emitter follower type bipolar transistors, and each color signal is output separately.

FIG. 20 is a diagram for explaining the basic structure and operation of another example of a photosensor cell constituting a photoelectric conversion device according to another embodiment of the present invention. FIG. 21 shows an equivalent circuit and an overall circuit configuration diagram thereof. The photosensor cell shown in FIG. 20 is a photosensor cell capable of simultaneously performing a read operation and a line refresh by the same horizontal scan pulse. 20 differs from the configuration already shown in FIGS. 1 to 3 in that the configuration shown in FIGS.
In the case of (1), only one MOS capacitor electrode 9 connected to the horizontal line 10 is connected to the vertically adjacent photosensor cells, and the MOS capacitor electrode 120 is also connected to the single photosensor cell. The capacitor type, and the emitters 7 and 7 ′ of the photosensor cells vertically adjacent to each other in FIG.
The vertical line looks like a single line, but two lines are arranged via an insulating layer). That is, the emitter 7 is connected to the wiring 8 through the contact hole 19, and the emitter 7 'is connected to the wiring 8 through the contact hole 19'. Wiring 12
1 are different from each other.

This becomes clearer when looking at the equivalent circuit of FIG. That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31 '. The MOS capacitor 150 'of the adjacent photosensor cell 152' in the figure of the photosensor cell 152 is connected to the common horizontal line 31 '.

The emitters of the photosensor cells 152 are alternately connected to the vertical lines 38, the emitters of the photosensor cells 152 'are connected to the vertical lines 138, and the emitters of the photosensor cells 152 "are alternately connected to the vertical lines 38. In the equivalent circuit, the difference from the image pickup apparatus of FIG.
8, a switching MOS transistor 148 for refreshing the vertical line 138 in addition to the switching MOS transistor 48 for refreshing the vertical line 138, a switching MOS transistor 40 for selecting the vertical line 38, and a switching MOS transistor for selecting the vertical line 138. 140 is added, and one output amplifier system is added. This output system has a switching M for refreshing each line.
The configuration is such that the OS transistors 48 and 148 are connected.
A configuration using only one output amplifier as shown in FIG. 22 using an OS transistor is also possible. FIG. 22 shows only the vertical line selection and output amplifier system of FIG.

According to the photosensor cell of FIG. 20 and the embodiment shown in FIG. 21, the following operation is possible. That is, when the read operation of each of the photosensor cells connected to the horizontal line 31 is completed and the output pulse from the vertical shift register 32 is output to the horizontal line 31 'during the horizontal blanking period in the television operation, the MOS Through the capacitor 151, the read-out photosensor cell 1
Refresh 52. At this time, the switching MO
S-transistor 48 is rendered conductive and vertical line 38
Is grounded.

The MOS connected to the horizontal line 31 '
The output of photosensor cell 152 'is read out to vertical line 138 through capacitor 150'. At this time, naturally, the switching MOS transistor 148 is turned off, and the vertical line 138 is in a floating state. As described above, by one vertical scan pulse, the refreshing of the photosensor cells which have already been read and the reading of the photosensor cells of the next line can be performed simultaneously with the same pulse. At this time, as described above, the voltage at the time of refreshing and the voltage at the time of reading are different at the time of reading because a bias voltage is applied due to the necessity of high-speed reading. However, as shown in FIG. 9 and the MOS capacitor electrode 120 are changed so that a different voltage is applied to the base of each photosensor cell even if the same voltage is applied to each electrode.

That is, the area of the refresh MOS capacitor is smaller than the area of the read MOS capacitor. When refreshing the sensor cells line by line instead of batch refreshing all the sensor cells as in this example, the collector may be formed of an n-type or n-type substrate as shown in FIG. It may be desirable to provide a separate collector for each horizontal line. If the collector is a substrate,
Since the collectors of all the optical sensor cells are in a common region, a constant bias voltage is applied to the collectors in the accumulation and light reception reading states. Of course, as described above, the floating base refresh can be performed between the emitters even when the bias voltage is applied to the collector. However, in this case, at the same time as the refresh of the base region is performed, a useless current flows between the emitter and the collector of the cell to which the refresh pulse is applied, resulting in an increase in power consumption. In order to overcome these disadvantages, the collectors of all the sensor cells are not used as a common area, and the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are separated from each other. That is, as described in connection with the structure of FIGS. 1 to 3, the substrate is p-type and n separated from each other for each horizontal line of the collector in the p-type substrate.
⁺ Have a structure with an embedded region. Adjacent horizontal lines n
⁺ Embedded regions may be separated by a structure in which ap region is interposed. Insulator isolation is better at reducing collector capacitors buried along horizontal lines.
In FIGS. 1 to 3, since the collector is composed of a substrate, the isolation regions surrounding the sensor cells are all provided to almost the same depth. On the other hand, in order to separate the collectors for each horizontal line from each other, the separation region in the horizontal line direction must be deeper than the separation region in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, when the voltage of the collector of the horizontal line is grounded at the end of the read operation and the refresh operation, the current between the emitter and the collector as described above does not flow. , Does not result in increased power consumption. When the charge storage operation based on the optical signal is started after the refresh, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit of FIG. 21, the output is alternately output to the output terminals 47 and 147 for each horizontal line. This is, as already explained,
With the configuration as shown in FIG. 22, it is also possible to take out the output from one amplifier.

As described above, according to this embodiment, line refresh can be performed with a relatively simple configuration, and the present invention can be applied to application fields such as ordinary television cameras. As another embodiment of the present invention, a type in which a plurality of emitters are provided in a photosensor cell, or a plurality of contacts are provided in one emitter to take out a plurality of outputs from one photosensor cell is considered.

This is because each photosensor cell of the photoelectric conversion device according to the present invention has an amplifying function. Therefore, even if a plurality of wiring capacitors are connected to each photosensor cell in order to extract a plurality of outputs from one photosensor cell, This is because the accumulated voltage Vp generated inside the photosensor cell can be read out to each output without any attenuation.

As described above, the configuration capable of taking out a plurality of outputs from each optical sensor cell has many advantages in signal processing or noise countermeasures for a photoelectric conversion device in which a large number of optical sensor cells are arranged. It is possible to add. Next, an example of a method for manufacturing the photoelectric conversion device according to the present invention will be described. 23 to 29 show selective epitaxial growth (R. Endo et al, "Novel de
voice isolation technology
with selected epitaxial
growth "Tech.Dig.of 1982 I
EDM, pp. 241-244) is shown.

On the back side of the n-type Si substrate 1 having an impurity concentration of about 1 × 10 ¹⁶ cm ⁻³ , an n ⁺ region 11 for contact is provided by diffusion of As or P. In order to prevent auto doping from the n ⁺ region, an oxide film and a nitride film are usually provided on the back surface although not shown in the figure.

As the substrate 1, a substrate whose impurity concentration and oxygen concentration are controlled uniformly is used. That is, a crystal wafer having a sufficiently long carrier line time and a uniform wafer is used. As such a material, for example, a crystal formed by the MCZ method is suitable. An oxide film of about 1 μm is formed on the surface of the substrate 1 by wet oxidation. That is, oxidation is performed in an H ₂ O atmosphere or an (H ₂ + O ₂ ) atmosphere. To obtain a good oxide film without causing stacking faults and the like, 900 ° C.
High pressure oxidation at moderate temperatures is suitable.

A SiO ₂ film having a thickness of, for example, about _{2 to 4} μm is deposited thereon by CVD. (N ₂ + SiH ₄ +
O ₂ ) A SiO ₂ film having a desired thickness is deposited in a gas system at a temperature of about 300 to 500 ° C. The molar ratio of O ₂ / SiH ₄ is set to about 4 to 40, depending on the temperature. By the photolithography process, the oxide film in the other region is left (CF ₄ + H ₂ ), C
Removal by reactive ion etching using a gas such as ₂ F ₆ or CH ₂ F ₂ (step of FIG. 23), for example, 1
When one pixel is provided in 0 × 10 μm ² , the SiO ₂ film is left in a mesh shape at a pitch of 10 μm. The width of the SiO ₂ film is selected to be, for example, about 2 μm. The surface damage layer and the contaminant layer by the reactive ion etching are changed to Ar
/ Cl ₂ gas-based plasma etching or wet etching followed by vapor deposition in ultra-high vacuum, load-lock type sputtering with sufficiently clean atmosphere, or irradiation of SiH ₄ gas with a CO ₂ laser structure Amorphous silicon 3
01 (step of FIG. 24), CBrF ₃ , CCl
Amorphous silicon other than those deposited on the side surfaces of the SiO ₂ layer is removed by anisotropic etching by reactive ion etching using a gas such as ₂ F ₂ or Cl ₂ (step of FIG. 25), as before. After sufficiently removing the damage and the contaminant layer, the surface of the silicon substrate is sufficiently cleaned, and the silicon layer is selectively grown using a (H ₂ + SiH ₂ , Cl ₂ + HCl) gas system. The growth is performed under a reduced pressure of several tens of Torr, the substrate temperature is 900 to 1000 ° C.,
The molar ratio of HCl is set to a value higher than a certain level. HC
If the amount of l is too small, selective growth does not occur. Although a silicon crystal layer grows on the silicon substrate, silicon is not deposited on the SiO ₂ layer because the silicon on the SiO ₂ layer is etched by HCl (step in FIG. 26). The thickness of n ⁻ layer 5 is, for example, about 3 to 5 μm.

The impurity concentration is preferably from 10 ¹² to 10 ¹⁶ c
Set to about m- ³ . Of course, this range may be deviated, but in a state where the impurity is completely depleted by the diffusion potential of the pn ^- junction or an operating voltage is applied to the collector, at least the impurity concentration and the n ^- region are completely depleted. It is desirable to choose the thickness.

Since a generally available HCl gas contains a large amount of moisture, an oxide film is always formed on the surface of the silicon substrate, and high quality epitaxial growth cannot be expected. HCl containing a large amount of water reacts with the material of the cylinder while in the cylinder and contains a large amount of heavy metal mainly composed of iron, so that an epitaxial layer easily contaminated with heavy metal tends to be formed. Since it is desirable that the epitaxial layer used in the photosensor cell has a smaller dark current component, it is necessary to minimize contamination by heavy metals. Of course, an ultra-high purity material is used for SiH ₂ Cl ₂ , but HCl has a particularly low moisture content, preferably at least a moisture content of 0.5 ppm.
Use the following: Of course, the lower the water content, the better. In order to further improve the quality of the epitaxially grown layer, the substrate is first subjected to high-temperature treatment at about 1150 to 1250 ° C. to remove oxygen from the vicinity of the surface, and then subjected to a long-term heat treatment at about 800 ° C. to generate many micro defects inside the substrate. It is also very effective to use a substrate having a denuded zone and capable of performing intrinsic gettering. Since epitaxial growth is performed in a state where the SiO ₂ layer 4 as an isolation region exists,
In order to reduce the incorporation of oxygen from SiO ₂ , the lower the growth temperature, the better. In the commonly used high frequency heating method, there is much contamination from the carbon susceptor, and it is difficult to further lower the temperature. A direct wafer heating method by lamp heating without bringing a carbon susceptor or the like into the reaction chamber can make the growth atmosphere the cleanest and grow a high quality epitaxial layer at a low temperature.

For the wafer support in the reaction chamber, ultra-high-purity molten sapphire having a lower vapor pressure is suitable. The raw material gas can be easily preheated, and the temperature within the wafer surface is easy to be uniform even when a large amount of gas is flowing. Suitable to get. UV irradiation on the wafer surface during growth
Further improve the quality of the epitaxial layer.

Amorphous silicon is deposited on the side walls of the SiO ₂ layer serving as the isolation region 4 (step in FIG. 25).
Since amorphous silicon is easily single-crystallized by solid phase growth, the crystal near the interface with the SiO ₂ separation region 4 is very excellent. After the high resistance n ^- layer 5 is formed by selective epitaxial growth (step of FIG. 26), the surface concentration
A P region 6 of about 20 × 10 ¹⁶ cm ^{−3 is} formed to a predetermined depth by diffusion from doped oxide or diffusion using a low-dose ion implantation layer as a source. The depth of p region 6 is, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of p region 6 are determined based on the following concept. To increase the sensitivity, the p region 6
It is desirable to lower the impurity concentration of Cbe to reduce Cbe. Cbe is approximately given as follows. Where Vbi is the emitter-base diffusion potential, Given by Where ε is the dielectric constant of the silicon crystal, N
_D is the impurity concentration of the emitter, N _A is the impurity concentration of the portion adjacent to the emitter of the base, and n _i is the intrinsic carrier concentration. As Cbe is reduced to reduce the N _A, the sensitivity is increased, but since the the N _A is made too small base region will completely become depleted in punching through state at operating conditions, is too low can Absent. It is set to such an extent that the base region is not completely depleted and does not enter a punch-through state.

After that, (H ₂ + O
₂ ) Several tens to several hundreds of square meters by gas steam oxidation
A thermal oxide film 3 having a thickness of about 800 to 900 ° C. is formed. Thereon, the (SiH ₄ + NH ₃₎ based nitride film by CVD gas (Si ₃ N ₄₎ 302 500~15
It is formed with a thickness of about 00 °. Forming temperature is 700-90
It is about 0 ° C. The NH ₃ gas, also commonly available alongside the HCl gas, contains a large amount of moisture. When NH ₃ gas having a high moisture content is used as a raw material, a nitride film having a high oxygen concentration is obtained, and reproducibility is poor.
The result is that a selective ratio cannot be obtained by selective etching with the O ₂ film. The NH ₃ gas also has a water content of at least 0.1.
It should be less than 5 ppm. It goes without saying that the smaller the water content, the better. A PSG film 300 is further deposited on the nitride film 302 by CVD. The gas system uses, for example, (N ₂ + SiH ₄ + O ₂ + PH ₃ )
A PSG film having a thickness of about 2000 to 3000 ° is deposited by CVD at a temperature of about 300 to 450 ° C. (step in FIG. 27). An As-doped polysilicon film 304 is deposited on the n ⁺ region 7 and on the refresh and read pulse application electrodes by a photolithography process including two mask alignment processes. In this case, a p-doped polysilicon film may be used. For example, a PSG film, a Si ₃ N ₄ film,
All the SiO ₂ film is removed, and only the PSG film and the SI ₃ N ₄ film are etched, leaving the underlying SiO ₂ film in the portion where the refresh and read pulse application electrodes are provided. Thereafter, As-doped polysilicon is replaced with (N ₂ + SiH _4).
+ AsH ₃ ) or (H ₂ + SiH ₄ + AsH ₃ ) gas by CVD. Deposition temperature is 550 ° C to 7
The temperature is about 00 ° C. and the thickness is 1000 to 2000 °. As a matter of course, non-doped polysilicon may be deposited by the CVD method, and then As or P may be diffused. The polysilicon film in the other portion except on the emitter and the refresh and readout pulse application electrodes is removed by etching after the photolithography process using a mask. Further, when the PSG film is etched, the polysilicon deposited on the PSG film by lift-off is removed in a self-aligned manner (step of FIG. 28). The polysilicon film is etched with a gas such as C ₂ Cl ₂ F ₄ or (CBrF ₃ + Cl ₂ ), and the Si ₃ N ₄ film is etched with a gas such as CH ₂ F ₂ .

Next, after the PSG film 305 is deposited by the gas-based CVD method as described above, a contact hole is formed on the polysilicon film for the refresh pulse and the read pulse electrode by a mask alignment step and an etching step. Open. Under these conditions, Al, Al-Si, Al-
A metal such as Cu-Si is deposited by vacuum evaporation or sputtering, or (CH ₃ ) ₃ Al or AlCl ₃
Al is deposited by a plasma CVD method using as a raw material gas, or a light irradiation CVD method in which the Al—C bond or the Al—Cl bond of the above raw material gas is cut by direct light irradiation. When the above-described CVD method is performed using (CH ₃ ) ₃ Al or AlCl ₃ as a raw material gas, hydrogen is allowed to flow in a large excess. In order to deposit Al in a thin and steep contact hole, a CVD method in which the substrate temperature is raised to a film thickness of 300 to 400 ° C. in a clean atmosphere free of moisture and oxygen is excellent. After the patterning of the metal wiring 10 shown in FIG. 1 is completed, an interlayer insulating film 306 is deposited by a CVD method. Reference numeral 306 denotes a PSG film, a CVD SiO ₂ film, or a Si ₃ N ₄ film formed by a (SiH ₄ + NH ₃ ) gas plasma CVD method when it is necessary to consider water resistance or the like. is there. In order to keep the content of hydrogen in the Si ₃ N ₄ film low, a plasma CVD method using a (SiH ₄ + N ₂ ) gas system is used.

[0109] The electrical breakdown of the Si ₃ N ₄ film which is phenomenon damaged by plasma CVD is formed larger, and Si ₃ by the optical CVD method to reduce the leakage current
N ₄ film is excellent. There are two types of light CVD methods. (SiH ₄ + NH ₃ + Hg) gas system for externally irradiating ultraviolet rays of 2537 ° from a mercury lamp;
This is a method of irradiating an iH ₄ + NH) ₃ gas system with ultraviolet rays of 1849 ° from a mercury lamp. In all cases, the substrate temperature is 150 ~
It is about 350 ° C.

By the mask alignment step and the etching step, the insulating films 305 and 3 are formed on the polysilicon on the emitter 7.
06 is opened by reactive ion etching after the contact hole penetrating through Al, Al-S by the method described above.
i, a metal such as Al-Cu-Si is deposited. In this case, since the aspect ratio of the contact hole is large, C
Deposition by the VD method is better. After the patterning of the metal wiring 8 in FIGS. 1 and 2 is completed, a Si ₃ N ₄ film or a PSG film 2 as a final passivation film is formed.
Is deposited by the CVD method (FIG. 29).

Also in this case, the film formed by the photo CVD method is excellent. Reference numeral 12 denotes a metal electrode made of Al, Al-Si or the like on the back surface. The method of manufacturing the photoelectric conversion device of the present invention includes various steps, and FIGS. 23 to 29 are merely examples.

An important point of the photoelectric conversion device of the present invention is how to suppress the leakage current between the p region 6 and the n ⁻ region 5 and between the p region 6 and the n ⁺ region 7. n ^- region 5
Of course, the dark current is reduced by improving the quality of the isolation region 4 and the n ⁻ region 5 made of an oxide film or the like.
The interface is the problem. In FIG. 23 to FIG. 29, for this purpose, the amorphous Si
The method of performing epitaxial growth after depositing the above has been described. In this case, during epitaxial growth, the substrate S
Amorphous Si is monocrystallized by solid phase growth from i. Epitaxial growth is performed at 850 ° C. to 100
It is performed at a relatively high temperature of about 0 ° C. Therefore, before amorphous Si is monocrystallized by solid phase growth from the substrate Si, microcrystals often start to grow in the amorphous Si, which causes deterioration of crystallinity.
The lower the temperature, the faster the solid phase growth rate is amorphous Si
Before performing selective epitaxial growth, it is relatively much faster than the rate at which crystallites begin to grow.
Amorphous Si by low temperature treatment of about 50 ° C to 700 ° C
Is a single crystal, the characteristics of the interface are improved. At this time, if there is a layer such as an oxide film between the substrate Si and the amorphous Si, the start of solid-phase growth is delayed. Therefore, an ultra-high cleaning process that does not include such a layer at the boundary between them is necessary.

For the solid phase growth of amorphous Si, in addition to the above-described furnace growth, a rapid annealing technique using, for example, a few seconds to several tens of seconds by using a flash lamp heating or an infrared lamp while keeping the substrate at a certain temperature is also available. It is valid. When using these technologies,
The Si deposited on the side wall of the O ₂ layer may be polycrystalline. However, it is necessary to deposit by a very clean process, and to make polycrystalline Si containing no oxygen, carbon, or the like at the crystal grain boundaries of the polycrystalline body.

After Si on the side surface of SiO ₂ is monocrystallized, selective growth of Si is performed. If the leakage current at the interface between the SiO ₂ isolation region 4 and the high resistance n ⁻ region 5 is a problem, the n-type impurity concentration is increased only in the portion of the high resistance n ⁻ region 5 adjacent to the SiO ₂ isolation region 4. In this case, the problem of the leakage current is avoided. For example, 0.3 of n ⁻ region 5 in contact with isolated SiO ₂ region 4
Only a region having a thickness of about 1 μm, for example, 1 to 10 × 1
The n-type impurity concentration is increased to about 0 ¹⁶ cm ^-3 . This configuration can be formed relatively easily. After forming a thermal oxide film of about 1 μm on the substrate 1, a thermal oxide film is deposited thereon by a CVD method. Only first required thickness of the SiO ₂ film, keep the SiO ₂ film containing P of a predetermined amount. Further, the separation region 4 is formed by depositing SiO ₂ thereon by CVD.
Make it. From the phosphorus-containing SiO ₂ film present in a sandwich state in the isolation region 4 in the subsequent high-temperature process,
Phosphorus diffuses into the high-resistance n ⁻ region 5 to form a favorable impurity distribution in which the interface has the highest impurity concentration.

That is, the structure is as shown in FIG. The isolation region 4 has a three-layer structure, 308 is a thermal oxide film SiO ₂ , and 309 is C containing phosphorus.
A VD method SiO ₂ film 301 is a CVD method SiO ₂ film. Adjacent to the isolation region 4, between the n ⁻ region 5,
A region 307 is formed by diffusion from the SiO ₂ film 309 containing phosphorus. 307 is formed all around the cell. With this structure, the base-collector capacitance Cbc
However, the base-collector leakage current is drastically reduced.

[0116] In FIGS. 23 to 29, in advance in advance to make the isolation insulating region 4, an example has been described for performing selective epitaxial growth, the high-resistance n required on a substrate ^-
A U-group separation technique (A. Hayasaka et al, "U-") in which a layer to be an isolation region is cut into a mesh shape by reactive ion etching to form an isolation region after epitaxial growth of the layer.
Groove isolation technology
e for high speed bipolar
VLSI'S ", Tech. Dig. Of IEDM.
P. 62, 1982).

The photoelectric conversion device according to the present invention includes a bipolar transistor in which a base region adjacent to the surface of a semiconductor wafer is floated in a region surrounded by an isolation region formed of an insulator. This is an apparatus for photoelectrically converting optical information by controlling the potential of a formed and floating base region with an electrode provided in a part of the base region via a thin insulating layer. An emitter region including a high impurity concentration region is provided in a part of the base region, and the emitter is connected to a MOS transistor operated by a horizontal scan pulse. The above-described electrode provided in a part of the floating base region via a thin insulating layer is connected to a horizontal line. The collector provided inside the wafer may be constituted by a substrate, or may be constituted by a high-concentration impurity buried region separated for each horizontal line on a high resistance substrate of the opposite conductivity type depending on the purpose. . An applied pulse voltage for reading a signal is substantially higher than a pulse voltage for refreshing a floating base region at an electrode provided via an insulating layer. Indeed, the two may be used a pulse train to wait for voltage, as described in the double capacitor structure, to increase the capacity C _ox of the read MOS capacitor electrode compared to the capacitance C _ox of the refreshing MOS capacitor electrode You may keep it. By the application of the refresh pulse, the carrier excited by light is accumulated in the floating base region in the reverse bias state, and a signal based on the optical signal is stored. When the signal is read, the base-emitter is deeply biased in the forward direction. As described above, a signal is read at a high speed by applying a read pulse voltage. As long as these features are provided, the photoelectric conversion device of the present invention may be realized by any structure, and is not limited to the structure described in the above embodiment.

For example, the same applies to a structure in which the conductivity type is completely inverted from the structure described in the above embodiment. However, at this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure where the conductivity type is completely inverted, the region becomes n-type. That is, the impurities constituting the base are As and P. When the surface of the region containing As or P is oxidized, As or P piles up on the Si side of the Si / SiO ₂ interface. That is, a strong drift electric field is generated inside the base from the surface to the inside, and the photoexcited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

When the base is a p-type, a commonly used impurity is boron. When the surface of the p-region containing boron is thermally oxidized, boron is taken into the oxide film, so that Si /
The boron concentration in Si near the SiO ₂ interface is slightly lower than the boron concentration inside. This depth is usually several hundred degrees depending on the oxide film thickness. Near this interface,
A reverse drift electric field occurs for the electrons, and the electrons photoexcited in this region tend to collect on the surface. In this state, the region where the reverse drift electric field is generated becomes a dead region. However, since the n ⁺ region exists in a part along the surface in the photoelectric conversion device of the present invention, p ⁺
Electrons collected at the Si / SiO ₂ interface in the region are
It flows before being recombined into this n ⁺ region. For this reason, for example, even if there is a region where boron is reduced near the Si / SiO ₂ interface and a reverse drift electric field is generated, the region hardly becomes a dead region. Rather, when such a region exists at the Si / SiO ₂ interface, the accumulated holes are separated from the Si / SiO ₂ interface so as to be present inside. The hole accumulation effect in the base is improved, which is highly desirable.

The photoelectric conversion device according to the present invention is not limited to the solid-state image pickup device described above, but may be, for example, an image input device such as an image input device, a facsimile, a work station, a digital copying machine, a word processor, an OCR, and a bar code reader. The present invention can also be applied to a photoelectric conversion subject detection device for autofocus, such as a device, a camera, a video camera, and an 8 mm camera.

As described above, the photoelectric conversion device of the present invention accumulates carriers excited by light in the base region, which is a floating control electrode region. In other words, Base Store Image
This is an apparatus to be called a Sensor, and is abbreviated as BASIS.

The photoelectric conversion device of the present invention is very easy to increase the density because one pixel can be constituted by one transistor, and at the same time, its dynamic range is low in blooming and smear due to its structure and high in sensitivity. It is characterized by the fact that it has a large signal voltage irrespective of the wiring capacitance due to its internal amplifying function, so that low recording is possible and peripheral circuits are easy. For example, as a future high quality solid-state imaging device, its industrial value is extremely high.

FIG. 14 shows the potential levels at the emitter, base, and collector portions during the cycle of the transient refresh operation, the accumulation operation, the read operation, and the transient refresh operation. The voltage level of each portion is a potential seen from the outside, and there are some portions that do not partially match the internal potential level.

For simplicity, the diffusion potential between the emitter and the base is omitted. Therefore, when the emitter and the base are represented at the same level in FIG. There is a diffusion potential given by

In FIG. 14, state represents a refresh operation, state represents an accumulation operation, state represents a read operation, and state represents an operation state when the emitter is grounded. The potential level is negative on the upper side of 0 volts and positive on the lower side. It is assumed that the base potential before the state is zero volts, and that the collector potential is all biased to the positive potential from the state.

The above series of operations will be described with reference to the timing chart of FIG. As the waveform 67 in FIG. 13, the time t ₁
At this time, when a positive voltage, that is, a refresh voltage V _RH is applied to the terminal 37, the base shown in FIG. A partial pressure is applied. This potential will gradually decrease toward zero potential between time t ₁ of t _2, at time t _2, the a potential 201 indicated by a dotted line in FIG. 14. This potential is the potential V _K remaining on the base in the transient refresh mode as described above. At time t ₂ , as shown by a waveform 67, the base is set at the moment when the refresh voltage V _RH returns to the zero voltage. Since the same voltage is generated by the capacitance division as before, the base becomes the potential obtained by adding the remaining voltage V _K and the newly generated voltage. That is, the base potential 202 shown in the state, Given by

When light is incident on such an emitter in a reverse bias state, holes generated by the light are accumulated in the base region.
Base potential 202 according to the intensity of the incident come light base potential 203 and 203 'changes toward increasingly positive potential as the 203 ". The voltage generated by the light V _P
And

Next, as shown by a waveform 69, the voltage from the vertical shift register is applied to the horizontal line, that is, the read voltage V _R.
Is applied, the base Are added, the base potential 204 when no light is irradiated is Becomes The potential 204 at this time is, as described above,
It is set so that the emitter is biased in the forward direction by about 0.5 to 0.6 V. In addition, the base potential 20
5, 205 'and 205 "are respectively Given by

When the base potential is thus higher than that of the emitter,
When a forward bias is applied, electron injection from the emitter side occurs, and the emitter potential gradually moves in the positive potential direction. The emitter potential 206 with respect to the base potential 204 when no light is irradiated is about 50 to 100 mV when the readout pulse width is about 1 to 2 μs when the forward bias is set to 0.5 to 0.6 V. ,
Assuming that this voltage is V _B , the emitter potentials 207, 20
7 ', 207 ", because the linearity if more pulse width 0.1μs as in the preceding example is sufficiently secured, respectively V <sub>P
+ V B, V P '+</sub> V B, a V _P "+ V _B.

After a certain read time, when the read voltage V _R becomes zero potential as shown by a waveform 69, the base becomes Since the following voltages are added, the base potential becomes the state before the read pulse is applied, that is, the reverse bias state as in the state, and the potential change of the emitter stops. That is, the base potential 208 at this time is Given by This is exactly the same as the state before the start of reading.

In this state, the optical information signal on the emitter side is read out. After this reading, the switching MOS transistors 48, 4
8 ', 48 "are turned on and the emitter is grounded, as in the state where the emitter is grounded.
The cycle goes through the refresh operation, the accumulation operation, and the read operation, and then returns to the state. At this time, before the first refresh operation is started, the base potential starts from zero potential, but goes around once. After that, the base potential And it will be respectively _{V P, V P ', V} P " is changed to the sum potential. Therefore, in this state, each base potential as the refresh voltage V _RH is applied V _K , _VK + _VP , _VK + _VP ',
V _K + V _P ″. In this case, a sufficient forward bias is not applied to the base, and where the light is strongly applied, the forward bias amount is large, so that the optical information is lost.
It is apparent from the calculation example of the refresh operation shown in FIG. 9 that the information of the light weak portion remains without disappearing.

Such a phenomenon is peculiar to the transient refresh mode. In the complete refresh mode, such a problem does not occur because a long refresh time is required until the base potential becomes zero potential. Another embodiment in which the above-described inconvenience does not occur and high-speed refresh is possible will be described below. The refresh method described so far has been performed by applying a pulse to the base through a MOS capacitor and setting the base potential to a positive potential. That is, when the base is at a positive potential, the base-collector junction diode Dbc becomes conductive, and holes flow out of the base, so that the base potential decreases toward the ground potential. That is, a transient refresh or a complete refresh in which the base potential completely becomes the ground potential is used. In the case of the p-base, a predetermined amount of holes has disappeared from the base, and thus, in a state where the refresh pulse has been removed, the p-base has a negative power failure and has a predetermined negative voltage.

On the other hand, in the embodiment described below, a MOS transistor is loaded to each photosensor cell, and the holes accumulated by the photoexcitation from the base are removed to make a predetermined negative voltage for refreshing. The present invention relates to an enabled photoelectric conversion device.

This will be described in detail with reference to FIGS. FIG. 31 is a plan view showing a part when two or more basic optical sensor cells are arranged two-dimensionally. FIG. 32 is a cross-sectional view taken along the line AA ′ of FIG. 31. FIG. It is a figure which shows the circuit structure at the time of arrange | positioning a sensor cell, respectively.

FIGS. 31 and 32 show the structure of emitter region 7, vertical line 8 for reading and contact 19 between this wiring and emitter region 7, p region 6 and MOS capacitor 9 in FIG. It is exactly the same. However, the MOS capacitor 9 is commonly used in the read and refresh operations in the embodiments shown in FIGS. 1 and 2, but is used as a read operation in the present embodiment as described later.

The difference from the embodiment shown in FIGS. 1 to 3 is that
P-channel MOS for refreshing each photosensor cell
The point is that a transistor is added. That is, FIG.
As apparent from the cross-sectional view of FIG. 2, the p region 6 of the optical sensor cell and the p region 220 separated from the p region 6 by diffusion, ion implantation, etc., and an n-type channel dope between the two. Region, oxide film region 3 and gate electrode 22
1 is added. This newly formed p region 220
Made at the same time as forming the p-region 6 of the photosensor cell,
The n-type region serving as a channel between the regions is subjected to channel doping by using an ion implantation technique or the like to increase the n-type impurity concentration so as to prevent punch-through between the source and the drain. Although the number of processes increases a little, pMOS
In order to suppress the punch-through between the source and the drain, it is also effective to make the p region 220 very thin near the surface.

As shown in the plan view of FIG. 31, the gate 221 of the p-channel MOS transistor is commonly connected to the MOS capacitor electrode 9 so that a pulse is applied through the horizontal line 10. Also p channel M
OS transistor p region, ie, drain region 220
Is connected to the horizontal line 223 via the contact 222.

Therefore, the horizontal lines 10 and 22
The 3 and the vertical line 8 are formed by a multilayer wiring technique, and are insulated from each other by an insulating film. FIG. 33 shows that a p-channel MOS transistor having a source region common to the base region of the photosensor cell having the structure described above and a gate region commonly connected to the wiring 10 is added to each photosensor cell.

Hereinafter, the operation of this embodiment will be described.
Before the hole-based accumulation operation by optical excitation, FIG.
The base region is biased to a negative voltage as in the state shown in FIG. In the charge accumulation operation, holes generated by light are accumulated in the base region as in the state, and the potential of the base changes in the positive direction according to the intensity of light. In this state, the read pulse voltage V _R
Is applied, the base potential is set to a positive potential as in the state, and the information stored in the base is read out to the emitter side. Also a state when the read pulse voltage V _R is made the ground potential, and after the information through the vertical line from the emitter side is output to the outside, the emitter through the wiring 8 of the vertical line is the state being grounded, already before The operation is the same as that of the embodiment described above.

When a read pulse is applied to the wiring 10,
As shown in FIG. 31, reading is performed from the photosensor cell 224. At this time, the same read pulse is simultaneously applied to the gate of the p-channel MOS transistor connected to the photosensor cell 224 '. However, this read pulse is a positive pulse, which causes the p-channel M
The OS transistor does not become conductive and has no effect on the photosensor cell 224 '.

As shown in FIG. 14, a negative pulse is applied to the wiring 10 in a state where the base potential of each optical sensor cell is changing according to the intensity of light. The p-channel MOS transistor is turned on by this negative pulse, and the base potential of the photosensor cell 224 'is
Assuming that the negative power supply voltage supplied to 23 is −V _SR ,
− (V _SR −V _TH ). Here, -V _TH is the threshold voltage of the pMOS transistor.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a main structure of an optical sensor cell according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ of the optical sensor cell of FIG. 1;

FIG. 3 is an equivalent circuit diagram of the photosensor cell of FIG.

FIG. 4 is an equivalent circuit diagram at the time of a read operation of the photosensor cell of FIGS. 1 to 3;

FIG. 5 is a graph showing a relationship between a read time and a read voltage of the photosensor cells of FIGS.

FIG. 6 is a graph showing a relationship between a storage voltage and a read time of the photosensor cells of FIGS. 1 to 3;

FIG. 7 is a graph showing a relationship between a bias voltage and a read time of the photosensor cells of FIGS.

FIG. 8 is an equivalent circuit diagram at the time of refresh operation of the photosensor cells of FIGS. 1 to 3;

FIG. 9 is a graph showing a relationship between a refresh time and a base potential of the photosensor cells of FIGS. 1 to 3;

FIG. 10 is a graph showing a relationship between a refresh time and a base potential of the photosensor cells of FIGS. 1 to 3;

FIG. 11 is a graph showing a relationship between a refresh time and a base potential of the photosensor cells of FIGS.

FIG. 12 is a circuit diagram of a photoelectric conversion device using the optical sensor cells shown in FIGS.

13 is a pulse timing chart of the photoelectric conversion device of FIG.

14 is a graph showing a potential distribution at each operation of the photoelectric conversion device in FIG.

15 is an equivalent circuit diagram related to an output signal of the photoelectric conversion device in FIG.

FIG. 16 is a graph showing an output voltage as a function of time from the moment when the photoelectric conversion device in FIG. 12 is turned on.

FIG. 17 is a circuit diagram illustrating another photoelectric conversion device.

FIG. 18 is a circuit diagram showing another photoelectric conversion device.

FIG. 19 is a circuit diagram showing another photoelectric conversion device.

FIG. 20 is a plan view for explaining a main structure of another photosensor cell according to the embodiment of the present invention.

21 is a circuit diagram of a photoelectric conversion device using the optical sensor cell shown in FIG.

FIG. 22 is a circuit diagram of a photoelectric conversion device using the optical sensor cell shown in FIG.

FIG. 23 is a sectional view illustrating an example of a method for manufacturing a photoelectric conversion device according to the present invention.

FIG. 24 is a cross-sectional view illustrating an example of a method for manufacturing a photoelectric conversion device according to the present invention.

FIG. 25 is a cross-sectional view illustrating an example of a method for manufacturing a photoelectric conversion device according to the present invention.

FIG. 26 is a sectional view illustrating an example of a method for manufacturing a photoelectric conversion device according to the present invention.

FIG. 27 is a sectional view illustrating an example of a method for manufacturing a photoelectric conversion device according to the present invention.

FIG. 28 is a cross-sectional view for illustrating one example of a method for manufacturing the photoelectric conversion device of the present invention.

FIG. 29 is a cross-sectional view illustrating an example of a method for manufacturing a photoelectric conversion device of the present invention.

FIG. 30 is a sectional view illustrating an example of a method for manufacturing a photoelectric conversion device according to the present invention.

FIG. 31 is a sectional view of an optical sensor cell according to an example of the present invention.

FIG. 32 is a sectional view taken along the line AA ′ of the optical sensor cell of FIG. 31.

FIG. 33 is a circuit configuration diagram of the photosensor cell of FIG. 31.

[Explanation of symbols]

1 silicon substrate, 2 PSG film, 3 insulating oxide film, 4 element isolation region, 5 n ⁻ region (collector region), 6 p region (base region), 7, 7 ′ n ⁺ region (emitter region), 8 wiring, 9 electrodes, 10
Wiring, 11n ⁺ region, 12 electrodes, 13 capacitor, 14 bipolar transistor, 15, 1
7 junction capacitance, 16,18 diode, 19,1
9 'contact, 20 light, 28 vertical lines,
30 light sensor cell, 31 horizontal line, 32
Vertical shift register, 33, 35 MOS transistor, 36, 37 terminal, 38 vertical line, 39
Horizontal shift register, 40 MOS transistors,
41 output lines, 42 MOS transistors,
43 terminal, 44 transistor, 44, 45 load resistance, 46 terminal, 47 terminal, 48 MOS transistor, 49 terminal, 61, 62, 63 section, 64 collector potential, 67 waveform, 80, 8
1 capacity, 82, 83 resistance, 84 current source, 10
0, 101, 102 horizontal shift registers, 111,
112 output lines, 138 vertical lines, 140
MOS transistor, 148 MOS transistor,
150, 150 'MOS capacitor, 152, 15
2 'photosensor cell, 202, 203 and 205 base potential, 220 p ⁺ regions, 222 and 225 lines, 251P ⁺ regions, 252 n ⁺ regions, 253
Wiring, 300 amorphous silicon, 302
Nitride film, 303 PSG film, 304 polysilicon, 305 PSG film, 306 interlayer insulating film.

Claims (1)

(57) [Claims] 1. A semiconductor device comprising: a base region made of a semiconductor of a first conductivity type; and an emitter and a collector region made of a semiconductor of a second conductivity type different from the first conductivity type. A transistor capable of accumulating carriers to be stored in the base region, and performing a storage operation, a read operation, and a refresh operation, wherein the impurity concentration of the base region decreases in a direction from the light incident surface toward the inside, When the impurity concentration at the light incident surface is N _AS and the impurity concentration at the interface with the collector region is N _Ai ,
The photoelectric conversion device, wherein the base region has an impurity concentration profile satisfying a relationship of N _AS / N _Ai > 3.